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media: i2c: imx415: Add more clock configurations

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Complete the list from "INCK Setting" section in IMX415-AAQR-C
(Rev. E19504, 2019/05/21). For consistency suffix all lane rate values by
UL, which is needed for 2376000000 anyway.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Alexander Stein 2024-01-17 08:39:36 +01:00 committed by Mauro Carvalho Chehab
parent d5df1c7f3f
commit b814b5b2ec
1 changed files with 260 additions and 5 deletions
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265
drivers/media/i2c/imx415.c
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@ -114,7 +114,7 @@ struct imx415_clk_params {
/* INCK Settings - includes all lane rate and INCK dependent registers */
static const struct imx415_clk_params imx415_clk_params[] = {
{
.lane_rate = 594000000,
.lane_rate = 594000000UL,
.inck = 27000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
@ -129,7 +129,37 @@ static const struct imx415_clk_params imx415_clk_params[] = {
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
},
{
.lane_rate = 720000000,
.lane_rate = 594000000UL,
.inck = 37125000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
.regs[2] = { IMX415_SYS_MODE, 0x7 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x24 },
.regs[5] = { IMX415_INCKSEL3, 0x080 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x24 },
.regs[8] = { IMX415_INCKSEL6, 0x0 },
.regs[9] = { IMX415_INCKSEL7, 0x1 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 },
},
{
.lane_rate = 594000000UL,
.inck = 74250000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
.regs[2] = { IMX415_SYS_MODE, 0x7 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x080 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x0 },
.regs[9] = { IMX415_INCKSEL7, 0x1 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
},
{
.lane_rate = 720000000UL,
.inck = 24000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
@ -144,7 +174,22 @@ static const struct imx415_clk_params imx415_clk_params[] = {
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
},
{
.lane_rate = 891000000,
.lane_rate = 720000000UL,
.inck = 72000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
.regs[2] = { IMX415_SYS_MODE, 0x9 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x0 },
.regs[9] = { IMX415_INCKSEL7, 0x1 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
},
{
.lane_rate = 891000000UL,
.inck = 27000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
@ -159,7 +204,37 @@ static const struct imx415_clk_params imx415_clk_params[] = {
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
},
{
.lane_rate = 1440000000,
.lane_rate = 891000000UL,
.inck = 37125000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
.regs[2] = { IMX415_SYS_MODE, 0x5 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x24 },
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x24 },
.regs[8] = { IMX415_INCKSEL6, 0x0 },
.regs[9] = { IMX415_INCKSEL7, 0x1 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
},
{
.lane_rate = 891000000UL,
.inck = 74250000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
.regs[2] = { IMX415_SYS_MODE, 0x5 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x0 },
.regs[9] = { IMX415_INCKSEL7, 0x1 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
},
{
.lane_rate = 1440000000UL,
.inck = 24000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
@ -174,7 +249,22 @@ static const struct imx415_clk_params imx415_clk_params[] = {
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
},
{
.lane_rate = 1485000000,
.lane_rate = 1440000000UL,
.inck = 72000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
.regs[2] = { IMX415_SYS_MODE, 0x8 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
},
{
.lane_rate = 1485000000UL,
.inck = 27000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
@ -188,6 +278,171 @@ static const struct imx415_clk_params imx415_clk_params[] = {
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
},
{
.lane_rate = 1485000000UL,
.inck = 37125000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
.regs[2] = { IMX415_SYS_MODE, 0x8 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x24 },
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x24 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
},
{
.lane_rate = 1485000000UL,
.inck = 74250000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
.regs[2] = { IMX415_SYS_MODE, 0x8 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
},
{
.lane_rate = 1782000000UL,
.inck = 27000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
.regs[2] = { IMX415_SYS_MODE, 0x4 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x23 },
.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
.regs[7] = { IMX415_INCKSEL5, 0x23 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
},
{
.lane_rate = 1782000000UL,
.inck = 37125000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
.regs[2] = { IMX415_SYS_MODE, 0x4 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x24 },
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x24 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
},
{
.lane_rate = 1782000000UL,
.inck = 74250000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
.regs[2] = { IMX415_SYS_MODE, 0x4 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
},
{
.lane_rate = 2079000000UL,
.inck = 27000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
.regs[2] = { IMX415_SYS_MODE, 0x2 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x23 },
.regs[5] = { IMX415_INCKSEL3, 0x0E7 },
.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
.regs[7] = { IMX415_INCKSEL5, 0x23 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
},
{
.lane_rate = 2079000000UL,
.inck = 37125000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
.regs[2] = { IMX415_SYS_MODE, 0x2 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x24 },
.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x24 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
},
{
.lane_rate = 2079000000UL,
.inck = 74250000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
.regs[2] = { IMX415_SYS_MODE, 0x2 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
},
{
.lane_rate = 2376000000UL,
.inck = 27000000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
.regs[2] = { IMX415_SYS_MODE, 0x0 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x23 },
.regs[5] = { IMX415_INCKSEL3, 0x108 },
.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
.regs[7] = { IMX415_INCKSEL5, 0x23 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
},
{
.lane_rate = 2376000000UL,
.inck = 37125000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
.regs[2] = { IMX415_SYS_MODE, 0x0 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x24 },
.regs[5] = { IMX415_INCKSEL3, 0x100 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x24 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
},
{
.lane_rate = 2376000000UL,
.inck = 74250000,
.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
.regs[2] = { IMX415_SYS_MODE, 0x0 },
.regs[3] = { IMX415_INCKSEL1, 0x00 },
.regs[4] = { IMX415_INCKSEL2, 0x28 },
.regs[5] = { IMX415_INCKSEL3, 0x100 },
.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
.regs[7] = { IMX415_INCKSEL5, 0x28 },
.regs[8] = { IMX415_INCKSEL6, 0x1 },
.regs[9] = { IMX415_INCKSEL7, 0x0 },
.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
},
};
/* all-pixel 2-lane 720 Mbps 15.74 Hz mode */