mirror of
https://github.com/torvalds/linux.git
synced 2024-11-11 14:42:24 +00:00
Reset controller updates for v5.5
This tag adds support for Meson SM1 ARB resets, Uniphier Pro5 USB3 resets, the Meson-A1 reset controller, SocFPGA Agilex resets, and Realtek RTD1195/RTD1295 resets. It adds some reset controller API keywords for get_maintainers.pl and makes a few remaining reset_control_ops const. Also included are a conversion of the Qualcomm device tree bindings to yaml and a few small kerneldoc improvements. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXbbwUxcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwEKeAP498UhJ8+GB8PUCpRIPAmFwjAON n+2EFHTn5Od08ueqqAEA4SH13tR5PJBo6G/J6KgLULUFts4Uc/Hb760/2ai3eQw= =eyHx -----END PGP SIGNATURE----- Merge tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux into arm/drivers Reset controller updates for v5.5 This tag adds support for Meson SM1 ARB resets, Uniphier Pro5 USB3 resets, the Meson-A1 reset controller, SocFPGA Agilex resets, and Realtek RTD1195/RTD1295 resets. It adds some reset controller API keywords for get_maintainers.pl and makes a few remaining reset_control_ops const. Also included are a conversion of the Qualcomm device tree bindings to yaml and a few small kerneldoc improvements. * tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux: reset: document (devm_)reset_control_get_optional variants reset: improve of_xlate documentation reset: simple: Add Realtek RTD1195/RTD1295 reset: simple: Keep alphabetical order MAINTAINERS: add reset controller framework keywords reset: zynqmp: Make reset_control_ops const reset: hisilicon: hi3660: Make reset_control_ops const reset: build simple reset controller driver for Agilex reset: add support for the Meson-A1 SoC Reset Controller dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller reset: uniphier-glue: Add Pro5 USB3 support dt-bindings: reset: pdc: Convert PDC Global bindings to yaml dt-bindings: reset: aoss: Convert AOSS reset bindings to yaml reset: Remove copy'n'paste redundancy in the comments reset: meson-audio-arb: add sm1 support reset: dt-bindings: meson: update arb bindings for sm1 Link: https://lore.kernel.org/r/ede6874508472d0917dca770ef80b90626b0f205.camel@pengutronix.de Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
b7f7a0b58f
@ -4,7 +4,8 @@ The Amlogic Audio ARB is a simple device which enables or
|
||||
disables the access of Audio FIFOs to DDR on AXG based SoC.
|
||||
|
||||
Required properties:
|
||||
- compatible: 'amlogic,meson-axg-audio-arb'
|
||||
- compatible: 'amlogic,meson-axg-audio-arb' or
|
||||
'amlogic,meson-sm1-audio-arb'
|
||||
- reg: physical base address of the controller and length of memory
|
||||
mapped region.
|
||||
- clocks: phandle to the fifo peripheral clock provided by the audio
|
||||
|
||||
@ -16,6 +16,7 @@ properties:
|
||||
- amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
|
||||
- amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
|
||||
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
|
||||
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -1,52 +0,0 @@
|
||||
Qualcomm AOSS Reset Controller
|
||||
======================================
|
||||
|
||||
This binding describes a reset-controller found on AOSS-CC (always on subsystem)
|
||||
for Qualcomm SDM845 SoCs.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be:
|
||||
"qcom,sdm845-aoss-cc"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: must specify the base address and size of the register
|
||||
space.
|
||||
|
||||
- #reset-cells:
|
||||
Usage: required
|
||||
Value type: <uint>
|
||||
Definition: must be 1; cell entry represents the reset index.
|
||||
|
||||
Example:
|
||||
|
||||
aoss_reset: reset-controller@c2a0000 {
|
||||
compatible = "qcom,sdm845-aoss-cc";
|
||||
reg = <0xc2a0000 0x31000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
|
||||
Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For list of all valid reset indicies see
|
||||
<dt-bindings/reset/qcom,sdm845-aoss.h>
|
||||
|
||||
Example:
|
||||
|
||||
modem-pil@4080000 {
|
||||
...
|
||||
|
||||
resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
|
||||
reset-names = "mss_restart";
|
||||
|
||||
...
|
||||
};
|
||||
47
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
Normal file
47
Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/qcom,aoss-reset.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm AOSS Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Sibi Sankar <sibis@codeaurora.org>
|
||||
|
||||
description:
|
||||
The bindings describe the reset-controller found on AOSS-CC (always on
|
||||
subsystem) for Qualcomm Technologies Inc SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: on SC7180 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sc7180-aoss-cc"
|
||||
- const: "qcom,sdm845-aoss-cc"
|
||||
|
||||
- description: on SDM845 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sdm845-aoss-cc"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
aoss_reset: reset-controller@c2a0000 {
|
||||
compatible = "qcom,sdm845-aoss-cc";
|
||||
reg = <0xc2a0000 0x31000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,52 +0,0 @@
|
||||
PDC Global
|
||||
======================================
|
||||
|
||||
This binding describes a reset-controller found on PDC-Global (Power Domain
|
||||
Controller) block for Qualcomm Technologies Inc SDM845 SoCs.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be:
|
||||
"qcom,sdm845-pdc-global"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: must specify the base address and size of the register
|
||||
space.
|
||||
|
||||
- #reset-cells:
|
||||
Usage: required
|
||||
Value type: <uint>
|
||||
Definition: must be 1; cell entry represents the reset index.
|
||||
|
||||
Example:
|
||||
|
||||
pdc_reset: reset-controller@b2e0000 {
|
||||
compatible = "qcom,sdm845-pdc-global";
|
||||
reg = <0xb2e0000 0x20000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
PDC reset clients
|
||||
======================================
|
||||
|
||||
Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For a list of all valid reset indices see
|
||||
<dt-bindings/reset/qcom,sdm845-pdc.h>
|
||||
|
||||
Example:
|
||||
|
||||
modem-pil@4080000 {
|
||||
...
|
||||
|
||||
resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
|
||||
reset-names = "pdc_reset";
|
||||
|
||||
...
|
||||
};
|
||||
47
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
Normal file
47
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm PDC Global
|
||||
|
||||
maintainers:
|
||||
- Sibi Sankar <sibis@codeaurora.org>
|
||||
|
||||
description:
|
||||
The bindings describes the reset-controller found on PDC-Global (Power Domain
|
||||
Controller) block for Qualcomm Technologies Inc SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: on SC7180 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sc7180-pdc-global"
|
||||
- const: "qcom,sdm845-pdc-global"
|
||||
|
||||
- description: on SDM845 SoCs the following compatibles must be specified
|
||||
items:
|
||||
- const: "qcom,sdm845-pdc-global"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pdc_reset: reset-controller@b2e0000 {
|
||||
compatible = "qcom,sdm845-pdc-global";
|
||||
reg = <0xb2e0000 0x20000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -130,6 +130,7 @@ this layer. These clocks and resets should be described in each property.
|
||||
Required properties:
|
||||
- compatible: Should be
|
||||
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
|
||||
"socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
|
||||
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
|
||||
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
|
||||
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
|
||||
@ -141,12 +142,12 @@ Required properties:
|
||||
- clocks: A list of phandles to the clock gate for the glue layer.
|
||||
According to the clock-names, appropriate clocks are required.
|
||||
- clock-names: Should contain
|
||||
"gio", "link" - for Pro4 SoC
|
||||
"gio", "link" - for Pro4 and Pro5 SoCs
|
||||
"link" - for others
|
||||
- resets: A list of phandles to the reset control for the glue layer.
|
||||
According to the reset-names, appropriate resets are required.
|
||||
- reset-names: Should contain
|
||||
"gio", "link" - for Pro4 SoC
|
||||
"gio", "link" - for Pro4 and Pro5 SoCs
|
||||
"link" - for others
|
||||
|
||||
Example:
|
||||
|
||||
@ -13872,6 +13872,7 @@ F: include/dt-bindings/reset/
|
||||
F: include/linux/reset.h
|
||||
F: include/linux/reset/
|
||||
F: include/linux/reset-controller.h
|
||||
K: \b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
|
||||
|
||||
RESTARTABLE SEQUENCES SUPPORT
|
||||
M: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
|
||||
|
||||
@ -129,7 +129,7 @@ config RESET_SCMI
|
||||
|
||||
config RESET_SIMPLE
|
||||
bool "Simple Reset Controller Driver" if COMPILE_TEST
|
||||
default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN || ARC
|
||||
default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
|
||||
help
|
||||
This enables a simple reset controller driver for reset lines that
|
||||
that can be asserted and deasserted by toggling bits in a contiguous,
|
||||
@ -138,10 +138,11 @@ config RESET_SIMPLE
|
||||
Currently this driver supports:
|
||||
- Altera SoCFPGAs
|
||||
- ASPEED BMC SoCs
|
||||
- Bitmain BM1880 SoC
|
||||
- Realtek SoCs
|
||||
- RCC reset controller in STM32 MCUs
|
||||
- Allwinner SoCs
|
||||
- ZTE's zx2967 family
|
||||
- Bitmain BM1880 SoC
|
||||
|
||||
config RESET_STM32MP157
|
||||
bool "STM32MP157 Reset Driver" if COMPILE_TEST
|
||||
|
||||
@ -78,8 +78,10 @@ static const char *rcdev_name(struct reset_controller_dev *rcdev)
|
||||
* @reset_spec: reset line specifier as found in the device tree
|
||||
* @flags: a flags pointer to fill in (optional)
|
||||
*
|
||||
* This simple translation function should be used for reset controllers
|
||||
* with 1:1 mapping, where reset lines can be indexed by number without gaps.
|
||||
* This static translation function is used by default if of_xlate in
|
||||
* :c:type:`reset_controller_dev` is not set. It is useful for all reset
|
||||
* controllers with 1:1 mapping, where reset lines can be indexed by number
|
||||
* without gaps.
|
||||
*/
|
||||
static int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
@ -334,7 +336,6 @@ EXPORT_SYMBOL_GPL(reset_control_reset);
|
||||
* internal state to be reset, but must be prepared for this to happen.
|
||||
* Consumers must not use reset_control_reset on shared reset lines when
|
||||
* reset_control_(de)assert has been used.
|
||||
* return 0.
|
||||
*
|
||||
* If rstc is NULL it is an optional reset and the function will just
|
||||
* return 0.
|
||||
@ -393,7 +394,6 @@ EXPORT_SYMBOL_GPL(reset_control_assert);
|
||||
* After calling this function, the reset is guaranteed to be deasserted.
|
||||
* Consumers must not use reset_control_reset on shared reset lines when
|
||||
* reset_control_(de)assert has been used.
|
||||
* return 0.
|
||||
*
|
||||
* If rstc is NULL it is an optional reset and the function will just
|
||||
* return 0.
|
||||
|
||||
@ -56,7 +56,7 @@ static int hi3660_reset_dev(struct reset_controller_dev *rcdev,
|
||||
return hi3660_reset_deassert(rcdev, idx);
|
||||
}
|
||||
|
||||
static struct reset_control_ops hi3660_reset_ops = {
|
||||
static const struct reset_control_ops hi3660_reset_ops = {
|
||||
.reset = hi3660_reset_dev,
|
||||
.assert = hi3660_reset_assert,
|
||||
.deassert = hi3660_reset_deassert,
|
||||
|
||||
@ -19,6 +19,11 @@ struct meson_audio_arb_data {
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
struct meson_audio_arb_match_data {
|
||||
const unsigned int *reset_bits;
|
||||
unsigned int reset_num;
|
||||
};
|
||||
|
||||
#define ARB_GENERAL_BIT 31
|
||||
|
||||
static const unsigned int axg_audio_arb_reset_bits[] = {
|
||||
@ -30,6 +35,27 @@ static const unsigned int axg_audio_arb_reset_bits[] = {
|
||||
[AXG_ARB_FRDDR_C] = 6,
|
||||
};
|
||||
|
||||
static const struct meson_audio_arb_match_data axg_audio_arb_match = {
|
||||
.reset_bits = axg_audio_arb_reset_bits,
|
||||
.reset_num = ARRAY_SIZE(axg_audio_arb_reset_bits),
|
||||
};
|
||||
|
||||
static const unsigned int sm1_audio_arb_reset_bits[] = {
|
||||
[AXG_ARB_TODDR_A] = 0,
|
||||
[AXG_ARB_TODDR_B] = 1,
|
||||
[AXG_ARB_TODDR_C] = 2,
|
||||
[AXG_ARB_FRDDR_A] = 4,
|
||||
[AXG_ARB_FRDDR_B] = 5,
|
||||
[AXG_ARB_FRDDR_C] = 6,
|
||||
[AXG_ARB_TODDR_D] = 3,
|
||||
[AXG_ARB_FRDDR_D] = 7,
|
||||
};
|
||||
|
||||
static const struct meson_audio_arb_match_data sm1_audio_arb_match = {
|
||||
.reset_bits = sm1_audio_arb_reset_bits,
|
||||
.reset_num = ARRAY_SIZE(sm1_audio_arb_reset_bits),
|
||||
};
|
||||
|
||||
static int meson_audio_arb_update(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
@ -82,7 +108,13 @@ static const struct reset_control_ops meson_audio_arb_rstc_ops = {
|
||||
};
|
||||
|
||||
static const struct of_device_id meson_audio_arb_of_match[] = {
|
||||
{ .compatible = "amlogic,meson-axg-audio-arb", },
|
||||
{
|
||||
.compatible = "amlogic,meson-axg-audio-arb",
|
||||
.data = &axg_audio_arb_match,
|
||||
}, {
|
||||
.compatible = "amlogic,meson-sm1-audio-arb",
|
||||
.data = &sm1_audio_arb_match,
|
||||
},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, meson_audio_arb_of_match);
|
||||
@ -104,10 +136,15 @@ static int meson_audio_arb_remove(struct platform_device *pdev)
|
||||
static int meson_audio_arb_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct meson_audio_arb_match_data *data;
|
||||
struct meson_audio_arb_data *arb;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
data = of_device_get_match_data(dev);
|
||||
if (!data)
|
||||
return -EINVAL;
|
||||
|
||||
arb = devm_kzalloc(dev, sizeof(*arb), GFP_KERNEL);
|
||||
if (!arb)
|
||||
return -ENOMEM;
|
||||
@ -126,8 +163,8 @@ static int meson_audio_arb_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(arb->regs);
|
||||
|
||||
spin_lock_init(&arb->lock);
|
||||
arb->reset_bits = axg_audio_arb_reset_bits;
|
||||
arb->rstc.nr_resets = ARRAY_SIZE(axg_audio_arb_reset_bits);
|
||||
arb->reset_bits = data->reset_bits;
|
||||
arb->rstc.nr_resets = data->reset_num;
|
||||
arb->rstc.ops = &meson_audio_arb_rstc_ops;
|
||||
arb->rstc.of_node = dev->of_node;
|
||||
arb->rstc.owner = THIS_MODULE;
|
||||
|
||||
@ -15,12 +15,16 @@
|
||||
#include <linux/types.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#define REG_COUNT 8
|
||||
#define BITS_PER_REG 32
|
||||
#define LEVEL_OFFSET 0x7c
|
||||
|
||||
struct meson_reset_param {
|
||||
int reg_count;
|
||||
int level_offset;
|
||||
};
|
||||
|
||||
struct meson_reset {
|
||||
void __iomem *reg_base;
|
||||
const struct meson_reset_param *param;
|
||||
struct reset_controller_dev rcdev;
|
||||
spinlock_t lock;
|
||||
};
|
||||
@ -46,10 +50,12 @@ static int meson_reset_level(struct reset_controller_dev *rcdev,
|
||||
container_of(rcdev, struct meson_reset, rcdev);
|
||||
unsigned int bank = id / BITS_PER_REG;
|
||||
unsigned int offset = id % BITS_PER_REG;
|
||||
void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
|
||||
void __iomem *reg_addr;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(reg_addr);
|
||||
@ -81,10 +87,21 @@ static const struct reset_control_ops meson_reset_ops = {
|
||||
.deassert = meson_reset_deassert,
|
||||
};
|
||||
|
||||
static const struct meson_reset_param meson8b_param = {
|
||||
.reg_count = 8,
|
||||
.level_offset = 0x7c,
|
||||
};
|
||||
|
||||
static const struct meson_reset_param meson_a1_param = {
|
||||
.reg_count = 3,
|
||||
.level_offset = 0x40,
|
||||
};
|
||||
|
||||
static const struct of_device_id meson_reset_dt_ids[] = {
|
||||
{ .compatible = "amlogic,meson8b-reset" },
|
||||
{ .compatible = "amlogic,meson-gxbb-reset" },
|
||||
{ .compatible = "amlogic,meson-axg-reset" },
|
||||
{ .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
|
||||
{ .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
|
||||
{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
|
||||
{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
@ -102,12 +119,16 @@ static int meson_reset_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(data->reg_base))
|
||||
return PTR_ERR(data->reg_base);
|
||||
|
||||
data->param = of_device_get_match_data(&pdev->dev);
|
||||
if (!data->param)
|
||||
return -ENODEV;
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
|
||||
data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
|
||||
data->rcdev.ops = &meson_reset_ops;
|
||||
data->rcdev.of_node = pdev->dev.of_node;
|
||||
|
||||
|
||||
@ -140,6 +140,10 @@ static const struct of_device_id uniphier_glue_reset_match[] = {
|
||||
.compatible = "socionext,uniphier-pro4-usb3-reset",
|
||||
.data = &uniphier_pro4_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,uniphier-pro5-usb3-reset",
|
||||
.data = &uniphier_pro4_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,uniphier-pxs2-usb3-reset",
|
||||
.data = &uniphier_pxs2_data,
|
||||
|
||||
@ -64,7 +64,7 @@ static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
|
||||
PM_RESET_ACTION_PULSE);
|
||||
}
|
||||
|
||||
static struct reset_control_ops zynqmp_reset_ops = {
|
||||
static const struct reset_control_ops zynqmp_reset_ops = {
|
||||
.reset = zynqmp_reset_reset,
|
||||
.assert = zynqmp_reset_assert,
|
||||
.deassert = zynqmp_reset_deassert,
|
||||
|
||||
74
include/dt-bindings/reset/amlogic,meson-a1-reset.h
Normal file
74
include/dt-bindings/reset/amlogic,meson-a1-reset.h
Normal file
@ -0,0 +1,74 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
|
||||
|
||||
/* RESET0 */
|
||||
/* 0 */
|
||||
#define RESET_AM2AXI_VAD 1
|
||||
/* 2-3 */
|
||||
#define RESET_PSRAM 4
|
||||
#define RESET_PAD_CTRL 5
|
||||
/* 6 */
|
||||
#define RESET_TEMP_SENSOR 7
|
||||
#define RESET_AM2AXI_DEV 8
|
||||
/* 9 */
|
||||
#define RESET_SPICC_A 10
|
||||
#define RESET_MSR_CLK 11
|
||||
#define RESET_AUDIO 12
|
||||
#define RESET_ANALOG_CTRL 13
|
||||
#define RESET_SAR_ADC 14
|
||||
#define RESET_AUDIO_VAD 15
|
||||
#define RESET_CEC 16
|
||||
#define RESET_PWM_EF 17
|
||||
#define RESET_PWM_CD 18
|
||||
#define RESET_PWM_AB 19
|
||||
/* 20 */
|
||||
#define RESET_IR_CTRL 21
|
||||
#define RESET_I2C_S_A 22
|
||||
/* 23 */
|
||||
#define RESET_I2C_M_D 24
|
||||
#define RESET_I2C_M_C 25
|
||||
#define RESET_I2C_M_B 26
|
||||
#define RESET_I2C_M_A 27
|
||||
#define RESET_I2C_PROD_AHB 28
|
||||
#define RESET_I2C_PROD 29
|
||||
/* 30-31 */
|
||||
|
||||
/* RESET1 */
|
||||
#define RESET_ACODEC 32
|
||||
#define RESET_DMA 33
|
||||
#define RESET_SD_EMMC_A 34
|
||||
/* 35 */
|
||||
#define RESET_USBCTRL 36
|
||||
/* 37 */
|
||||
#define RESET_USBPHY 38
|
||||
/* 39-41 */
|
||||
#define RESET_RSA 42
|
||||
#define RESET_DMC 43
|
||||
/* 44 */
|
||||
#define RESET_IRQ_CTRL 45
|
||||
/* 46 */
|
||||
#define RESET_NIC_VAD 47
|
||||
#define RESET_NIC_AXI 48
|
||||
#define RESET_RAMA 49
|
||||
#define RESET_RAMB 50
|
||||
/* 51-52 */
|
||||
#define RESET_ROM 53
|
||||
#define RESET_SPIFC 54
|
||||
#define RESET_GIC 55
|
||||
#define RESET_UART_C 56
|
||||
#define RESET_UART_B 57
|
||||
#define RESET_UART_A 58
|
||||
#define RESET_OSC_RING 59
|
||||
/* 60-63 */
|
||||
|
||||
/* RESET2 */
|
||||
/* 64-95 */
|
||||
|
||||
#endif
|
||||
@ -13,5 +13,7 @@
|
||||
#define AXG_ARB_FRDDR_A 3
|
||||
#define AXG_ARB_FRDDR_B 4
|
||||
#define AXG_ARB_FRDDR_C 5
|
||||
#define AXG_ARB_TODDR_D 6
|
||||
#define AXG_ARB_FRDDR_D 7
|
||||
|
||||
#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
|
||||
|
||||
@ -62,7 +62,8 @@ struct reset_control_lookup {
|
||||
* @of_node: corresponding device tree node as phandle target
|
||||
* @of_reset_n_cells: number of cells in reset line specifiers
|
||||
* @of_xlate: translation function to translate from specifier as found in the
|
||||
* device tree to id as given to the reset control ops
|
||||
* device tree to id as given to the reset control ops, defaults
|
||||
* to :c:func:`of_reset_simple_xlate`.
|
||||
* @nr_resets: number of reset controls in this reset controller device
|
||||
*/
|
||||
struct reset_controller_dev {
|
||||
|
||||
@ -203,12 +203,34 @@ static inline struct reset_control *reset_control_get_shared(
|
||||
return __reset_control_get(dev, id, 0, true, false, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* reset_control_get_optional_exclusive - optional reset_control_get_exclusive()
|
||||
* @dev: device to be reset by the controller
|
||||
* @id: reset line name
|
||||
*
|
||||
* Optional variant of reset_control_get_exclusive(). If the requested reset
|
||||
* is not specified in the device tree, this function returns NULL instead of
|
||||
* an error.
|
||||
*
|
||||
* See reset_control_get_exclusive() for more information.
|
||||
*/
|
||||
static inline struct reset_control *reset_control_get_optional_exclusive(
|
||||
struct device *dev, const char *id)
|
||||
{
|
||||
return __reset_control_get(dev, id, 0, false, true, true);
|
||||
}
|
||||
|
||||
/**
|
||||
* reset_control_get_optional_shared - optional reset_control_get_shared()
|
||||
* @dev: device to be reset by the controller
|
||||
* @id: reset line name
|
||||
*
|
||||
* Optional variant of reset_control_get_shared(). If the requested reset
|
||||
* is not specified in the device tree, this function returns NULL instead of
|
||||
* an error.
|
||||
*
|
||||
* See reset_control_get_shared() for more information.
|
||||
*/
|
||||
static inline struct reset_control *reset_control_get_optional_shared(
|
||||
struct device *dev, const char *id)
|
||||
{
|
||||
@ -354,12 +376,36 @@ static inline struct reset_control *devm_reset_control_get_shared(
|
||||
return __devm_reset_control_get(dev, id, 0, true, false, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_reset_control_get_optional_exclusive - resource managed
|
||||
* reset_control_get_optional_exclusive()
|
||||
* @dev: device to be reset by the controller
|
||||
* @id: reset line name
|
||||
*
|
||||
* Managed reset_control_get_optional_exclusive(). For reset controllers
|
||||
* returned from this function, reset_control_put() is called automatically on
|
||||
* driver detach.
|
||||
*
|
||||
* See reset_control_get_optional_exclusive() for more information.
|
||||
*/
|
||||
static inline struct reset_control *devm_reset_control_get_optional_exclusive(
|
||||
struct device *dev, const char *id)
|
||||
{
|
||||
return __devm_reset_control_get(dev, id, 0, false, true, true);
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_reset_control_get_optional_shared - resource managed
|
||||
* reset_control_get_optional_shared()
|
||||
* @dev: device to be reset by the controller
|
||||
* @id: reset line name
|
||||
*
|
||||
* Managed reset_control_get_optional_shared(). For reset controllers returned
|
||||
* from this function, reset_control_put() is called automatically on driver
|
||||
* detach.
|
||||
*
|
||||
* See reset_control_get_optional_shared() for more information.
|
||||
*/
|
||||
static inline struct reset_control *devm_reset_control_get_optional_shared(
|
||||
struct device *dev, const char *id)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user