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soc/tegra: Add generic PM domain support
Implements generic PM domain support on top of the existing Tegra power- gate API. Drivers are thus allowed to move away from the Tegra-specific API and towards using generic power domains directly. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXI3unAAoJEN0jrNd/PrOhdPIP/jOgS5Qf1u8QelFvPbsXouRf xpBy9sa43oow8f+0RVjTrsWDikjniCYcGDPZbfgmXEN5sWYK2xBIZeaMysGezPXS /g9VnxU0HZsQ+5AOWHS/vxYLfB9Q6g3w4P7XDDzKmJ9mFaLeyNR4ulGWwLxpeF/1 au38f/dXgjU9I+NwXJWhTEspQrXAshIwp6lsQkjcpLmAMeFBOjB7c92uTYmVXI9F XtGcpGmIqDwRaieY1lqE0iGUMgox2XG2bKgNuwZ+Eng+ICz2ACuGfyH7hwCeWJpK HByxL83aA9a+G8KIsPZgJYTCuQA7UVYjWp5A5UqpuhsP7Da4EagX3Bdvcwqy/sgk rcLNSTuksbJyHT/yQO5cj9lPrdFckSglChZlSRX1J5FhQN2xHw/1CmfDgPmZ1Htt D+66iLm3lJ+SZlwaZToofU89GYRc+GoZVPQrMBMCwTIBcYf6ACtG7hYIB6JrxHJg xyiSbDKRYyHBWHoL534G2S8xtnTjMHG1RLD2SoI49Qsa9OTmJz50NainElPi2DX5 266zz87Fa+5WePEp0NjBIJ0Hgq4uoMJFpvkG2pzODb2fwHxzW7E/KB6pAV9/+1EZ F+sPDHUnzTSLx76h7vs1v4ye9TXrcuKXXnhU7YBm6eWCgeM3GOf6V8u7z6BQDxxT rAYhbGOeeAiORGdMUo4h =oeBF -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.7-genpd' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Merge "soc/tegra: Add generic PM domain support" from Thierry Reding: Implements generic PM domain support on top of the existing Tegra power- gate API. Drivers are thus allowed to move away from the Tegra-specific API and towards using generic power domains directly. * tag 'tegra-for-4.7-genpd' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Add generic PM domain support dt-bindings: Add power domain info for NVIDIA PMC
This commit is contained in:
Arnd Bergmann
commit
b7dcc6d01f
@ -1,5 +1,7 @@
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NVIDIA Tegra Power Management Controller (PMC)
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== Power Management Controller Node ==
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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@ -70,6 +72,11 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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Optional nodes:
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- powergates : This node contains a hierarchy of power domain nodes, which
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should match the powergates on the Tegra SoC. See "Powergate
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Nodes" below.
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Example:
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/ SoC dts including file
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@ -115,3 +122,76 @@ pmc@7000f400 {
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};
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...
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};
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== Powergate Nodes ==
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Each of the powergate nodes represents a power-domain on the Tegra SoC
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that can be power-gated by the Tegra PMC. The name of the powergate node
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should be one of the below. Note that not every powergate is applicable
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to all Tegra devices and the following list shows which powergates are
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applicable to which devices. Please refer to the Tegra TRM for more
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details on the various powergates.
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Name Description Devices Applicable
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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Required properties:
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- clocks: Must contain an entry for each clock required by the PMC for
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controlling a power-gate. See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each reset required by the PMC for
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controlling a power-gate. See ../reset/reset.txt for details.
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- #power-domain-cells: Must be 0.
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Example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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powergates {
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pd_audio: aud {
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clocks = <&tegra_car TEGRA210_CLK_APE>,
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<&tegra_car TEGRA210_CLK_APB2APE>;
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resets = <&tegra_car 198>;
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#power-domain-cells = <0>;
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};
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};
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};
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== Powergate Clients ==
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Hardware blocks belonging to a power domain should contain a "power-domains"
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property that is a phandle pointing to the corresponding powergate node.
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Example:
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adma: adma@702e2000 {
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...
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power-domains = <&pd_audio>;
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...
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};
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@ -31,10 +31,13 @@
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/reboot.h>
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#include <linux/reset.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <soc/tegra/common.h>
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@ -102,6 +105,16 @@
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#define GPU_RG_CNTRL 0x2d4
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struct tegra_powergate {
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struct generic_pm_domain genpd;
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struct tegra_pmc *pmc;
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unsigned int id;
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struct clk **clks;
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unsigned int num_clks;
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struct reset_control **resets;
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unsigned int num_resets;
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};
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struct tegra_pmc_soc {
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unsigned int num_powergates;
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const char *const *powergates;
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@ -132,6 +145,7 @@ struct tegra_pmc_soc {
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* @cpu_pwr_good_en: CPU power good signal is enabled
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* @lp0_vec_phys: physical base address of the LP0 warm boot code
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* @lp0_vec_size: size of the LP0 warm boot code
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* @powergates_available: Bitmap of available power gates
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* @powergates_lock: mutex for power gate register access
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*/
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struct tegra_pmc {
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@ -156,6 +170,7 @@ struct tegra_pmc {
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bool cpu_pwr_good_en;
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u32 lp0_vec_phys;
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u32 lp0_vec_size;
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DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
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struct mutex powergates_lock;
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};
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@ -165,6 +180,12 @@ static struct tegra_pmc *pmc = &(struct tegra_pmc) {
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.suspend_mode = TEGRA_SUSPEND_NONE,
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};
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static inline struct tegra_powergate *
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to_powergate(struct generic_pm_domain *domain)
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{
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return container_of(domain, struct tegra_powergate, genpd);
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}
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static u32 tegra_pmc_readl(unsigned long offset)
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{
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return readl(pmc->base + offset);
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@ -188,6 +209,31 @@ static inline bool tegra_powergate_is_valid(int id)
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return (pmc->soc && pmc->soc->powergates[id]);
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}
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static inline bool tegra_powergate_is_available(int id)
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{
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return test_bit(id, pmc->powergates_available);
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}
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static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
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{
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unsigned int i;
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if (!pmc || !pmc->soc || !name)
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return -EINVAL;
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for (i = 0; i < pmc->soc->num_powergates; i++) {
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if (!tegra_powergate_is_valid(i))
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continue;
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if (!strcmp(name, pmc->soc->powergates[i]))
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return i;
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}
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dev_err(pmc->dev, "powergate %s not found\n", name);
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return -ENODEV;
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}
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/**
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* tegra_powergate_set() - set the state of a partition
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* @id: partition ID
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@ -218,60 +264,10 @@ static int tegra_powergate_set(unsigned int id, bool new_state)
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return err;
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}
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/**
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* tegra_powergate_power_on() - power on partition
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* @id: partition ID
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*/
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int tegra_powergate_power_on(unsigned int id)
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{
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if (!tegra_powergate_is_valid(id))
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return -EINVAL;
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return tegra_powergate_set(id, true);
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}
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/**
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* tegra_powergate_power_off() - power off partition
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* @id: partition ID
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*/
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int tegra_powergate_power_off(unsigned int id)
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{
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if (!tegra_powergate_is_valid(id))
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return -EINVAL;
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return tegra_powergate_set(id, false);
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}
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EXPORT_SYMBOL(tegra_powergate_power_off);
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/**
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* tegra_powergate_is_powered() - check if partition is powered
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* @id: partition ID
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*/
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int tegra_powergate_is_powered(unsigned int id)
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{
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int status;
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if (!tegra_powergate_is_valid(id))
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return -EINVAL;
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mutex_lock(&pmc->powergates_lock);
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status = tegra_powergate_state(id);
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mutex_unlock(&pmc->powergates_lock);
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return status;
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}
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/**
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* tegra_powergate_remove_clamping() - remove power clamps for partition
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* @id: partition ID
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*/
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int tegra_powergate_remove_clamping(unsigned int id)
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static int __tegra_powergate_remove_clamping(unsigned int id)
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{
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u32 mask;
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if (!tegra_powergate_is_valid(id))
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return -EINVAL;
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mutex_lock(&pmc->powergates_lock);
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/*
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@ -303,6 +299,231 @@ out:
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return 0;
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}
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static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
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{
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unsigned int i;
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for (i = 0; i < pg->num_clks; i++)
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clk_disable_unprepare(pg->clks[i]);
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}
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static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
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{
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unsigned int i;
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int err;
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for (i = 0; i < pg->num_clks; i++) {
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err = clk_prepare_enable(pg->clks[i]);
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if (err)
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goto out;
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}
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return 0;
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out:
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while (i--)
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clk_disable_unprepare(pg->clks[i]);
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return err;
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}
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static int tegra_powergate_reset_assert(struct tegra_powergate *pg)
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{
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unsigned int i;
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int err;
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for (i = 0; i < pg->num_resets; i++) {
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err = reset_control_assert(pg->resets[i]);
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if (err)
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return err;
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}
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return 0;
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}
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static int tegra_powergate_reset_deassert(struct tegra_powergate *pg)
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{
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unsigned int i;
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int err;
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for (i = 0; i < pg->num_resets; i++) {
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err = reset_control_deassert(pg->resets[i]);
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if (err)
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return err;
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}
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return 0;
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}
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static int tegra_powergate_power_up(struct tegra_powergate *pg,
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bool disable_clocks)
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{
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int err;
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err = tegra_powergate_reset_assert(pg);
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if (err)
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return err;
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usleep_range(10, 20);
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err = tegra_powergate_set(pg->id, true);
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if (err < 0)
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return err;
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usleep_range(10, 20);
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err = tegra_powergate_enable_clocks(pg);
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if (err)
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goto disable_clks;
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usleep_range(10, 20);
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err = __tegra_powergate_remove_clamping(pg->id);
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if (err)
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goto disable_clks;
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usleep_range(10, 20);
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err = tegra_powergate_reset_deassert(pg);
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if (err)
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goto powergate_off;
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usleep_range(10, 20);
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if (disable_clocks)
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tegra_powergate_disable_clocks(pg);
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return 0;
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disable_clks:
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tegra_powergate_disable_clocks(pg);
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usleep_range(10, 20);
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powergate_off:
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tegra_powergate_set(pg->id, false);
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return err;
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}
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static int tegra_powergate_power_down(struct tegra_powergate *pg)
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{
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int err;
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err = tegra_powergate_enable_clocks(pg);
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if (err)
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return err;
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usleep_range(10, 20);
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err = tegra_powergate_reset_assert(pg);
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if (err)
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goto disable_clks;
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usleep_range(10, 20);
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tegra_powergate_disable_clocks(pg);
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usleep_range(10, 20);
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err = tegra_powergate_set(pg->id, false);
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if (err)
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goto assert_resets;
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return 0;
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assert_resets:
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tegra_powergate_enable_clocks(pg);
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usleep_range(10, 20);
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tegra_powergate_reset_deassert(pg);
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usleep_range(10, 20);
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disable_clks:
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tegra_powergate_disable_clocks(pg);
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return err;
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}
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static int tegra_genpd_power_on(struct generic_pm_domain *domain)
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{
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struct tegra_powergate *pg = to_powergate(domain);
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struct tegra_pmc *pmc = pg->pmc;
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int err;
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err = tegra_powergate_power_up(pg, true);
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if (err)
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dev_err(pmc->dev, "failed to turn on PM domain %s: %d\n",
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pg->genpd.name, err);
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return err;
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}
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static int tegra_genpd_power_off(struct generic_pm_domain *domain)
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{
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struct tegra_powergate *pg = to_powergate(domain);
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struct tegra_pmc *pmc = pg->pmc;
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int err;
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err = tegra_powergate_power_down(pg);
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if (err)
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dev_err(pmc->dev, "failed to turn off PM domain %s: %d\n",
|
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pg->genpd.name, err);
|
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|
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return err;
|
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}
|
||||
|
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/**
|
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* tegra_powergate_power_on() - power on partition
|
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* @id: partition ID
|
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*/
|
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int tegra_powergate_power_on(unsigned int id)
|
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{
|
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if (!tegra_powergate_is_available(id))
|
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return -EINVAL;
|
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|
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return tegra_powergate_set(id, true);
|
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}
|
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|
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/**
|
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* tegra_powergate_power_off() - power off partition
|
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* @id: partition ID
|
||||
*/
|
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int tegra_powergate_power_off(unsigned int id)
|
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{
|
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if (!tegra_powergate_is_available(id))
|
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return -EINVAL;
|
||||
|
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return tegra_powergate_set(id, false);
|
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}
|
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EXPORT_SYMBOL(tegra_powergate_power_off);
|
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|
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/**
|
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* tegra_powergate_is_powered() - check if partition is powered
|
||||
* @id: partition ID
|
||||
*/
|
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int tegra_powergate_is_powered(unsigned int id)
|
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{
|
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int status;
|
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|
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if (!tegra_powergate_is_valid(id))
|
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return -EINVAL;
|
||||
|
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mutex_lock(&pmc->powergates_lock);
|
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status = tegra_powergate_state(id);
|
||||
mutex_unlock(&pmc->powergates_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* tegra_powergate_remove_clamping() - remove power clamps for partition
|
||||
* @id: partition ID
|
||||
*/
|
||||
int tegra_powergate_remove_clamping(unsigned int id)
|
||||
{
|
||||
if (!tegra_powergate_is_available(id))
|
||||
return -EINVAL;
|
||||
|
||||
return __tegra_powergate_remove_clamping(id);
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_powergate_remove_clamping);
|
||||
|
||||
/**
|
||||
@ -316,35 +537,20 @@ EXPORT_SYMBOL(tegra_powergate_remove_clamping);
|
||||
int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
|
||||
struct reset_control *rst)
|
||||
{
|
||||
int ret;
|
||||
struct tegra_powergate pg;
|
||||
int err;
|
||||
|
||||
reset_control_assert(rst);
|
||||
pg.id = id;
|
||||
pg.clks = &clk;
|
||||
pg.num_clks = 1;
|
||||
pg.resets = &rst;
|
||||
pg.num_resets = 1;
|
||||
|
||||
ret = tegra_powergate_power_on(id);
|
||||
if (ret)
|
||||
goto err_power;
|
||||
err = tegra_powergate_power_up(&pg, false);
|
||||
if (err)
|
||||
pr_err("failed to turn on partition %d: %d\n", id, err);
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
usleep_range(10, 20);
|
||||
|
||||
ret = tegra_powergate_remove_clamping(id);
|
||||
if (ret)
|
||||
goto err_clamp;
|
||||
|
||||
usleep_range(10, 20);
|
||||
reset_control_deassert(rst);
|
||||
|
||||
return 0;
|
||||
|
||||
err_clamp:
|
||||
clk_disable_unprepare(clk);
|
||||
err_clk:
|
||||
tegra_powergate_power_off(id);
|
||||
err_power:
|
||||
return ret;
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
|
||||
|
||||
@ -486,6 +692,155 @@ static int tegra_powergate_debugfs_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned int i, count;
|
||||
int err;
|
||||
|
||||
count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
|
||||
if (count == 0)
|
||||
return -ENODEV;
|
||||
|
||||
pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
|
||||
if (!pg->clks)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
pg->clks[i] = of_clk_get(np, i);
|
||||
if (IS_ERR(pg->clks[i])) {
|
||||
err = PTR_ERR(pg->clks[i]);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
pg->num_clks = count;
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
while (i--)
|
||||
clk_put(pg->clks[i]);
|
||||
kfree(pg->clks);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct reset_control *rst;
|
||||
unsigned int i, count;
|
||||
int err;
|
||||
|
||||
count = of_count_phandle_with_args(np, "resets", "#reset-cells");
|
||||
if (count == 0)
|
||||
return -ENODEV;
|
||||
|
||||
pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL);
|
||||
if (!pg->resets)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
pg->resets[i] = of_reset_control_get_by_index(np, i);
|
||||
if (IS_ERR(pg->resets[i])) {
|
||||
err = PTR_ERR(pg->resets[i]);
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
pg->num_resets = count;
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
while (i--)
|
||||
reset_control_put(pg->resets[i]);
|
||||
kfree(pg->resets);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
|
||||
{
|
||||
struct tegra_powergate *pg;
|
||||
bool off;
|
||||
int id;
|
||||
|
||||
pg = kzalloc(sizeof(*pg), GFP_KERNEL);
|
||||
if (!pg)
|
||||
goto error;
|
||||
|
||||
id = tegra_powergate_lookup(pmc, np->name);
|
||||
if (id < 0)
|
||||
goto free_mem;
|
||||
|
||||
/*
|
||||
* Clear the bit for this powergate so it cannot be managed
|
||||
* directly via the legacy APIs for controlling powergates.
|
||||
*/
|
||||
clear_bit(id, pmc->powergates_available);
|
||||
|
||||
pg->id = id;
|
||||
pg->genpd.name = np->name;
|
||||
pg->genpd.power_off = tegra_genpd_power_off;
|
||||
pg->genpd.power_on = tegra_genpd_power_on;
|
||||
pg->pmc = pmc;
|
||||
|
||||
if (tegra_powergate_of_get_clks(pg, np))
|
||||
goto set_available;
|
||||
|
||||
if (tegra_powergate_of_get_resets(pg, np))
|
||||
goto remove_clks;
|
||||
|
||||
off = !tegra_powergate_is_powered(pg->id);
|
||||
|
||||
pm_genpd_init(&pg->genpd, NULL, off);
|
||||
|
||||
if (of_genpd_add_provider_simple(np, &pg->genpd))
|
||||
goto remove_resets;
|
||||
|
||||
dev_dbg(pmc->dev, "added power domain %s\n", pg->genpd.name);
|
||||
|
||||
return;
|
||||
|
||||
remove_resets:
|
||||
while (pg->num_resets--)
|
||||
reset_control_put(pg->resets[pg->num_resets]);
|
||||
kfree(pg->resets);
|
||||
|
||||
remove_clks:
|
||||
while (pg->num_clks--)
|
||||
clk_put(pg->clks[pg->num_clks]);
|
||||
kfree(pg->clks);
|
||||
|
||||
set_available:
|
||||
set_bit(id, pmc->powergates_available);
|
||||
|
||||
free_mem:
|
||||
kfree(pg);
|
||||
|
||||
error:
|
||||
dev_err(pmc->dev, "failed to create power domain for %s\n", np->name);
|
||||
}
|
||||
|
||||
static void tegra_powergate_init(struct tegra_pmc *pmc)
|
||||
{
|
||||
struct device_node *np, *child;
|
||||
|
||||
np = of_get_child_by_name(pmc->dev->of_node, "powergates");
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
for_each_child_of_node(np, child) {
|
||||
tegra_powergate_add(pmc, child);
|
||||
of_node_put(child);
|
||||
}
|
||||
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
|
||||
unsigned long *status, unsigned int *bit)
|
||||
{
|
||||
@ -887,6 +1242,8 @@ static int tegra_pmc_probe(struct platform_device *pdev)
|
||||
return err;
|
||||
}
|
||||
|
||||
tegra_powergate_init(pmc);
|
||||
|
||||
mutex_lock(&pmc->powergates_lock);
|
||||
iounmap(pmc->base);
|
||||
pmc->base = base;
|
||||
@ -1120,6 +1477,7 @@ static int __init tegra_pmc_early_init(void)
|
||||
const struct of_device_id *match;
|
||||
struct device_node *np;
|
||||
struct resource regs;
|
||||
unsigned int i;
|
||||
bool invert;
|
||||
u32 value;
|
||||
|
||||
@ -1169,6 +1527,11 @@ static int __init tegra_pmc_early_init(void)
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/* Create a bit-map of the available and valid partitions */
|
||||
for (i = 0; i < pmc->soc->num_powergates; i++)
|
||||
if (pmc->soc->powergates[i])
|
||||
set_bit(i, pmc->powergates_available);
|
||||
|
||||
mutex_init(&pmc->powergates_lock);
|
||||
|
||||
/*
|
||||
|
||||
@ -72,6 +72,7 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
|
||||
#define TEGRA_POWERGATE_AUD 27
|
||||
#define TEGRA_POWERGATE_DFD 28
|
||||
#define TEGRA_POWERGATE_VE2 29
|
||||
#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
|
||||
|
||||
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user