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net: hns3: add support for registering devlink for PF
Add devlink register support for HNS3 ethernet PF driver. Signed-off-by: Yufeng Mo <moyufeng@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -90,6 +90,7 @@ config HNS_ENET
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config HNS3
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tristate "Hisilicon Network Subsystem Support HNS3 (Framework)"
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depends on PCI
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select NET_DEVLINK
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help
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This selects the framework support for Hisilicon Network Subsystem 3.
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This layer facilitates clients like ENET, RoCE and user-space ethernet
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@ -7,6 +7,6 @@ ccflags-y := -I $(srctree)/drivers/net/ethernet/hisilicon/hns3
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ccflags-y += -I $(srctree)/$(src)
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obj-$(CONFIG_HNS3_HCLGE) += hclge.o
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hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o hclge_mbx.o hclge_err.o hclge_debugfs.o hclge_ptp.o
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hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o hclge_mbx.o hclge_err.o hclge_debugfs.o hclge_ptp.o hclge_devlink.o
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hclge-$(CONFIG_HNS3_DCB) += hclge_dcb.o
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54
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
Normal file
54
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
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@ -0,0 +1,54 @@
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// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (c) 2021 Hisilicon Limited. */
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#include <net/devlink.h>
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#include "hclge_devlink.h"
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static const struct devlink_ops hclge_devlink_ops = {
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};
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int hclge_devlink_init(struct hclge_dev *hdev)
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{
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struct pci_dev *pdev = hdev->pdev;
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struct hclge_devlink_priv *priv;
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struct devlink *devlink;
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int ret;
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devlink = devlink_alloc(&hclge_devlink_ops,
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sizeof(struct hclge_devlink_priv));
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if (!devlink)
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return -ENOMEM;
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priv = devlink_priv(devlink);
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priv->hdev = hdev;
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ret = devlink_register(devlink, &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "failed to register devlink, ret = %d\n",
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ret);
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goto out_reg_fail;
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}
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hdev->devlink = devlink;
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return 0;
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out_reg_fail:
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devlink_free(devlink);
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return ret;
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}
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void hclge_devlink_uninit(struct hclge_dev *hdev)
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{
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struct devlink *devlink = hdev->devlink;
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if (!devlink)
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return;
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devlink_unregister(devlink);
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devlink_free(devlink);
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hdev->devlink = NULL;
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}
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15
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h
Normal file
15
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2021 Hisilicon Limited. */
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#ifndef __HCLGE_DEVLINK_H
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#define __HCLGE_DEVLINK_H
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#include "hclge_main.h"
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struct hclge_devlink_priv {
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struct hclge_dev *hdev;
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};
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int hclge_devlink_init(struct hclge_dev *hdev);
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void hclge_devlink_uninit(struct hclge_dev *hdev);
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#endif
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@ -23,6 +23,7 @@
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#include "hclge_tm.h"
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#include "hclge_err.h"
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#include "hnae3.h"
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#include "hclge_devlink.h"
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#define HCLGE_NAME "hclge"
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#define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset)))
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@ -11482,10 +11483,14 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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if (ret)
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goto out;
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ret = hclge_devlink_init(hdev);
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if (ret)
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goto err_pci_uninit;
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/* Firmware command queue initialize */
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ret = hclge_cmd_queue_init(hdev);
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if (ret)
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goto err_pci_uninit;
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goto err_devlink_uninit;
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/* Firmware command initialize */
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ret = hclge_cmd_init(hdev);
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@ -11658,6 +11663,8 @@ err_msi_uninit:
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pci_free_irq_vectors(pdev);
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err_cmd_uninit:
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hclge_cmd_uninit(hdev);
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err_devlink_uninit:
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hclge_devlink_uninit(hdev);
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err_pci_uninit:
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pcim_iounmap(pdev, hdev->hw.io_base);
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pci_clear_master(pdev);
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@ -12048,6 +12055,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
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hclge_cmd_uninit(hdev);
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hclge_misc_irq_uninit(hdev);
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hclge_devlink_uninit(hdev);
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hclge_pci_uninit(hdev);
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mutex_destroy(&hdev->vport_lock);
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hclge_uninit_vport_vlan_table(hdev);
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@ -8,6 +8,7 @@
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#include <linux/phy.h>
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#include <linux/if_vlan.h>
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#include <linux/kfifo.h>
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#include <net/devlink.h>
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#include "hclge_cmd.h"
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#include "hclge_ptp.h"
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@ -943,6 +944,7 @@ struct hclge_dev {
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cpumask_t affinity_mask;
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struct irq_affinity_notify affinity_notify;
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struct hclge_ptp *ptp;
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struct devlink *devlink;
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};
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/* VPort level vlan tag configuration for TX direction */
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