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rtc: stm32: add stm32mp1 rtc support
This patch adds support for stm32mp1 RTC. Some common registers with previous RTC version have a different offset. It is the case for Control Register (CR) and ALaRMA Register (ALRMAR). There are also new registers regarding event flags: now, Alarm event flag is in Status Register (SR) and write 1 in Status Clear Register (SCR) is required to clear the event. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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@ -11,6 +11,7 @@
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/regmap.h>
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#include <linux/rtc.h>
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@ -39,7 +40,7 @@
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#define STM32_RTC_CR_ALRAE BIT(8)
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#define STM32_RTC_CR_ALRAIE BIT(12)
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/* STM32_RTC_ISR bit fields */
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/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
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#define STM32_RTC_ISR_ALRAWF BIT(0)
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#define STM32_RTC_ISR_INITS BIT(4)
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#define STM32_RTC_ISR_RSF BIT(5)
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@ -71,21 +72,36 @@
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#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
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#define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
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/* STM32_RTC_SR/_SCR bit fields */
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#define STM32_RTC_SR_ALRA BIT(0)
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/* STM32_RTC_VERR bit fields */
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#define STM32_RTC_VERR_MINREV_SHIFT 0
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#define STM32_RTC_VERR_MINREV GENMASK(3, 0)
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#define STM32_RTC_VERR_MAJREV_SHIFT 4
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#define STM32_RTC_VERR_MAJREV GENMASK(7, 4)
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/* STM32_RTC_WPR key constants */
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#define RTC_WPR_1ST_KEY 0xCA
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#define RTC_WPR_2ND_KEY 0x53
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#define RTC_WPR_WRONG_KEY 0xFF
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/* Max STM32 RTC register offset is 0x3FC */
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#define UNDEF_REG 0xFFFF
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struct stm32_rtc;
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struct stm32_rtc_registers {
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u8 tr;
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u8 dr;
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u8 cr;
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u8 isr;
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u8 prer;
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u8 alrmar;
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u8 wpr;
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u16 tr;
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u16 dr;
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u16 cr;
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u16 isr;
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u16 prer;
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u16 alrmar;
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u16 wpr;
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u16 sr;
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u16 scr;
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u16 verr;
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};
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struct stm32_rtc_events {
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@ -98,6 +114,7 @@ struct stm32_rtc_data {
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void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
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bool has_pclk;
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bool need_dbp;
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bool has_wakeirq;
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};
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struct stm32_rtc {
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@ -110,6 +127,7 @@ struct stm32_rtc {
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struct clk *rtc_ck;
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const struct stm32_rtc_data *data;
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int irq_alarm;
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int wakeirq_alarm;
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};
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static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
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@ -193,7 +211,7 @@ static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
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mutex_lock(&rtc->rtc_dev->ops_lock);
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status = readl_relaxed(rtc->base + regs->isr);
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status = readl_relaxed(rtc->base + regs->sr);
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cr = readl_relaxed(rtc->base + regs->cr);
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if ((status & evts->alra) &&
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@ -325,7 +343,7 @@ static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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alrmar = readl_relaxed(rtc->base + regs->alrmar);
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cr = readl_relaxed(rtc->base + regs->cr);
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status = readl_relaxed(rtc->base + regs->isr);
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status = readl_relaxed(rtc->base + regs->sr);
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if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
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/*
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@ -533,6 +551,7 @@ static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
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static const struct stm32_rtc_data stm32_rtc_data = {
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.has_pclk = false,
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.need_dbp = true,
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.has_wakeirq = false,
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.regs = {
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.tr = 0x00,
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.dr = 0x04,
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@ -541,6 +560,9 @@ static const struct stm32_rtc_data stm32_rtc_data = {
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.prer = 0x10,
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.alrmar = 0x1C,
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.wpr = 0x24,
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.sr = 0x0C, /* set to ISR offset to ease alarm management */
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.scr = UNDEF_REG,
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.verr = UNDEF_REG,
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},
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.events = {
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.alra = STM32_RTC_ISR_ALRAF,
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@ -551,6 +573,7 @@ static const struct stm32_rtc_data stm32_rtc_data = {
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static const struct stm32_rtc_data stm32h7_rtc_data = {
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.has_pclk = true,
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.need_dbp = true,
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.has_wakeirq = false,
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.regs = {
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.tr = 0x00,
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.dr = 0x04,
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@ -559,6 +582,9 @@ static const struct stm32_rtc_data stm32h7_rtc_data = {
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.prer = 0x10,
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.alrmar = 0x1C,
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.wpr = 0x24,
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.sr = 0x0C, /* set to ISR offset to ease alarm management */
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.scr = UNDEF_REG,
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.verr = UNDEF_REG,
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},
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.events = {
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.alra = STM32_RTC_ISR_ALRAF,
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@ -566,9 +592,41 @@ static const struct stm32_rtc_data stm32h7_rtc_data = {
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.clear_events = stm32_rtc_clear_events,
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};
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static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
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unsigned int flags)
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{
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struct stm32_rtc_registers regs = rtc->data->regs;
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/* Flags are cleared by writing 1 in RTC_SCR */
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writel_relaxed(flags, rtc->base + regs.scr);
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}
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static const struct stm32_rtc_data stm32mp1_data = {
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.has_pclk = true,
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.need_dbp = false,
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.has_wakeirq = true,
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.regs = {
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.tr = 0x00,
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.dr = 0x04,
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.cr = 0x18,
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.isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
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.prer = 0x10,
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.alrmar = 0x40,
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.wpr = 0x24,
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.sr = 0x50,
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.scr = 0x5C,
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.verr = 0x3F4,
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},
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.events = {
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.alra = STM32_RTC_SR_ALRA,
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},
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.clear_events = stm32mp1_rtc_clear_events,
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};
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static const struct of_device_id stm32_rtc_of_match[] = {
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{ .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
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{ .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
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{ .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
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@ -727,12 +785,19 @@ static int stm32_rtc_probe(struct platform_device *pdev)
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goto err;
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}
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platform_set_drvdata(pdev, rtc);
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ret = device_init_wakeup(&pdev->dev, true);
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if (rtc->data->has_wakeirq) {
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rtc->wakeirq_alarm = platform_get_irq(pdev, 1);
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if (rtc->wakeirq_alarm <= 0)
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ret = rtc->wakeirq_alarm;
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else
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ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
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rtc->wakeirq_alarm);
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}
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if (ret)
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dev_warn(&pdev->dev,
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"alarm won't be able to wake up the system");
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dev_warn(&pdev->dev, "alarm can't wake up the system: %d", ret);
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platform_set_drvdata(pdev, rtc);
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rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
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&stm32_rtc_ops, THIS_MODULE);
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@ -760,6 +825,14 @@ static int stm32_rtc_probe(struct platform_device *pdev)
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if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
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dev_warn(&pdev->dev, "Date/Time must be initialized\n");
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if (regs->verr != UNDEF_REG) {
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u32 ver = readl_relaxed(rtc->base + regs->verr);
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dev_info(&pdev->dev, "registered rev:%d.%d\n",
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(ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
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(ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
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}
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return 0;
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err:
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if (rtc->data->has_pclk)
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@ -769,6 +842,7 @@ err:
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if (rtc->data->need_dbp)
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regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
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dev_pm_clear_wake_irq(&pdev->dev);
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device_init_wakeup(&pdev->dev, false);
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return ret;
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@ -795,6 +869,7 @@ static int stm32_rtc_remove(struct platform_device *pdev)
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if (rtc->data->need_dbp)
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regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
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dev_pm_clear_wake_irq(&pdev->dev);
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device_init_wakeup(&pdev->dev, false);
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return 0;
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