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MIPS: Octeon: Allow CVMSEG to be disabled
Don't include cvmseg states into thread_status when CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE is not defined or 0. Fix compile for kernel without this feature. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -202,11 +202,13 @@ struct octeon_cop2_state {
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#define COP2_INIT \
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.cp2 = {0,},
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#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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struct octeon_cvmseg_state {
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unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
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[cpu_dcache_line_size() / sizeof(unsigned long)];
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};
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#endif
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#else
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#define COP2_INIT
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#endif
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@ -263,7 +265,10 @@ struct thread_struct {
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unsigned long trap_nr;
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
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#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
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#endif
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#endif
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struct mips_abi *abi;
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};
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@ -306,7 +306,10 @@ void output_octeon_cop2_state_defines(void)
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OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
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OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3);
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OFFSET(THREAD_CP2, task_struct, thread.cp2);
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#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
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#endif
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BLANK();
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}
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#endif
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