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spi: spi-geni-qcom: Add support for GPI dma
We can use GPI DMA for devices where it is enabled by firmware. Add support for this mode Signed-off-by: Vinod Koul <vkoul@kernel.org> -- -Changes since v4: - Fix the kbuild bot warning -Changes since v3: - Drop merged spi core, geni patches - Remove global structs and use local variables instead - modularize code more as suggested by Doug - fix kbuild bot warning drivers/spi/spi-geni-qcom.c | 254 +++++++++++++++++++++++++++++++++--- 1 file changed, 239 insertions(+), 15 deletions(-) Link: https://lore.kernel.org/r/20211020060954.1531783-1-vkoul@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vinod Koul
Mark Brown
parent
e954af1343
commit
b59c122484
@ -2,6 +2,9 @@
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// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma/qcom-gpi-dma.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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@ -63,6 +66,15 @@
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#define TIMESTAMP_AFTER BIT(3)
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#define POST_CMD_DELAY BIT(4)
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#define GSI_LOOPBACK_EN BIT(0)
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#define GSI_CS_TOGGLE BIT(3)
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#define GSI_CPHA BIT(4)
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#define GSI_CPOL BIT(5)
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#define MAX_TX_SG 3
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#define NUM_SPI_XFER 8
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#define SPI_XFER_TIMEOUT_MS 250
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struct spi_geni_master {
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struct geni_se se;
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struct device *dev;
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@ -84,6 +96,9 @@ struct spi_geni_master {
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int irq;
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bool cs_flag;
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bool abort_failed;
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struct dma_chan *tx;
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struct dma_chan *rx;
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int cur_xfer_mode;
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};
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static int get_spi_clk_cfg(unsigned int speed_hz,
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@ -330,34 +345,197 @@ static int setup_fifo_params(struct spi_device *spi_slv,
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return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
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}
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static void
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spi_gsi_callback_result(void *cb, const struct dmaengine_result *result)
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{
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struct spi_master *spi = cb;
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if (result->result != DMA_TRANS_NOERROR) {
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dev_err(&spi->dev, "DMA txn failed: %d\n", result->result);
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return;
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}
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if (!result->residue) {
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dev_dbg(&spi->dev, "DMA txn completed\n");
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spi_finalize_current_transfer(spi);
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} else {
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dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue);
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}
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}
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static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
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struct spi_device *spi_slv, struct spi_master *spi)
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{
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unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
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struct dma_slave_config config = {};
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struct gpi_spi_config peripheral = {};
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struct dma_async_tx_descriptor *tx_desc, *rx_desc;
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int ret;
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config.peripheral_config = &peripheral;
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config.peripheral_size = sizeof(peripheral);
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peripheral.set_config = true;
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if (xfer->bits_per_word != mas->cur_bits_per_word ||
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xfer->speed_hz != mas->cur_speed_hz) {
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mas->cur_bits_per_word = xfer->bits_per_word;
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mas->cur_speed_hz = xfer->speed_hz;
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}
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if (xfer->tx_buf && xfer->rx_buf) {
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peripheral.cmd = SPI_DUPLEX;
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} else if (xfer->tx_buf) {
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peripheral.cmd = SPI_TX;
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peripheral.rx_len = 0;
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} else if (xfer->rx_buf) {
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peripheral.cmd = SPI_RX;
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if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
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peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
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} else {
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int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
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peripheral.rx_len = (xfer->len / bytes_per_word);
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}
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}
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peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
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peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
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peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
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peripheral.cs = spi_slv->chip_select;
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peripheral.pack_en = true;
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peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
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ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
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&peripheral.clk_src, &peripheral.clk_div);
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if (ret) {
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dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
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return ret;
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}
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if (!xfer->cs_change) {
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if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers))
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peripheral.fragmentation = FRAGMENTATION;
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}
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if (peripheral.cmd & SPI_RX) {
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dmaengine_slave_config(mas->rx, &config);
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rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
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DMA_DEV_TO_MEM, flags);
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if (!rx_desc) {
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dev_err(mas->dev, "Err setting up rx desc\n");
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return -EIO;
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}
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}
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/*
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* Prepare the TX always, even for RX or tx_buf being null, we would
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* need TX to be prepared per GSI spec
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*/
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dmaengine_slave_config(mas->tx, &config);
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tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
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DMA_MEM_TO_DEV, flags);
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if (!tx_desc) {
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dev_err(mas->dev, "Err setting up tx desc\n");
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return -EIO;
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}
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tx_desc->callback_result = spi_gsi_callback_result;
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tx_desc->callback_param = spi;
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if (peripheral.cmd & SPI_RX)
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dmaengine_submit(rx_desc);
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dmaengine_submit(tx_desc);
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if (peripheral.cmd & SPI_RX)
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dma_async_issue_pending(mas->rx);
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dma_async_issue_pending(mas->tx);
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return 1;
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}
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static bool geni_can_dma(struct spi_controller *ctlr,
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struct spi_device *slv, struct spi_transfer *xfer)
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{
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struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
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/* check if dma is supported */
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return mas->cur_xfer_mode != GENI_SE_FIFO;
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}
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static int spi_geni_prepare_message(struct spi_master *spi,
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struct spi_message *spi_msg)
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{
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int ret;
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struct spi_geni_master *mas = spi_master_get_devdata(spi);
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int ret;
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if (spi_geni_is_abort_still_pending(mas))
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return -EBUSY;
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switch (mas->cur_xfer_mode) {
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case GENI_SE_FIFO:
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if (spi_geni_is_abort_still_pending(mas))
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return -EBUSY;
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ret = setup_fifo_params(spi_msg->spi, spi);
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if (ret)
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dev_err(mas->dev, "Couldn't select mode %d\n", ret);
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return ret;
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ret = setup_fifo_params(spi_msg->spi, spi);
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if (ret)
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dev_err(mas->dev, "Couldn't select mode %d\n", ret);
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case GENI_GPI_DMA:
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/* nothing to do for GPI DMA */
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return 0;
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}
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dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
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return -EINVAL;
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}
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static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
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{
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int ret;
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mas->tx = dma_request_chan(mas->dev, "tx");
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ret = dev_err_probe(mas->dev, IS_ERR(mas->tx), "Failed to get tx DMA ch\n");
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if (ret < 0)
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goto err_tx;
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mas->rx = dma_request_chan(mas->dev, "rx");
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ret = dev_err_probe(mas->dev, IS_ERR(mas->rx), "Failed to get rx DMA ch\n");
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if (ret < 0)
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goto err_rx;
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return 0;
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err_rx:
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dma_release_channel(mas->tx);
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mas->tx = NULL;
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err_tx:
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mas->rx = NULL;
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return ret;
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}
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static void spi_geni_release_dma_chan(struct spi_geni_master *mas)
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{
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if (mas->rx) {
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dma_release_channel(mas->rx);
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mas->rx = NULL;
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}
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if (mas->tx) {
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dma_release_channel(mas->tx);
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mas->tx = NULL;
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}
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}
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static int spi_geni_init(struct spi_geni_master *mas)
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{
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struct geni_se *se = &mas->se;
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unsigned int proto, major, minor, ver;
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u32 spi_tx_cfg;
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u32 spi_tx_cfg, fifo_disable;
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int ret = -ENXIO;
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pm_runtime_get_sync(mas->dev);
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proto = geni_se_read_proto(se);
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if (proto != GENI_SE_SPI) {
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dev_err(mas->dev, "Invalid proto %d\n", proto);
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pm_runtime_put(mas->dev);
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return -ENXIO;
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goto out_pm;
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}
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mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
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@ -380,15 +558,38 @@ static int spi_geni_init(struct spi_geni_master *mas)
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else
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mas->oversampling = 1;
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geni_se_select_mode(se, GENI_SE_FIFO);
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fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
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switch (fifo_disable) {
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case 1:
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ret = spi_geni_grab_gpi_chan(mas);
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if (!ret) { /* success case */
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mas->cur_xfer_mode = GENI_GPI_DMA;
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geni_se_select_mode(se, GENI_GPI_DMA);
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dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
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break;
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}
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/*
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* in case of failure to get dma channel, we can still do the
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* FIFO mode, so fallthrough
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*/
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dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
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fallthrough;
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case 0:
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mas->cur_xfer_mode = GENI_SE_FIFO;
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geni_se_select_mode(se, GENI_SE_FIFO);
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ret = 0;
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break;
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}
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/* We always control CS manually */
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spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
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spi_tx_cfg &= ~CS_TOGGLE;
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writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
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out_pm:
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pm_runtime_put(mas->dev);
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return 0;
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return ret;
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}
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static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
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@ -569,8 +770,11 @@ static int spi_geni_transfer_one(struct spi_master *spi,
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if (!xfer->len)
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return 0;
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setup_fifo_xfer(xfer, mas, slv->mode, spi);
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return 1;
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if (mas->cur_xfer_mode == GENI_SE_FIFO) {
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setup_fifo_xfer(xfer, mas, slv->mode, spi);
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return 1;
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}
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return setup_gsi_xfer(xfer, mas, slv, spi);
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}
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static irqreturn_t geni_spi_isr(int irq, void *data)
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@ -665,6 +869,13 @@ static int spi_geni_probe(struct platform_device *pdev)
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if (irq < 0)
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return irq;
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
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if (ret) {
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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if (ret)
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return dev_err_probe(dev, ret, "could not set DMA mask\n");
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}
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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@ -704,9 +915,10 @@ static int spi_geni_probe(struct platform_device *pdev)
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spi->max_speed_hz = 50000000;
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spi->prepare_message = spi_geni_prepare_message;
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spi->transfer_one = spi_geni_transfer_one;
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spi->can_dma = geni_can_dma;
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spi->dma_map_dev = dev->parent;
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spi->auto_runtime_pm = true;
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spi->handle_err = handle_fifo_timeout;
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spi->set_cs = spi_geni_set_cs;
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spi->use_gpio_descriptors = true;
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init_completion(&mas->cs_done);
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@ -732,9 +944,17 @@ static int spi_geni_probe(struct platform_device *pdev)
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if (ret)
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goto spi_geni_probe_runtime_disable;
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/*
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* check the mode supported and set_cs for fifo mode only
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* for dma (gsi) mode, the gsi will set cs based on params passed in
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* TRE
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*/
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if (mas->cur_xfer_mode == GENI_SE_FIFO)
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spi->set_cs = spi_geni_set_cs;
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ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
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if (ret)
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goto spi_geni_probe_runtime_disable;
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goto spi_geni_release_dma;
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ret = spi_register_master(spi);
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if (ret)
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@ -743,6 +963,8 @@ static int spi_geni_probe(struct platform_device *pdev)
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return 0;
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spi_geni_probe_free_irq:
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free_irq(mas->irq, spi);
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spi_geni_release_dma:
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spi_geni_release_dma_chan(mas);
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spi_geni_probe_runtime_disable:
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pm_runtime_disable(dev);
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return ret;
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@ -756,6 +978,8 @@ static int spi_geni_remove(struct platform_device *pdev)
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/* Unregister _before_ disabling pm_runtime() so we stop transfers */
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spi_unregister_master(spi);
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spi_geni_release_dma_chan(mas);
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free_irq(mas->irq, spi);
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pm_runtime_disable(&pdev->dev);
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return 0;
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