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[PATCH] SPI eeprom driver
This is adds a simple SPI EEPROM driver, providing access to the EEPROM through sysfs much like the I2C "eeprom" driver ... except this driver supports write access, and multiple EEPROM sizes. From: "Tuppa, Walter" <walter.tuppa@siemens.com> Since I have EEPROMs on SPI with different address sizing, I made some changes to your at25.c to support them. Works perfectly. (Also includes a small bugfix for the "what size address" test.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Walter Tuppa <walter.tuppa@siemens.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
David Brownell
Linus Torvalds
parent
3925a5ce44
commit
b587b13a4f
@ -135,6 +135,16 @@ config SPI_S3C24XX_GPIO
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comment "SPI Protocol Masters"
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comment "SPI Protocol Masters"
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depends on SPI_MASTER
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depends on SPI_MASTER
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config SPI_AT25
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tristate "SPI EEPROMs from most vendors"
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depends on SPI_MASTER && SYSFS
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help
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Enable this driver to get read/write support to most SPI EEPROMs,
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after you configure the board init code to know about each eeprom
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on your target board.
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This driver can also be built as a module. If so, the module
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will be called at25.
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#
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#
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# Add new SPI protocol masters in alphabetical order above this line
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# Add new SPI protocol masters in alphabetical order above this line
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@ -22,6 +22,7 @@ obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
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# ... add above this line ...
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# ... add above this line ...
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# SPI protocol drivers (device/link on bus)
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# SPI protocol drivers (device/link on bus)
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obj-$(CONFIG_SPI_AT25) += at25.o
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# ... add above this line ...
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# ... add above this line ...
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# SPI slave controller drivers (upstream link)
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# SPI slave controller drivers (upstream link)
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381
drivers/spi/at25.c
Normal file
381
drivers/spi/at25.c
Normal file
@ -0,0 +1,381 @@
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/*
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* at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
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*
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* Copyright (C) 2006 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/sched.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/eeprom.h>
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struct at25_data {
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struct spi_device *spi;
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struct mutex lock;
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struct spi_eeprom chip;
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struct bin_attribute bin;
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unsigned addrlen;
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};
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#define AT25_WREN 0x06 /* latch the write enable */
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#define AT25_WRDI 0x04 /* reset the write enable */
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#define AT25_RDSR 0x05 /* read status register */
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#define AT25_WRSR 0x01 /* write status register */
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#define AT25_READ 0x03 /* read byte(s) */
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#define AT25_WRITE 0x02 /* write byte(s)/sector */
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#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
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#define AT25_SR_WEN 0x02 /* write enable (latched) */
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#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
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#define AT25_SR_BP1 0x08
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#define AT25_SR_WPEN 0x80 /* writeprotect enable */
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#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
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/* Specs often allow 5 msec for a page write, sometimes 20 msec;
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* it's important to recover from write timeouts.
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*/
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#define EE_TIMEOUT 25
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/*-------------------------------------------------------------------------*/
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#define io_limit PAGE_SIZE /* bytes */
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static ssize_t
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at25_ee_read(
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struct at25_data *at25,
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char *buf,
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unsigned offset,
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size_t count
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)
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{
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u8 command[EE_MAXADDRLEN + 1];
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u8 *cp;
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ssize_t status;
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struct spi_transfer t[2];
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struct spi_message m;
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cp = command;
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*cp++ = AT25_READ;
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/* 8/16/24-bit address is written MSB first */
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switch (at25->addrlen) {
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default: /* case 3 */
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*cp++ = offset >> 16;
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case 2:
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*cp++ = offset >> 8;
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case 1:
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case 0: /* can't happen: for better codegen */
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*cp++ = offset >> 0;
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}
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spi_message_init(&m);
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memset(t, 0, sizeof t);
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t[0].tx_buf = command;
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t[0].len = at25->addrlen + 1;
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = count;
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spi_message_add_tail(&t[1], &m);
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mutex_lock(&at25->lock);
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/* Read it all at once.
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*
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* REVISIT that's potentially a problem with large chips, if
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* other devices on the bus need to be accessed regularly or
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* this chip is clocked very slowly
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*/
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status = spi_sync(at25->spi, &m);
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dev_dbg(&at25->spi->dev,
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"read %Zd bytes at %d --> %d\n",
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count, offset, (int) status);
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mutex_unlock(&at25->lock);
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return status ? status : count;
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}
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static ssize_t
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at25_bin_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
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{
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struct device *dev;
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struct at25_data *at25;
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dev = container_of(kobj, struct device, kobj);
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at25 = dev_get_drvdata(dev);
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if (unlikely(off >= at25->bin.size))
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return 0;
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if ((off + count) > at25->bin.size)
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count = at25->bin.size - off;
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if (unlikely(!count))
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return count;
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return at25_ee_read(at25, buf, off, count);
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}
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static ssize_t
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at25_ee_write(struct at25_data *at25, char *buf, loff_t off, size_t count)
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{
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ssize_t status = 0;
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unsigned written = 0;
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unsigned buf_size;
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u8 *bounce;
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/* Temp buffer starts with command and address */
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buf_size = at25->chip.page_size;
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if (buf_size > io_limit)
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buf_size = io_limit;
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bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
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if (!bounce)
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return -ENOMEM;
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/* For write, rollover is within the page ... so we write at
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* most one page, then manually roll over to the next page.
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*/
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bounce[0] = AT25_WRITE;
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mutex_lock(&at25->lock);
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do {
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unsigned long timeout, retries;
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unsigned segment;
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unsigned offset = (unsigned) off;
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u8 *cp = bounce + 1;
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*cp = AT25_WREN;
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status = spi_write(at25->spi, cp, 1);
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if (status < 0) {
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dev_dbg(&at25->spi->dev, "WREN --> %d\n",
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(int) status);
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break;
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}
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/* 8/16/24-bit address is written MSB first */
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switch (at25->addrlen) {
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default: /* case 3 */
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*cp++ = offset >> 16;
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case 2:
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*cp++ = offset >> 8;
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case 1:
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case 0: /* can't happen: for better codegen */
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*cp++ = offset >> 0;
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}
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/* Write as much of a page as we can */
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segment = buf_size - (offset % buf_size);
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if (segment > count)
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segment = count;
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memcpy(cp, buf, segment);
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status = spi_write(at25->spi, bounce,
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segment + at25->addrlen + 1);
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dev_dbg(&at25->spi->dev,
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"write %u bytes at %u --> %d\n",
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segment, offset, (int) status);
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if (status < 0)
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break;
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/* REVISIT this should detect (or prevent) failed writes
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* to readonly sections of the EEPROM...
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*/
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/* Wait for non-busy status */
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timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
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retries = 0;
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do {
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int sr;
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sr = spi_w8r8(at25->spi, AT25_RDSR);
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if (sr < 0 || (sr & AT25_SR_nRDY)) {
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dev_dbg(&at25->spi->dev,
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"rdsr --> %d (%02x)\n", sr, sr);
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/* at HZ=100, this is sloooow */
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msleep(1);
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continue;
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}
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if (!(sr & AT25_SR_nRDY))
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break;
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} while (retries++ < 3 || time_before_eq(jiffies, timeout));
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if (time_after(jiffies, timeout)) {
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dev_err(&at25->spi->dev,
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"write %d bytes offset %d, "
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"timeout after %u msecs\n",
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segment, offset,
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jiffies_to_msecs(jiffies -
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(timeout - EE_TIMEOUT)));
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status = -ETIMEDOUT;
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break;
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}
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off += segment;
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buf += segment;
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count -= segment;
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written += segment;
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} while (count > 0);
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mutex_unlock(&at25->lock);
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kfree(bounce);
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return written ? written : status;
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}
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static ssize_t
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at25_bin_write(struct kobject *kobj, char *buf, loff_t off, size_t count)
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{
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struct device *dev;
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struct at25_data *at25;
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dev = container_of(kobj, struct device, kobj);
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at25 = dev_get_drvdata(dev);
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if (unlikely(off >= at25->bin.size))
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return -EFBIG;
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if ((off + count) > at25->bin.size)
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count = at25->bin.size - off;
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if (unlikely(!count))
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return count;
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return at25_ee_write(at25, buf, off, count);
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}
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/*-------------------------------------------------------------------------*/
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static int at25_probe(struct spi_device *spi)
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{
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struct at25_data *at25 = NULL;
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const struct spi_eeprom *chip;
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int err;
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int sr;
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int addrlen;
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/* Chip description */
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chip = spi->dev.platform_data;
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if (!chip) {
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dev_dbg(&spi->dev, "no chip description\n");
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err = -ENODEV;
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goto fail;
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}
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/* For now we only support 8/16/24 bit addressing */
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if (chip->flags & EE_ADDR1)
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addrlen = 1;
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else if (chip->flags & EE_ADDR2)
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addrlen = 2;
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else if (chip->flags & EE_ADDR3)
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addrlen = 3;
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else {
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dev_dbg(&spi->dev, "unsupported address type\n");
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err = -EINVAL;
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goto fail;
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}
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/* Ping the chip ... the status register is pretty portable,
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* unlike probing manufacturer IDs. We do expect that system
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* firmware didn't write it in the past few milliseconds!
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*/
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sr = spi_w8r8(spi, AT25_RDSR);
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if (sr < 0 || sr & AT25_SR_nRDY) {
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dev_dbg(&at25->spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
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err = -ENXIO;
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goto fail;
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}
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if (!(at25 = kzalloc(sizeof *at25, GFP_KERNEL))) {
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err = -ENOMEM;
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goto fail;
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}
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mutex_init(&at25->lock);
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at25->chip = *chip;
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at25->spi = spi_dev_get(spi);
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dev_set_drvdata(&spi->dev, at25);
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at25->addrlen = addrlen;
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/* Export the EEPROM bytes through sysfs, since that's convenient.
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* Default to root-only access to the data; EEPROMs often hold data
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* that's sensitive for read and/or write, like ethernet addresses,
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* security codes, board-specific manufacturing calibrations, etc.
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*/
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at25->bin.attr.name = "eeprom";
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at25->bin.attr.mode = S_IRUSR;
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at25->bin.attr.owner = THIS_MODULE;
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at25->bin.read = at25_bin_read;
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at25->bin.size = at25->chip.byte_len;
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if (!(chip->flags & EE_READONLY)) {
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at25->bin.write = at25_bin_write;
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at25->bin.attr.mode |= S_IWUSR;
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}
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err = sysfs_create_bin_file(&spi->dev.kobj, &at25->bin);
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if (err)
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goto fail;
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dev_info(&spi->dev, "%Zd %s %s eeprom%s, pagesize %u\n",
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(at25->bin.size < 1024)
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? at25->bin.size
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: (at25->bin.size / 1024),
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(at25->bin.size < 1024) ? "Byte" : "KByte",
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at25->chip.name,
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(chip->flags & EE_READONLY) ? " (readonly)" : "",
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at25->chip.page_size);
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return 0;
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fail:
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dev_dbg(&spi->dev, "probe err %d\n", err);
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kfree(at25);
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return err;
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}
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static int __devexit at25_remove(struct spi_device *spi)
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{
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struct at25_data *at25;
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at25 = dev_get_drvdata(&spi->dev);
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sysfs_remove_bin_file(&spi->dev.kobj, &at25->bin);
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kfree(at25);
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return 0;
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}
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|
||||||
|
/*-------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
static struct spi_driver at25_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "at25",
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
},
|
||||||
|
.probe = at25_probe,
|
||||||
|
.remove = __devexit_p(at25_remove),
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init at25_init(void)
|
||||||
|
{
|
||||||
|
return spi_register_driver(&at25_driver);
|
||||||
|
}
|
||||||
|
module_init(at25_init);
|
||||||
|
|
||||||
|
static void __exit at25_exit(void)
|
||||||
|
{
|
||||||
|
spi_unregister_driver(&at25_driver);
|
||||||
|
}
|
||||||
|
module_exit(at25_exit);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
|
||||||
|
MODULE_AUTHOR("David Brownell");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
|
|
||||||
22
include/linux/spi/eeprom.h
Normal file
22
include/linux/spi/eeprom.h
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
#ifndef __LINUX_SPI_EEPROM_H
|
||||||
|
#define __LINUX_SPI_EEPROM_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Put one of these structures in platform_data for SPI EEPROMS handled
|
||||||
|
* by the "at25" driver. On SPI, most EEPROMS understand the same core
|
||||||
|
* command set. If you need to support EEPROMs that don't yet fit, add
|
||||||
|
* flags to support those protocol options. These values all come from
|
||||||
|
* the chip datasheets.
|
||||||
|
*/
|
||||||
|
struct spi_eeprom {
|
||||||
|
u32 byte_len;
|
||||||
|
char name[10];
|
||||||
|
u16 page_size; /* for writes */
|
||||||
|
u16 flags;
|
||||||
|
#define EE_ADDR1 0x0001 /* 8 bit addrs */
|
||||||
|
#define EE_ADDR2 0x0002 /* 16 bit addrs */
|
||||||
|
#define EE_ADDR3 0x0004 /* 24 bit addrs */
|
||||||
|
#define EE_READONLY 0x0008 /* disallow writes */
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __LINUX_SPI_EEPROM_H */
|
||||||
Loading…
Reference in New Issue
Block a user