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pinctrl: Ingenic: Add pinctrl driver for JZ4755.
Add support for probing the pinctrl-ingenic driver on the JZ4755 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1618757073-1724-11-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
周琰杰 (Zhou Yanjie)
Linus Walleij
parent
215c81a3e9
commit
b582b5a434
@ -86,6 +86,7 @@ enum jz_version {
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ID_JZ4740,
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ID_JZ4725B,
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ID_JZ4750,
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ID_JZ4755,
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ID_JZ4760,
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ID_JZ4770,
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ID_JZ4780,
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@ -565,6 +566,138 @@ static const struct ingenic_chip_info jz4750_chip_info = {
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.pull_downs = jz4750_pull_downs,
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};
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static const u32 jz4755_pull_ups[6] = {
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0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,
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};
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static const u32 jz4755_pull_downs[6] = {
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0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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};
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static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
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static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
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static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
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static int jz4755_uart2_data_pins[] = { 0x9f, };
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static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
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static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
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static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
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static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
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static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
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static int jz4755_cim_pins[] = {
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0x89, 0x8b, 0x8a, 0x88,
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0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
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};
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static int jz4755_lcd_8bit_pins[] = {
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0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
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0x72, 0x73, 0x74,
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};
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static int jz4755_lcd_16bit_pins[] = {
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0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
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};
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static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
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static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
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static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
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static int jz4755_lcd_generic_pins[] = { 0x75, };
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static int jz4755_nand_cs1_pins[] = { 0x55, };
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static int jz4755_nand_cs2_pins[] = { 0x56, };
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static int jz4755_nand_cs3_pins[] = { 0x57, };
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static int jz4755_nand_cs4_pins[] = { 0x58, };
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static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
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static int jz4755_pwm_pwm0_pins[] = { 0x94, };
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static int jz4755_pwm_pwm1_pins[] = { 0xab, };
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static int jz4755_pwm_pwm2_pins[] = { 0x96, };
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static int jz4755_pwm_pwm3_pins[] = { 0x97, };
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static int jz4755_pwm_pwm4_pins[] = { 0x98, };
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static int jz4755_pwm_pwm5_pins[] = { 0x99, };
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static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
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static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
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static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
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static const struct group_desc jz4755_groups[] = {
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INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
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INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
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INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
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INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
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INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
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jz4755_mmc0_1bit_funcs),
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INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
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jz4755_mmc0_4bit_funcs),
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INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
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INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
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INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
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INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
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INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
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INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
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INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
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INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
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jz4755_lcd_24bit_funcs),
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INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
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INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
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INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
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INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
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INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
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INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
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INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
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INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
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INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
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INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
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INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
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INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
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INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
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};
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static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
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static const char *jz4755_uart1_groups[] = { "uart1-data", };
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static const char *jz4755_uart2_groups[] = { "uart2-data", };
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static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
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static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
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static const char *jz4755_i2c_groups[] = { "i2c-data", };
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static const char *jz4755_cim_groups[] = { "cim-data", };
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static const char *jz4755_lcd_groups[] = {
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"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
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"lcd-special", "lcd-generic",
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};
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static const char *jz4755_nand_groups[] = {
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"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
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};
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static const char *jz4755_pwm0_groups[] = { "pwm0", };
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static const char *jz4755_pwm1_groups[] = { "pwm1", };
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static const char *jz4755_pwm2_groups[] = { "pwm2", };
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static const char *jz4755_pwm3_groups[] = { "pwm3", };
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static const char *jz4755_pwm4_groups[] = { "pwm4", };
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static const char *jz4755_pwm5_groups[] = { "pwm5", };
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static const struct function_desc jz4755_functions[] = {
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{ "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
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{ "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
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{ "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
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{ "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
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{ "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
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{ "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
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{ "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), },
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{ "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), },
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{ "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), },
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{ "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), },
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{ "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), },
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{ "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), },
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{ "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), },
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{ "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), },
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{ "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), },
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};
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static const struct ingenic_chip_info jz4755_chip_info = {
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.num_chips = 6,
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.reg_offset = 0x100,
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.version = ID_JZ4755,
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.groups = jz4755_groups,
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.num_groups = ARRAY_SIZE(jz4755_groups),
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.functions = jz4755_functions,
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.num_functions = ARRAY_SIZE(jz4755_functions),
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.pull_ups = jz4755_pull_ups,
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.pull_downs = jz4755_pull_downs,
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};
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static const u32 jz4760_pull_ups[6] = {
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0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
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};
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@ -2695,6 +2828,7 @@ static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
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{ .compatible = "ingenic,jz4740-gpio", },
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{ .compatible = "ingenic,jz4725b-gpio", },
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{ .compatible = "ingenic,jz4750-gpio", },
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{ .compatible = "ingenic,jz4755-gpio", },
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{ .compatible = "ingenic,jz4760-gpio", },
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{ .compatible = "ingenic,jz4770-gpio", },
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{ .compatible = "ingenic,jz4780-gpio", },
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@ -2904,6 +3038,11 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
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.compatible = "ingenic,jz4750-pinctrl",
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.data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)
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},
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{
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.compatible = "ingenic,jz4755-pinctrl",
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.data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)
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},
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{
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.compatible = "ingenic,jz4760-pinctrl",
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.data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
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},
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