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MIPS: remove asm/war.h

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The major part for workaround handling has already moved to config
options. This change replaces the remaining defines by already
available config options and gets rid of war.h

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2022-02-18 11:04:39 +01:00
parent c47c7ab9b5
commit b56d1cafef
17 changed files with 47 additions and 91 deletions
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38
arch/mips/Kconfig
View File

@ -2521,13 +2521,51 @@ config CPU_HAS_SYNC
#
# CPU non-features
#
# Work around the "daddi" and "daddiu" CPU errata:
#
# - The `daddi' instruction fails to trap on overflow.
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
# erratum #23
#
# - The `daddiu' instruction can produce an incorrect result.
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
# erratum #41
# "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
# #15
# "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
# "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
config CPU_DADDI_WORKAROUNDS
bool
# Work around certain R4000 CPU errata (as implemented by GCC):
#
# - A double-word or a variable shift may give an incorrect result
# if executed immediately after starting an integer division:
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
# erratum #28
# "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
# #19
#
# - A double-word or a variable shift may give an incorrect result
# if executed while an integer multiplication is in progress:
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
# errata #16 & #28
#
# - An integer division may give an incorrect result if started in
# a delay slot of a taken branch or a jump:
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
# erratum #52
config CPU_R4000_WORKAROUNDS
bool
select CPU_R4400_WORKAROUNDS
# Work around certain R4400 CPU errata (as implemented by GCC):
#
# - A double-word or a variable shift may give an incorrect result
# if executed immediately after starting an integer division:
# "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
# "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
config CPU_R4400_WORKAROUNDS
bool

1
arch/mips/include/asm/futex.h
View File

@ -17,7 +17,6 @@
#include <asm/compiler.h>
#include <asm/errno.h>
#include <asm/sync.h>
#include <asm/war.h>
#define arch_futex_atomic_op_inuser arch_futex_atomic_op_inuser
#define futex_atomic_cmpxchg_inatomic futex_atomic_cmpxchg_inatomic

1
arch/mips/include/asm/mipsmtregs.h
View File

@ -9,7 +9,6 @@
#define _ASM_MIPSMTREGS_H
#include <asm/mipsregs.h>
#include <asm/war.h>
#ifndef __ASSEMBLY__

1
arch/mips/include/asm/mipsregs.h
View File

@ -17,7 +17,6 @@
#include <linux/types.h>
#include <asm/hazards.h>
#include <asm/isa-rev.h>
#include <asm/war.h>
/*
* The following macros are especially useful for __asm__

73
arch/mips/include/asm/war.h
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@ -1,73 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle
* Copyright (C) 2007 Maciej W. Rozycki
*/
#ifndef _ASM_WAR_H
#define _ASM_WAR_H
/*
* Work around certain R4000 CPU errata (as implemented by GCC):
*
* - A double-word or a variable shift may give an incorrect result
* if executed immediately after starting an integer division:
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
* erratum #28
* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
* #19
*
* - A double-word or a variable shift may give an incorrect result
* if executed while an integer multiplication is in progress:
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
* errata #16 & #28
*
* - An integer division may give an incorrect result if started in
* a delay slot of a taken branch or a jump:
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
* erratum #52
*/
#ifdef CONFIG_CPU_R4000_WORKAROUNDS
#define R4000_WAR 1
#else
#define R4000_WAR 0
#endif
/*
* Work around certain R4400 CPU errata (as implemented by GCC):
*
* - A double-word or a variable shift may give an incorrect result
* if executed immediately after starting an integer division:
* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
* "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
*/
#ifdef CONFIG_CPU_R4400_WORKAROUNDS
#define R4400_WAR 1
#else
#define R4400_WAR 0
#endif
/*
* Work around the "daddi" and "daddiu" CPU errata:
*
* - The `daddi' instruction fails to trap on overflow.
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
* erratum #23
*
* - The `daddiu' instruction can produce an incorrect result.
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
* erratum #41
* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
* #15
* "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
*/
#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
#define DADDI_WAR 1
#else
#define DADDI_WAR 0
#endif
#endif /* _ASM_WAR_H */

1
arch/mips/kernel/entry.S
View File

@ -17,7 +17,6 @@
#include <asm/stackframe.h>
#include <asm/isadep.h>
#include <asm/thread_info.h>
#include <asm/war.h>
#ifndef CONFIG_PREEMPTION
#define resume_kernel restore_all

1
arch/mips/kernel/genex.S
View File

@ -19,7 +19,6 @@
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/sync.h>
#include <asm/war.h>
#include <asm/thread_info.h>
__INIT

9
arch/mips/kernel/r4k-bugs64.c
View File

@ -163,7 +163,8 @@ static __always_inline __init void check_mult_sh(void)
}
pr_cont("no.\n");
panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
panic(bug64hit,
IS_ENABLED(CONFIG_CPU_R4000_WORKAROUNDS) ? nowar : r4kwar);
}
static volatile int daddi_ov;
@ -239,7 +240,8 @@ static __init void check_daddi(void)
}
pr_cont("no.\n");
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
panic(bug64hit,
IS_ENABLED(CONFIG_CPU_DADDI_WORKAROUNDS) ? nowar : daddiwar);
}
int daddiu_bug = -1;
@ -307,7 +309,8 @@ static __init void check_daddiu(void)
}
pr_cont("no.\n");
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
panic(bug64hit,
IS_ENABLED(CONFIG_CPU_DADDI_WORKAROUNDS) ? nowar : daddiwar);
}
void __init check_bugs64_early(void)

1
arch/mips/kernel/scall32-o32.S
View File

@ -19,7 +19,6 @@
#include <asm/sysmips.h>
#include <asm/thread_info.h>
#include <asm/unistd.h>
#include <asm/war.h>
#include <asm/asm-offsets.h>
.align 5

1
arch/mips/kernel/scall64-n64.S
View File

@ -18,7 +18,6 @@
#include <asm/sysmips.h>
#include <asm/thread_info.h>
#include <asm/unistd.h>
#include <asm/war.h>
#ifndef CONFIG_MIPS32_COMPAT
/* Neither O32 nor N32, so define handle_sys here */

1
arch/mips/kernel/signal.c
View File

@ -35,7 +35,6 @@
#include <asm/sim.h>
#include <asm/ucontext.h>
#include <asm/cpu-features.h>
#include <asm/war.h>
#include <asm/dsp.h>
#include <asm/inst.h>
#include <asm/msa.h>

1
arch/mips/kernel/signal_n32.c
View File

@ -24,7 +24,6 @@
#include <asm/ucontext.h>
#include <asm/fpu.h>
#include <asm/cpu-features.h>
#include <asm/war.h>
#include "signal-common.h"

1
arch/mips/lib/delay.c
View File

@ -16,7 +16,6 @@
#include <asm/asm.h>
#include <asm/compiler.h>
#include <asm/war.h>
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
#define GCC_DADDI_IMM_ASM() "I"

1
arch/mips/mm/c-octeon.c
View File

@ -23,7 +23,6 @@
#include <asm/r4kcache.h>
#include <asm/traps.h>
#include <asm/mmu_context.h>
#include <asm/war.h>
#include <asm/octeon/octeon.h>

1
arch/mips/mm/c-r4k.c
View File

@ -33,7 +33,6 @@
#include <asm/r4kcache.h>
#include <asm/sections.h>
#include <asm/mmu_context.h>
#include <asm/war.h>
#include <asm/cacheflush.h> /* for run_uncached() */
#include <asm/traps.h>
#include <asm/mips-cps.h>

5
arch/mips/mm/page.c
View File

@ -25,7 +25,6 @@
#include <asm/mipsregs.h>
#include <asm/mmu_context.h>
#include <asm/cpu.h>
#include <asm/war.h>
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
#include <asm/sibyte/sb1250.h>
@ -103,7 +102,9 @@ static int cache_line_size;
static inline void
pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
{
if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
if (cpu_has_64bit_gp_regs &&
IS_ENABLED(CONFIG_CPU_DADDI_WORKAROUNDS) &&
r4k_daddiu_bug()) {
if (off > 0x7fff) {
uasm_i_lui(buf, T9, uasm_rel_hi(off));
uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));

1
arch/mips/mm/tlbex.c
View File

@ -33,7 +33,6 @@
#include <asm/cacheflush.h>
#include <asm/cpu-type.h>
#include <asm/mmu_context.h>
#include <asm/war.h>
#include <asm/uasm.h>
#include <asm/setup.h>
#include <asm/tlbex.h>