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amd64_edac: Fix node id signedness
A node id can never be negative since we use it as an index into the DRAM ranges array. This also makes one of the BUG_ON conditions redundant. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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@ -226,7 +226,8 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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* returns true if the SysAddr given by sys_addr matches the
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* DRAM base/limit associated with node_id
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*/
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static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, int nid)
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static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr,
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unsigned nid)
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{
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u64 addr;
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@ -252,7 +253,7 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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u64 sys_addr)
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{
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struct amd64_pvt *pvt;
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int node_id;
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unsigned node_id;
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u32 intlv_en, bits;
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/*
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@ -302,7 +303,7 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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}
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found:
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return edac_mc_find(node_id);
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return edac_mc_find((int)node_id);
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err_no_match:
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debugf2("sys_addr 0x%lx doesn't match any node\n",
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@ -602,7 +603,7 @@ static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
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static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
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{
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struct amd64_pvt *pvt;
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int node_id, intlv_shift;
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unsigned node_id, intlv_shift;
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u64 bits, dram_addr;
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u32 intlv_sel;
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@ -616,7 +617,8 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
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*/
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pvt = mci->pvt_info;
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node_id = pvt->mc_node_id;
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BUG_ON((node_id < 0) || (node_id > 7));
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BUG_ON(node_id > 7);
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intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
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@ -2147,7 +2149,7 @@ static int init_csrows(struct mem_ctl_info *mci)
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}
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/* get all cores on this DCT */
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static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
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static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid)
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{
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int cpu;
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@ -2157,7 +2159,7 @@ static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
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}
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/* check MCG_CTL on all the cpus on this node */
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static bool amd64_nb_mce_bank_enabled_on_node(int nid)
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static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid)
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{
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cpumask_var_t mask;
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int cpu, nbe;
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@ -288,7 +288,7 @@
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#define MSR_MCGCTL_NBE BIT(4)
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/* AMD sets the first MC device at device ID 0x18. */
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static inline int get_node_id(struct pci_dev *pdev)
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static inline u8 get_node_id(struct pci_dev *pdev)
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{
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return PCI_SLOT(pdev->devfn) - 0x18;
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}
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@ -335,7 +335,7 @@ struct amd64_pvt {
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/* pci_device handles which we utilize */
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struct pci_dev *F1, *F2, *F3;
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int mc_node_id; /* MC index of this MC node */
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unsigned mc_node_id; /* MC index of this MC node */
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int ext_model; /* extended model value of this node */
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int channel_count;
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