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drm/i915/dp: convert g4x_dp.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct drm_i915_private as the main display device data pointer type. Convert g4x_dp.[ch] to struct intel_display. Some stragglers are left behind where needed. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b80ffb6373e9e3daaba0762ff7aebe168511b3a7.1725012870.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
1138137c2c
commit
b34b43f9cb
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@ -89,6 +89,7 @@ void g4x_dp_set_clock(struct intel_encoder *encoder,
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static void intel_dp_prepare(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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enum port port = encoder->port;
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@ -118,7 +119,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
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/* Preserve the BIOS-computed detected bit. This is
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* supposed to be read-only.
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*/
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intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
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intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
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/* Handle DP bits in common between all three register formats */
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intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
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@ -140,7 +141,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
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} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
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intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
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intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),
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intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),
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TRANS_DP_ENH_FRAMING,
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pipe_config->enhanced_framing ?
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TRANS_DP_ENH_FRAMING : 0);
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@ -166,9 +167,10 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
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static void assert_dp_port(struct intel_dp *intel_dp, bool state)
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{
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struct intel_display *display = to_intel_display(intel_dp);
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
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bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
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I915_STATE_WARN(dev_priv, cur_state != state,
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"[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
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@ -179,7 +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state)
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static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
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{
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bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
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struct intel_display *display = &dev_priv->display;
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bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
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I915_STATE_WARN(dev_priv, cur_state != state,
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"eDP PLL state assertion failure (expected %s, current %s)\n",
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@ -191,6 +194,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
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static void ilk_edp_pll_on(struct intel_dp *intel_dp,
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const struct intel_crtc_state *pipe_config)
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{
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struct intel_display *display = to_intel_display(intel_dp);
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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@ -198,7 +202,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
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assert_dp_port_disabled(intel_dp);
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assert_edp_pll_disabled(dev_priv);
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drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
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drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
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pipe_config->port_clock);
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intel_dp->DP &= ~DP_PLL_FREQ_MASK;
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@ -208,8 +212,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
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else
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intel_dp->DP |= DP_PLL_FREQ_270MHZ;
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intel_de_write(dev_priv, DP_A, intel_dp->DP);
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intel_de_posting_read(dev_priv, DP_A);
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intel_de_write(display, DP_A, intel_dp->DP);
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intel_de_posting_read(display, DP_A);
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udelay(500);
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/*
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@ -223,14 +227,15 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
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intel_dp->DP |= DP_PLL_ENABLE;
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intel_de_write(dev_priv, DP_A, intel_dp->DP);
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intel_de_posting_read(dev_priv, DP_A);
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intel_de_write(display, DP_A, intel_dp->DP);
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intel_de_posting_read(display, DP_A);
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udelay(200);
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}
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static void ilk_edp_pll_off(struct intel_dp *intel_dp,
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const struct intel_crtc_state *old_crtc_state)
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{
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struct intel_display *display = to_intel_display(intel_dp);
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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@ -238,22 +243,23 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
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assert_dp_port_disabled(intel_dp);
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assert_edp_pll_enabled(dev_priv);
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drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
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drm_dbg_kms(display->drm, "disabling eDP PLL\n");
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intel_dp->DP &= ~DP_PLL_ENABLE;
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intel_de_write(dev_priv, DP_A, intel_dp->DP);
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intel_de_posting_read(dev_priv, DP_A);
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intel_de_write(display, DP_A, intel_dp->DP);
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intel_de_posting_read(display, DP_A);
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udelay(200);
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}
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static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
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enum port port, enum pipe *pipe)
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{
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struct intel_display *display = &dev_priv->display;
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enum pipe p;
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for_each_pipe(dev_priv, p) {
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u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
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for_each_pipe(display, p) {
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u32 val = intel_de_read(display, TRANS_DP_CTL(p));
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if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
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*pipe = p;
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@ -261,7 +267,7 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
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}
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}
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drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
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drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",
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port_name(port));
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/* must initialize pipe to something for the asserts */
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@ -274,10 +280,11 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
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i915_reg_t dp_reg, enum port port,
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enum pipe *pipe)
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{
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struct intel_display *display = &dev_priv->display;
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bool ret;
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u32 val;
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val = intel_de_read(dev_priv, dp_reg);
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val = intel_de_read(display, dp_reg);
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ret = val & DP_PORT_EN;
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@ -333,6 +340,7 @@ static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
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static void intel_dp_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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u32 tmp, flags = 0;
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@ -344,12 +352,12 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
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else
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pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
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tmp = intel_de_read(dev_priv, intel_dp->output_reg);
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tmp = intel_de_read(display, intel_dp->output_reg);
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pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
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if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
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u32 trans_dp = intel_de_read(dev_priv,
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u32 trans_dp = intel_de_read(display,
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TRANS_DP_CTL(crtc->pipe));
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if (trans_dp & TRANS_DP_ENH_FRAMING)
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@ -390,7 +398,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
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g4x_dp_get_m_n(pipe_config);
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if (port == PORT_A) {
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if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
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if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
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pipe_config->port_clock = 162000;
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else
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pipe_config->port_clock = 270000;
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@ -410,17 +418,18 @@ static void
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intel_dp_link_down(struct intel_encoder *encoder,
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const struct intel_crtc_state *old_crtc_state)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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enum port port = encoder->port;
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if (drm_WARN_ON(&dev_priv->drm,
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(intel_de_read(dev_priv, intel_dp->output_reg) &
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if (drm_WARN_ON(display->drm,
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(intel_de_read(display, intel_dp->output_reg) &
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DP_PORT_EN) == 0))
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return;
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drm_dbg_kms(&dev_priv->drm, "\n");
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drm_dbg_kms(display->drm, "\n");
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if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
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(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
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@ -430,12 +439,12 @@ intel_dp_link_down(struct intel_encoder *encoder,
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intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
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intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
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}
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intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(display, intel_dp->output_reg);
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intel_dp->DP &= ~DP_PORT_EN;
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intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(display, intel_dp->output_reg);
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/*
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* HW workaround for IBX, we need to move the port
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@ -454,12 +463,12 @@ intel_dp_link_down(struct intel_encoder *encoder,
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intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
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intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
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DP_LINK_TRAIN_PAT_1;
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intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(display, intel_dp->output_reg);
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intel_dp->DP &= ~DP_PORT_EN;
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intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(display, intel_dp->output_reg);
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intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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@ -480,7 +489,7 @@ static void g4x_dp_audio_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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if (!crtc_state->has_audio)
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@ -488,7 +497,7 @@ static void g4x_dp_audio_enable(struct intel_encoder *encoder,
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/* Enable audio presence detect */
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intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
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intel_de_write(i915, intel_dp->output_reg, intel_dp->DP);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_audio_codec_enable(encoder, crtc_state, conn_state);
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}
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@ -497,7 +506,7 @@ static void g4x_dp_audio_disable(struct intel_encoder *encoder,
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const struct intel_crtc_state *old_crtc_state,
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const struct drm_connector_state *old_conn_state)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_display *display = to_intel_display(encoder);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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if (!old_crtc_state->has_audio)
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@ -507,7 +516,7 @@ static void g4x_dp_audio_disable(struct intel_encoder *encoder,
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/* Disable audio presence detect */
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intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;
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intel_de_write(i915, intel_dp->output_reg, intel_dp->DP);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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}
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static void intel_disable_dp(struct intel_atomic_state *state,
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@ -596,7 +605,7 @@ cpt_set_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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u8 dp_train_pat)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_display *display = to_intel_display(intel_dp);
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intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
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@ -615,8 +624,8 @@ cpt_set_link_train(struct intel_dp *intel_dp,
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return;
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}
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intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(display, intel_dp->output_reg);
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}
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static void
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@ -624,7 +633,7 @@ g4x_set_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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u8 dp_train_pat)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_display *display = to_intel_display(intel_dp);
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intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
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@ -643,14 +652,14 @@ g4x_set_link_train(struct intel_dp *intel_dp,
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return;
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}
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intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(display, intel_dp->output_reg);
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}
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static void intel_dp_enable_port(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_display *display = to_intel_display(intel_dp);
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/* enable with pattern 1 (as per spec) */
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@ -665,8 +674,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
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*/
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intel_dp->DP |= DP_PORT_EN;
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intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(dev_priv, intel_dp->output_reg);
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intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
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intel_de_posting_read(display, intel_dp->output_reg);
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}
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static void intel_enable_dp(struct intel_atomic_state *state,
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@ -674,12 +683,13 @@ static void intel_enable_dp(struct intel_atomic_state *state,
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const struct intel_crtc_state *pipe_config,
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const struct drm_connector_state *conn_state)
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{
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struct intel_display *display = to_intel_display(state);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
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u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
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intel_wakeref_t wakeref;
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if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
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if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))
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return;
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with_intel_pps_lock(intel_dp, wakeref) {
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@ -1026,21 +1036,21 @@ static void
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g4x_set_signal_levels(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
u8 train_set = intel_dp->train_set[0];
|
||||
u32 signal_levels;
|
||||
|
||||
signal_levels = g4x_signal_levels(train_set);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
|
||||
drm_dbg_kms(display->drm, "Using signal levels %08x\n",
|
||||
signal_levels);
|
||||
|
||||
intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
|
||||
intel_dp->DP |= signal_levels;
|
||||
|
||||
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
||||
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
||||
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
|
||||
intel_de_posting_read(display, intel_dp->output_reg);
|
||||
}
|
||||
|
||||
/* SNB CPU eDP voltage swing and pre-emphasis control */
|
||||
|
|
@ -1074,21 +1084,21 @@ static void
|
|||
snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
u8 train_set = intel_dp->train_set[0];
|
||||
u32 signal_levels;
|
||||
|
||||
signal_levels = snb_cpu_edp_signal_levels(train_set);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
|
||||
drm_dbg_kms(display->drm, "Using signal levels %08x\n",
|
||||
signal_levels);
|
||||
|
||||
intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
|
||||
intel_dp->DP |= signal_levels;
|
||||
|
||||
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
||||
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
||||
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
|
||||
intel_de_posting_read(display, intel_dp->output_reg);
|
||||
}
|
||||
|
||||
/* IVB CPU eDP voltage swing and pre-emphasis control */
|
||||
|
|
@ -1126,21 +1136,21 @@ static void
|
|||
ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
||||
u8 train_set = intel_dp->train_set[0];
|
||||
u32 signal_levels;
|
||||
|
||||
signal_levels = ivb_cpu_edp_signal_levels(train_set);
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
|
||||
drm_dbg_kms(display->drm, "Using signal levels %08x\n",
|
||||
signal_levels);
|
||||
|
||||
intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
|
||||
intel_dp->DP |= signal_levels;
|
||||
|
||||
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
||||
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
||||
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
|
||||
intel_de_posting_read(display, intel_dp->output_reg);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1185,15 +1195,15 @@ intel_dp_hotplug(struct intel_encoder *encoder,
|
|||
|
||||
static bool ibx_digital_port_connected(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
|
||||
|
||||
return intel_de_read(dev_priv, SDEISR) & bit;
|
||||
return intel_de_read(display, SDEISR) & bit;
|
||||
}
|
||||
|
||||
static bool g4x_digital_port_connected(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
u32 bit;
|
||||
|
||||
switch (encoder->hpd_pin) {
|
||||
|
|
@ -1211,15 +1221,15 @@ static bool g4x_digital_port_connected(struct intel_encoder *encoder)
|
|||
return false;
|
||||
}
|
||||
|
||||
return intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv)) & bit;
|
||||
return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;
|
||||
}
|
||||
|
||||
static bool ilk_digital_port_connected(struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
||||
u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
|
||||
struct intel_display *display = to_intel_display(encoder);
|
||||
u32 bit = display->hotplug.hpd[encoder->hpd_pin];
|
||||
|
||||
return intel_de_read(dev_priv, DEISR) & bit;
|
||||
return intel_de_read(display, DEISR) & bit;
|
||||
}
|
||||
|
||||
static void g4x_dp_suspend_complete(struct intel_encoder *encoder)
|
||||
|
|
@ -1241,7 +1251,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
|
|||
|
||||
enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
struct intel_display *display = to_intel_display(intel_dp);
|
||||
struct drm_i915_private *dev_priv = to_i915(display->drm);
|
||||
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
||||
enum pipe pipe;
|
||||
|
||||
|
|
@ -1254,10 +1265,11 @@ enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
|
|||
|
||||
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
|
||||
{
|
||||
struct intel_display *display = to_intel_display(encoder->dev);
|
||||
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
|
||||
|
||||
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
|
||||
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
|
||||
|
||||
intel_dp->reset_link_params = true;
|
||||
|
||||
|
|
@ -1293,7 +1305,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
|
|||
|
||||
/* FIXME bail? */
|
||||
if (!devdata)
|
||||
drm_dbg_kms(&dev_priv->drm, "No VBT child device for DP-%c\n",
|
||||
drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",
|
||||
port_name(port));
|
||||
|
||||
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
|
||||
|
|
@ -1313,7 +1325,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
|
|||
|
||||
mutex_init(&dig_port->hdcp_mutex);
|
||||
|
||||
if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
|
||||
if (drm_encoder_init(display->drm, &intel_encoder->base,
|
||||
&intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
|
||||
"DP %c", port_name(port)))
|
||||
goto err_encoder_init;
|
||||
|
|
@ -1397,7 +1409,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
|
|||
|
||||
dig_port->hpd_pulse = intel_dp_hpd_pulse;
|
||||
|
||||
if (HAS_GMCH(dev_priv)) {
|
||||
if (HAS_GMCH(display)) {
|
||||
dig_port->connected = g4x_digital_port_connected;
|
||||
} else {
|
||||
if (port == PORT_A)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user