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Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', 'pl', 'spear' and 'versatile' into devel

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This commit is contained in:
Russell King 2010-07-31 14:19:35 +01:00
commit b31fc7af78
192 changed files with 4175 additions and 1319 deletions
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53
arch/arm/Kconfig
View File

@ -10,6 +10,7 @@ config ARM
default y
select HAVE_AOUT
select HAVE_IDE
select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_ATOMIC64 if (!CPU_32v6K)
@ -24,6 +25,7 @@ config ARM
select HAVE_KERNEL_LZMA
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_REGS_AND_STACK_ACCESS_API
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
@ -704,7 +706,6 @@ config ARCH_SHARK
config ARCH_LH7A40X
bool "Sharp LH7A40X"
select CPU_ARM922T
select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
select ARCH_USES_GETTIMEOFFSET
help
@ -1016,11 +1017,6 @@ endmenu
source "arch/arm/common/Kconfig"
config FORCE_MAX_ZONEORDER
int
depends on SA1111
default "9"
menu "Bus support"
config ARM_AMBA
@ -1157,9 +1153,10 @@ config HOTPLUG_CPU
config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
default y
select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
@ -1226,10 +1223,6 @@ config OABI_COMPAT
config ARCH_HAS_HOLES_MEMORYMODEL
bool
# Discontigmem is deprecated
config ARCH_DISCONTIGMEM_ENABLE
bool
config ARCH_SPARSEMEM_ENABLE
bool
@ -1237,13 +1230,7 @@ config ARCH_SPARSEMEM_DEFAULT
def_bool ARCH_SPARSEMEM_ENABLE
config ARCH_SELECT_MEMORY_MODEL
def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
config NODES_SHIFT
int
default "4" if ARCH_LH7A40X
default "2"
depends on NEED_MULTIPLE_NODES
def_bool ARCH_SPARSEMEM_ENABLE
config HIGHMEM
bool "High Memory Support (EXPERIMENTAL)"
@ -1275,8 +1262,36 @@ config HW_PERF_EVENTS
Enable hardware performance counter support for perf events. If
disabled, perf events will use software events only.
config SPARSE_IRQ
bool "Support sparse irq numbering"
depends on EXPERIMENTAL
help
This enables support for sparse irqs. This is useful in general
as most CPUs have a fairly sparse array of IRQ vectors, which
the irq_desc then maps directly on to. Systems with a high
number of off-chip IRQs will want to treat this as
experimental until they have been independently verified.
If you don't know what to do here, say N.
source "mm/Kconfig"
config FORCE_MAX_ZONEORDER
int "Maximum zone order" if ARCH_SHMOBILE
range 11 64 if ARCH_SHMOBILE
default "9" if SA1111
default "11"
help
The kernel memory allocator divides physically contiguous memory
blocks into "zones", where each zone is a power of two number of
pages. This option selects the largest power of two that the kernel
keeps in the memory allocator. If you need to allocate very large
blocks of physically contiguous memory, then you may need to
increase this value.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
config LEDS
bool "Timer and CPU usage LEDs"
depends on ARCH_CDB89712 || ARCH_EBSA110 || \

46
arch/arm/common/gic.c
View File

@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq)
spin_unlock(&irq_controller_lock);
}
static int gic_set_type(unsigned int irq, unsigned int type)
{
void __iomem *base = gic_dist_base(irq);
unsigned int gicirq = gic_irq(irq);
u32 enablemask = 1 << (gicirq % 32);
u32 enableoff = (gicirq / 32) * 4;
u32 confmask = 0x2 << ((gicirq % 16) * 2);
u32 confoff = (gicirq / 16) * 4;
bool enabled = false;
u32 val;
/* Interrupt configuration for SGIs can't be changed */
if (gicirq < 16)
return -EINVAL;
if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
spin_lock(&irq_controller_lock);
val = readl(base + GIC_DIST_CONFIG + confoff);
if (type == IRQ_TYPE_LEVEL_HIGH)
val &= ~confmask;
else if (type == IRQ_TYPE_EDGE_RISING)
val |= confmask;
/*
* As recommended by the spec, disable the interrupt before changing
* the configuration
*/
if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
enabled = true;
}
writel(val, base + GIC_DIST_CONFIG + confoff);
if (enabled)
writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
spin_unlock(&irq_controller_lock);
return 0;
}
#ifdef CONFIG_SMP
static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
{
@ -161,6 +206,7 @@ static struct irq_chip gic_chip = {
.ack = gic_ack_irq,
.mask = gic_mask_irq,
.unmask = gic_unmask_irq,
.set_type = gic_set_type,
#ifdef CONFIG_SMP
.set_affinity = gic_set_cpu,
#endif

5
arch/arm/common/sa1111.c
View File

@ -185,13 +185,10 @@ static struct sa1111_dev_info sa1111_devices[] = {
},
};
void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes)
void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
{
unsigned int sz = SZ_1M >> PAGE_SHIFT;
if (node != 0)
sz = 0;
size[1] = size[0] - sz;
size[0] = sz;
}

1
arch/arm/include/asm/hwcap.h
View File

@ -19,6 +19,7 @@
#define HWCAP_NEON 4096
#define HWCAP_VFPv3 8192
#define HWCAP_VFPv3D16 16384
#define HWCAP_TLS 32768
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
/*

2
arch/arm/include/asm/irq.h
View File

@ -7,6 +7,8 @@
#define irq_canonicalize(i) (i)
#endif
#define NR_IRQS_LEGACY 16
/*
* Use this value to indicate lack of interrupt
* capability

22
arch/arm/include/asm/kexec.h
View File

@ -19,10 +19,26 @@
#ifndef __ASSEMBLY__
struct kimage;
/* Provide a dummy definition to avoid build failures. */
/**
* crash_setup_regs() - save registers for the panic kernel
* @newregs: registers are saved here
* @oldregs: registers to be saved (may be %NULL)
*
* Function copies machine registers from @oldregs to @newregs. If @oldregs is
* %NULL then current registers are stored there.
*/
static inline void crash_setup_regs(struct pt_regs *newregs,
struct pt_regs *oldregs) { }
struct pt_regs *oldregs)
{
if (oldregs) {
memcpy(newregs, oldregs, sizeof(*newregs));
} else {
__asm__ __volatile__ ("stmia %0, {r0 - r15}"
: : "r" (&newregs->ARM_r0));
__asm__ __volatile__ ("mrs %0, cpsr"
: "=r" (newregs->ARM_cpsr));
}
}
#endif /* __ASSEMBLY__ */

2
arch/arm/include/asm/mach/arch.h
View File

@ -20,6 +20,7 @@ struct machine_desc {
* by assembler code in head.S, head-common.S
*/
unsigned int nr; /* architecture number */
unsigned int nr_irqs; /* number of IRQs */
unsigned int phys_io; /* start of physical io */
unsigned int io_pg_offst; /* byte offset for io
* page tabe entry */
@ -37,6 +38,7 @@ struct machine_desc {
void (*fixup)(struct machine_desc *,
struct tag *, char **,
struct meminfo *);
void (*reserve)(void);/* reserve mem blocks */
void (*map_io)(void);/* IO mapping function */
void (*init_irq)(void);
struct sys_timer *timer; /* system tick timer */

1
arch/arm/include/asm/mach/irq.h
View File

@ -17,6 +17,7 @@ struct seq_file;
/*
* This is internal. Do not use it.
*/
extern unsigned int arch_nr_irqs;
extern void (*init_arch_irq)(void);
extern void init_FIQ(void);
extern int show_fiq_list(struct seq_file *, void *);

16
arch/arm/include/asm/memblock.h Normal file
View File

@ -0,0 +1,16 @@
#ifndef _ASM_ARM_MEMBLOCK_H
#define _ASM_ARM_MEMBLOCK_H
#ifdef CONFIG_MMU
extern phys_addr_t lowmem_end_addr;
#define MEMBLOCK_REAL_LIMIT lowmem_end_addr
#else
#define MEMBLOCK_REAL_LIMIT 0
#endif
struct meminfo;
struct machine_desc;
extern void arm_memblock_init(struct meminfo *, struct machine_desc *);
#endif

67
arch/arm/include/asm/memory.h
View File

@ -158,7 +158,7 @@
#endif
#ifndef arch_adjust_zones
#define arch_adjust_zones(node,size,holes) do { } while (0)
#define arch_adjust_zones(size,holes) do { } while (0)
#elif !defined(CONFIG_ZONE_DMA)
#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
#endif
@ -234,76 +234,11 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
* virt_to_page(k) convert a _valid_ virtual address to struct page *
* virt_addr_valid(k) indicates whether a virtual address is valid
*/
#ifndef CONFIG_DISCONTIGMEM
#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
#define PHYS_TO_NID(addr) (0)
#else /* CONFIG_DISCONTIGMEM */
/*
* This is more complex. We have a set of mem_map arrays spread
* around in memory.
*/
#include <linux/numa.h>
#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn)
#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
#define virt_to_page(kaddr) \
(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < MAX_NUMNODES)
/*
* Common discontigmem stuff.
* PHYS_TO_NID is used by the ARM kernel/setup.c
*/
#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT)
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and returns the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
/*
* Given a page frame number, find the owning node of the memory
* and returns the mem_map of that node.
*/
#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
#ifdef NODE_MEM_SIZE_BITS
#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1)
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) \
(((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
/*
* Given a page frame number, convert it to a node id.
*/
#define PFN_TO_NID(pfn) \
(((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
#endif /* NODE_MEM_SIZE_BITS */
#endif /* !CONFIG_DISCONTIGMEM */
/*
* Optional coherency support. Currently used only by selected
* Intel XSC3-based systems.

30
arch/arm/include/asm/mmzone.h
View File

@ -1,30 +0,0 @@
/*
* arch/arm/include/asm/mmzone.h
*
* 1999-12-29 Nicolas Pitre Created
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_MMZONE_H
#define __ASM_MMZONE_H
/*
* Currently defined in arch/arm/mm/discontig.c
*/
extern pg_data_t discontig_node_data[];
/*
* Return a pointer to the node data for node n.
*/
#define NODE_DATA(nid) (&discontig_node_data[nid])
/*
* NODE_MEM_MAP gives the kaddr for the mem_map of the node.
*/
#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map)
#include <mach/memory.h>
#endif

36
arch/arm/include/asm/ptrace.h
View File

@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs);
#define predicate(x) ((x) & 0xf0000000)
#define PREDICATE_ALWAYS 0xe0000000
/*
* kprobe-based event tracer support
*/
#include <linux/stddef.h>
#include <linux/types.h>
#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
extern int regs_query_register_offset(const char *name);
extern const char *regs_query_register_name(unsigned int offset);
extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
unsigned int n);
/**
* regs_get_register() - get register value from its offset
* @regs: pt_regs from which register value is gotten
* @offset: offset number of the register.
*
* regs_get_register returns the value of a register whose offset from @regs.
* The @offset is the offset of the register in struct pt_regs.
* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
*/
static inline unsigned long regs_get_register(struct pt_regs *regs,
unsigned int offset)
{
if (unlikely(offset > MAX_REG_OFFSET))
return 0;
return *(unsigned long *)((unsigned long)regs + offset);
}
/* Valid only for Kernel mode traps. */
static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
{
return regs->ARM_sp;
}
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */

8
arch/arm/include/asm/setup.h
View File

@ -201,8 +201,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
struct membank {
unsigned long start;
unsigned long size;
unsigned short node;
unsigned short highmem;
unsigned int highmem;
};
struct meminfo {
@ -212,9 +211,8 @@ struct meminfo {
extern struct meminfo meminfo;
#define for_each_nodebank(iter,mi,no) \
for (iter = 0; iter < (mi)->nr_banks; iter++) \
if ((mi)->bank[iter].node == no)
#define for_each_bank(iter,mi) \
for (iter = 0; iter < (mi)->nr_banks; iter++)
#define bank_pfn_start(bank) __phys_to_pfn((bank)->start)
#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size)

46
arch/arm/include/asm/tls.h Normal file
View File

@ -0,0 +1,46 @@
#ifndef __ASMARM_TLS_H
#define __ASMARM_TLS_H
#ifdef __ASSEMBLY__
.macro set_tls_none, tp, tmp1, tmp2
.endm
.macro set_tls_v6k, tp, tmp1, tmp2
mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
.endm
.macro set_tls_v6, tp, tmp1, tmp2
ldr \tmp1, =elf_hwcap
ldr \tmp1, [\tmp1, #0]
mov \tmp2, #0xffff0fff
tst \tmp1, #HWCAP_TLS @ hardware TLS available?
mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
.endm
.macro set_tls_software, tp, tmp1, tmp2
mov \tmp1, #0xffff0fff
str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
.endm
#endif
#ifdef CONFIG_TLS_REG_EMUL
#define tls_emu 1
#define has_tls_reg 1
#define set_tls set_tls_none
#elif __LINUX_ARM_ARCH__ >= 7 || \
(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
#define tls_emu 0
#define has_tls_reg 1
#define set_tls set_tls_v6k
#elif __LINUX_ARM_ARCH__ == 6
#define tls_emu 0
#define has_tls_reg (elf_hwcap & HWCAP_TLS)
#define set_tls set_tls_v6
#else
#define tls_emu 0
#define has_tls_reg 0
#define set_tls set_tls_software
#endif
#endif /* __ASMARM_TLS_H */

18
arch/arm/include/asm/vfpmacros.h
View File

@ -3,6 +3,8 @@
*
* Assembler-only file containing VFP macros and register definitions.
*/
#include <asm/hwcap.h>
#include "vfp.h"
@ Macros to allow building with old toolkits (with no VFP support)
@ -22,11 +24,19 @@
LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
#endif
#ifdef CONFIG_VFPv3
#if __LINUX_ARM_ARCH__ <= 6
ldr \tmp, =elf_hwcap @ may not have MVFR regs
ldr \tmp, [\tmp, #0]
tst \tmp, #HWCAP_VFPv3D16
ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
addne \base, \base, #32*4 @ step over unused register space
#else
VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
cmp \tmp, #2 @ 32 x 64bit registers?
ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
addne \base, \base, #32*4 @ step over unused register space
#endif
#endif
.endm
@ -38,10 +48,18 @@
STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
#endif
#ifdef CONFIG_VFPv3
#if __LINUX_ARM_ARCH__ <= 6
ldr \tmp, =elf_hwcap @ may not have MVFR regs
ldr \tmp, [\tmp, #0]
tst \tmp, #HWCAP_VFPv3D16
stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
addne \base, \base, #32*4 @ step over unused register space
#else
VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
cmp \tmp, #2 @ 32 x 64bit registers?
stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
addne \base, \base, #32*4 @ step over unused register space
#endif
#endif
.endm

1
arch/arm/kernel/Makefile
View File

@ -39,6 +39,7 @@ obj-$(CONFIG_ARM_THUMBEE) += thumbee.o
obj-$(CONFIG_KGDB) += kgdb.o
obj-$(CONFIG_ARM_UNWIND) += unwind.o
obj-$(CONFIG_HAVE_TCM) += tcm.o
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312

60
arch/arm/kernel/crash_dump.c Normal file
View File

@ -0,0 +1,60 @@
/*
* arch/arm/kernel/crash_dump.c
*
* Copyright (C) 2010 Nokia Corporation.
* Author: Mika Westerberg
*
* This code is taken from arch/x86/kernel/crash_dump_64.c
* Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
* Copyright (C) IBM Corporation, 2004. All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/errno.h>
#include <linux/crash_dump.h>
#include <linux/uaccess.h>
#include <linux/io.h>
/* stores the physical address of elf header of crash image */
unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
/**
* copy_oldmem_page() - copy one page from old kernel memory
* @pfn: page frame number to be copied
* @buf: buffer where the copied page is placed
* @csize: number of bytes to copy
* @offset: offset in bytes into the page
* @userbuf: if set, @buf is int he user address space
*
* This function copies one page from old kernel memory into buffer pointed by
* @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
* copied or negative error in case of failure.
*/
ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
size_t csize, unsigned long offset,
int userbuf)
{
void *vaddr;
if (!csize)
return 0;
vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
if (!vaddr)
return -ENOMEM;
if (userbuf) {
if (copy_to_user(buf, vaddr + offset, csize)) {
iounmap(vaddr);
return -EFAULT;
}
} else {
memcpy(buf, vaddr + offset, csize);
}
iounmap(vaddr);
return csize;
}

23
arch/arm/kernel/entry-armv.S
View File

@ -22,6 +22,7 @@
#include <asm/thread_notify.h>
#include <asm/unwind.h>
#include <asm/unistd.h>
#include <asm/tls.h>
#include "entry-header.S"
@ -735,12 +736,7 @@ ENTRY(__switch_to)
#ifdef CONFIG_MMU
ldr r6, [r2, #TI_CPU_DOMAIN]
#endif
#if defined(CONFIG_HAS_TLS_REG)
mcr p15, 0, r3, c13, c0, 3 @ set TLS register
#elif !defined(CONFIG_TLS_REG_EMUL)
mov r4, #0xffff0fff
str r3, [r4, #-15] @ TLS val at 0xffff0ff0
#endif
set_tls r3, r4, r5
#ifdef CONFIG_MMU
mcr p15, 0, r6, c3, c0, 0 @ Set domain register
#endif
@ -1005,17 +1001,12 @@ kuser_cmpxchg_fixup:
*/
__kuser_get_tls: @ 0xffff0fe0
#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
#else
mrc p15, 0, r0, c13, c0, 3 @ read TLS register
#endif
ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
usr_ret lr
.rep 5
.word 0 @ pad up to __kuser_helper_version
.endr
mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
.rep 4
.word 0 @ 0xffff0ff0 software TLS value, then
.endr @ pad up to __kuser_helper_version
/*
* Reference declaration:

41
arch/arm/kernel/irq.c
View File

@ -47,12 +47,14 @@
#define irq_finish(irq) do { } while (0)
#endif
unsigned int arch_nr_irqs;
void (*init_arch_irq)(void) __initdata = NULL;
unsigned long irq_err_count;
int show_interrupts(struct seq_file *p, void *v)
{
int i = *(loff_t *) v, cpu;
struct irq_desc *desc;
struct irqaction * action;
unsigned long flags;
@ -67,24 +69,25 @@ int show_interrupts(struct seq_file *p, void *v)
seq_putc(p, '\n');
}
if (i < NR_IRQS) {
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
action = irq_desc[i].action;
if (i < nr_irqs) {
desc = irq_to_desc(i);
raw_spin_lock_irqsave(&desc->lock, flags);
action = desc->action;
if (!action)
goto unlock;
seq_printf(p, "%3d: ", i);
for_each_present_cpu(cpu)
seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
seq_printf(p, " %10s", desc->chip->name ? : "-");
seq_printf(p, " %s", action->name);
for (action = action->next; action; action = action->next)
seq_printf(p, ", %s", action->name);
seq_putc(p, '\n');
unlock:
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
} else if (i == NR_IRQS) {
raw_spin_unlock_irqrestore(&desc->lock, flags);
} else if (i == nr_irqs) {
#ifdef CONFIG_FIQ
show_fiq_list(p, v);
#endif
@ -112,7 +115,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
* Some hardware gives randomly wrong interrupts. Rather
* than crashing, do something sensible.
*/
if (unlikely(irq >= NR_IRQS)) {
if (unlikely(irq >= nr_irqs)) {
if (printk_ratelimit())
printk(KERN_WARNING "Bad IRQ%u\n", irq);
ack_bad_irq(irq);
@ -132,12 +135,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
struct irq_desc *desc;
unsigned long flags;
if (irq >= NR_IRQS) {
if (irq >= nr_irqs) {
printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
return;
}
desc = irq_desc + irq;
desc = irq_to_desc(irq);
raw_spin_lock_irqsave(&desc->lock, flags);
desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
if (iflags & IRQF_VALID)
@ -151,14 +154,25 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
void __init init_IRQ(void)
{
struct irq_desc *desc;
int irq;
for (irq = 0; irq < NR_IRQS; irq++)
irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE;
for (irq = 0; irq < nr_irqs; irq++) {
desc = irq_to_desc_alloc_node(irq, 0);
desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
}
init_arch_irq();
}
#ifdef CONFIG_SPARSE_IRQ
int __init arch_probe_nr_irqs(void)
{
nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
return 0;
}
#endif
#ifdef CONFIG_HOTPLUG_CPU
static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
@ -178,10 +192,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
void migrate_irqs(void)
{
unsigned int i, cpu = smp_processor_id();
struct irq_desc *desc;
for (i = 0; i < NR_IRQS; i++) {
struct irq_desc *desc = irq_desc + i;
for_each_irq_desc(i, desc) {
if (desc->node == cpu) {
unsigned int newcpu = cpumask_any_and(desc->affinity,
cpu_online_mask);

4
arch/arm/kernel/machine_kexec.c
View File

@ -43,6 +43,10 @@ void machine_shutdown(void)
void machine_crash_shutdown(struct pt_regs *regs)
{
local_irq_disable();
crash_save_cpu(regs, smp_processor_id());
printk(KERN_INFO "Loading crashdump kernel...\n");
}
void machine_kexec(struct kimage *image)

96
arch/arm/kernel/ptrace.c
View File

@ -52,6 +52,102 @@
#define BREAKINST_THUMB 0xde01
#endif
struct pt_regs_offset {
const char *name;
int offset;
};
#define REG_OFFSET_NAME(r) \
{.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
#define REG_OFFSET_END {.name = NULL, .offset = 0}
static const struct pt_regs_offset regoffset_table[] = {
REG_OFFSET_NAME(r0),
REG_OFFSET_NAME(r1),
REG_OFFSET_NAME(r2),
REG_OFFSET_NAME(r3),
REG_OFFSET_NAME(r4),
REG_OFFSET_NAME(r5),
REG_OFFSET_NAME(r6),
REG_OFFSET_NAME(r7),
REG_OFFSET_NAME(r8),
REG_OFFSET_NAME(r9),
REG_OFFSET_NAME(r10),
REG_OFFSET_NAME(fp),
REG_OFFSET_NAME(ip),
REG_OFFSET_NAME(sp),
REG_OFFSET_NAME(lr),
REG_OFFSET_NAME(pc),
REG_OFFSET_NAME(cpsr),
REG_OFFSET_NAME(ORIG_r0),
REG_OFFSET_END,
};
/**
* regs_query_register_offset() - query register offset from its name
* @name: the name of a register
*
* regs_query_register_offset() returns the offset of a register in struct
* pt_regs from its name. If the name is invalid, this returns -EINVAL;
*/
int regs_query_register_offset(const char *name)
{
const struct pt_regs_offset *roff;
for (roff = regoffset_table; roff->name != NULL; roff++)
if (!strcmp(roff->name, name))
return roff->offset;
return -EINVAL;
}
/**
* regs_query_register_name() - query register name from its offset
* @offset: the offset of a register in struct pt_regs.
*
* regs_query_register_name() returns the name of a register from its
* offset in struct pt_regs. If the @offset is invalid, this returns NULL;
*/
const char *regs_query_register_name(unsigned int offset)
{
const struct pt_regs_offset *roff;
for (roff = regoffset_table; roff->name != NULL; roff++)
if (roff->offset == offset)
return roff->name;
return NULL;
}
/**
* regs_within_kernel_stack() - check the address in the stack
* @regs: pt_regs which contains kernel stack pointer.
* @addr: address which is checked.
*
* regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
* If @addr is within the kernel stack, it returns true. If not, returns false.
*/
bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
{
return ((addr & ~(THREAD_SIZE - 1)) ==
(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
}
/**
* regs_get_kernel_stack_nth() - get Nth entry of the stack
* @regs: pt_regs which contains kernel stack pointer.
* @n: stack entry number.
*
* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
* is specified by @regs. If the @n th entry is NOT in the kernel stack,
* this returns 0.
*/
unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
{
unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
addr += n;
if (regs_within_kernel_stack(regs, (unsigned long)addr))
return *addr;
else
return 0;
}
/*
* this routine will get a word off of the processes privileged stack.
* the offset is how far from the base addr as stored in the THREAD.

6
arch/arm/kernel/relocate_kernel.S
View File

@ -10,6 +10,12 @@ relocate_new_kernel:
ldr r0,kexec_indirection_page
ldr r1,kexec_start_address
/*
* If there is no indirection page (we are doing crashdumps)
* skip any relocation.
*/
cmp r0, #0
beq 2f
0: /* top, read another word for the indirection page */
ldr r3, [r0],#4

100
arch/arm/kernel/setup.c
View File

@ -19,12 +19,15 @@
#include <linux/seq_file.h>
#include <linux/screen_info.h>
#include <linux/init.h>
#include <linux/kexec.h>
#include <linux/crash_dump.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <linux/fs.h>
#include <linux/proc_fs.h>
#include <linux/memblock.h>
#include <asm/unified.h>
#include <asm/cpu.h>
@ -269,6 +272,21 @@ static void __init cacheid_init(void)
extern struct proc_info_list *lookup_processor_type(unsigned int);
extern struct machine_desc *lookup_machine_type(unsigned int);
static void __init feat_v6_fixup(void)
{
int id = read_cpuid_id();
if ((id & 0xff0f0000) != 0x41070000)
return;
/*
* HWCAP_TLS is available only on 1136 r1p0 and later,
* see also kuser_get_tls_init.
*/
if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
elf_hwcap &= ~HWCAP_TLS;
}
static void __init setup_processor(void)
{
struct proc_info_list *list;
@ -311,6 +329,8 @@ static void __init setup_processor(void)
elf_hwcap &= ~HWCAP_THUMB;
#endif
feat_v6_fixup();
cacheid_init();
cpu_proc_init();
}
@ -402,13 +422,12 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
size -= start & ~PAGE_MASK;
bank->start = PAGE_ALIGN(start);
bank->size = size & PAGE_MASK;
bank->node = PHYS_TO_NID(start);
/*
* Check whether this memory region has non-zero size or
* invalid node number.
*/
if (bank->size == 0 || bank->node >= MAX_NUMNODES)
if (bank->size == 0)
return -EINVAL;
meminfo.nr_banks++;
@ -663,6 +682,79 @@ static int __init customize_machine(void)
}
arch_initcall(customize_machine);
#ifdef CONFIG_KEXEC
static inline unsigned long long get_total_mem(void)
{
unsigned long total;
total = max_low_pfn - min_low_pfn;
return total << PAGE_SHIFT;
}
/**
* reserve_crashkernel() - reserves memory are for crash kernel
*
* This function reserves memory area given in "crashkernel=" kernel command
* line parameter. The memory reserved is used by a dump capture kernel when
* primary kernel is crashing.
*/
static void __init reserve_crashkernel(void)
{
unsigned long long crash_size, crash_base;
unsigned long long total_mem;
int ret;
total_mem = get_total_mem();
ret = parse_crashkernel(boot_command_line, total_mem,
&crash_size, &crash_base);
if (ret)
return;
ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
if (ret < 0) {
printk(KERN_WARNING "crashkernel reservation failed - "
"memory is in use (0x%lx)\n", (unsigned long)crash_base);
return;
}
printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
"for crashkernel (System RAM: %ldMB)\n",
(unsigned long)(crash_size >> 20),
(unsigned long)(crash_base >> 20),
(unsigned long)(total_mem >> 20));
crashk_res.start = crash_base;
crashk_res.end = crash_base + crash_size - 1;
insert_resource(&iomem_resource, &crashk_res);
}
#else
static inline void reserve_crashkernel(void) {}
#endif /* CONFIG_KEXEC */
/*
* Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
* is_kdump_kernel() to determine if we are booting after a panic. Hence
* ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
*/
#ifdef CONFIG_CRASH_DUMP
/*
* elfcorehdr= specifies the location of elf core header stored by the crashed
* kernel. This option will be passed by kexec loader to the capture kernel.
*/
static int __init setup_elfcorehdr(char *arg)
{
char *end;
if (!arg)
return -EINVAL;
elfcorehdr_addr = memparse(arg, &end);
return end > arg ? 0 : -EINVAL;
}
early_param("elfcorehdr", setup_elfcorehdr);
#endif /* CONFIG_CRASH_DUMP */
void __init setup_arch(char **cmdline_p)
{
struct tag *tags = (struct tag *)&init_tags;
@ -716,12 +808,15 @@ void __init setup_arch(char **cmdline_p)
parse_early_param();
arm_memblock_init(&meminfo, mdesc);
paging_init(mdesc);
request_standard_resources(&meminfo, mdesc);
#ifdef CONFIG_SMP
smp_init_cpus();
#endif
reserve_crashkernel();
cpu_init();
tcm_init();
@ -729,6 +824,7 @@ void __init setup_arch(char **cmdline_p)
/*
* Set up various architecture-specific pointers
*/
arch_nr_irqs = mdesc->nr_irqs;
init_arch_irq = mdesc->init_irq;
system_timer = mdesc->timer;
init_machine = mdesc->init_machine;

41
arch/arm/kernel/traps.c
View File

@ -30,6 +30,7 @@
#include <asm/unistd.h>
#include <asm/traps.h>
#include <asm/unwind.h>
#include <asm/tls.h>
#include "ptrace.h"
#include "signal.h"
@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
case NR(set_tls):
thread->tp_value = regs->ARM_r0;
#if defined(CONFIG_HAS_TLS_REG)
asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
#elif !defined(CONFIG_TLS_REG_EMUL)
/*
* User space must never try to access this directly.
* Expect your app to break eventually if you do so.
* The user helper at 0xffff0fe0 must be used instead.
* (see entry-armv.S for details)
*/
*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
#endif
if (tls_emu)
return 0;
if (has_tls_reg) {
asm ("mcr p15, 0, %0, c13, c0, 3"
: : "r" (regs->ARM_r0));
} else {
/*
* User space must never try to access this directly.
* Expect your app to break eventually if you do so.
* The user helper at 0xffff0fe0 must be used instead.
* (see entry-armv.S for details)
*/
*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
}
return 0;
#ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
@ -743,6 +747,16 @@ void __init trap_init(void)
return;
}
static void __init kuser_get_tls_init(unsigned long vectors)
{
/*
* vectors + 0xfe0 = __kuser_get_tls
* vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
*/
if (tls_emu || has_tls_reg)
memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
}
void __init early_trap_init(void)
{
unsigned long vectors = CONFIG_VECTORS_BASE;
@ -760,6 +774,11 @@ void __init early_trap_init(void)
memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);
memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
/*
* Do processor specific fixups for the kuser helpers
*/
kuser_get_tls_init(vectors);
/*
* Copy signal return handlers into the vector page, and
* set sigreturn to be a pointer to these.

10
arch/arm/mach-aaec2000/include/mach/memory.h
View File

@ -14,14 +14,4 @@
#define PHYS_OFFSET UL(0xf0000000)
/*
* The nodes are the followings:
*
* node 0: 0xf000.0000 - 0xf3ff.ffff
* node 1: 0xf400.0000 - 0xf7ff.ffff
* node 2: 0xf800.0000 - 0xfbff.ffff
* node 3: 0xfc00.0000 - 0xffff.ffff
*/
#define NODE_MEM_SIZE_BITS 26
#endif /* __ASM_ARCH_MEMORY_H */

11
arch/arm/mach-at91/Kconfig
View File

@ -366,6 +366,17 @@ config MACH_STAMP9G20
endif
if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
comment "AT91SAM9260/AT91SAM9G20 boards"
config MACH_SNAPPER_9260
bool "Bluewater Systems Snapper 9260/9G20 module"
help
Select this if you are using the Bluewater Systems Snapper 9260 or
Snapper 9G20 modules.
<http://www.bluewatersys.com/>
endif
# ----------------------------------------------------------
if ARCH_AT91SAM9G45

3
arch/arm/mach-at91/Makefile
View File

@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
# AT91SAM9260/AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
# AT91SAM9G45 board-specific support
obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o

11
arch/arm/mach-at91/at91sam9g45.c
View File

@ -20,6 +20,7 @@
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include <mach/cpu.h>
#include "generic.h"
#include "clock.h"
@ -176,6 +177,13 @@ static struct clk mmc1_clk = {
.type = CLK_TYPE_PERIPHERAL,
};
/* Video decoder clock - Only for sam9m10/sam9m11 */
static struct clk vdec_clk = {
.name = "vdec_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
.type = CLK_TYPE_PERIPHERAL,
};
/* One additional fake clock for ohci */
static struct clk ohci_clk = {
.name = "ohci_clk",
@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void)
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
clk_register(&vdec_clk);
clk_register(&pck0);
clk_register(&pck1);
}

45
arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
View File

@ -26,6 +26,9 @@
#include <linux/spi/spi.h>
#include <linux/spi/at73c213.h>
#include <linux/clk.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/consumer.h>
#include <mach/hardware.h>
#include <asm/setup.h>
@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = {
}
};
#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
REGULATOR_SUPPLY("AVDD", "0-001b"),
REGULATOR_SUPPLY("HPVDD", "0-001b"),
REGULATOR_SUPPLY("DBVDD", "0-001b"),
REGULATOR_SUPPLY("DCVDD", "0-001b"),
};
static struct regulator_init_data ek_avdd_reg_init_data = {
.constraints = {
.name = "3V3",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = ek_audio_consumer_supplies,
.num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
};
static struct fixed_voltage_config ek_vdd_pdata = {
.supply_name = "board-3V3",
.microvolts = 3300000,
.gpio = -EINVAL,
.enabled_at_boot = 0,
.init_data = &ek_avdd_reg_init_data,
};
static struct platform_device ek_voltage_regulator = {
.name = "reg-fixed-voltage",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &ek_vdd_pdata,
},
};
static void __init ek_add_regulators(void)
{
platform_device_register(&ek_voltage_regulator);
}
#else
static void __init ek_add_regulators(void) {}
#endif
static struct i2c_board_info __initdata ek_i2c_devices[] = {
{
I2C_BOARD_INFO("24c512", 0x50),
@ -256,6 +299,8 @@ static void __init ek_board_init(void)
ek_add_device_nand();
/* Ethernet */
at91_add_device_eth(&ek_macb_data);
/* Regulators */
ek_add_regulators();
/* MMC */
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
at91_add_device_mci(0, &ek_mmc_data);

45
arch/arm/mach-at91/board-sam9g20ek.c
View File

@ -27,6 +27,9 @@
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/clk.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/consumer.h>
#include <mach/hardware.h>
#include <asm/setup.h>
@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void)
static void __init ek_add_device_buttons(void) {}
#endif
#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
REGULATOR_SUPPLY("AVDD", "0-001b"),
REGULATOR_SUPPLY("HPVDD", "0-001b"),
REGULATOR_SUPPLY("DBVDD", "0-001b"),
REGULATOR_SUPPLY("DCVDD", "0-001b"),
};
static struct regulator_init_data ek_avdd_reg_init_data = {
.constraints = {
.name = "3V3",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = ek_audio_consumer_supplies,
.num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
};
static struct fixed_voltage_config ek_vdd_pdata = {
.supply_name = "board-3V3",
.microvolts = 3300000,
.gpio = -EINVAL,
.enabled_at_boot = 0,
.init_data = &ek_avdd_reg_init_data,
};
static struct platform_device ek_voltage_regulator = {
.name = "reg-fixed-voltage",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &ek_vdd_pdata,
},
};
static void __init ek_add_regulators(void)
{
platform_device_register(&ek_voltage_regulator);
}
#else
static void __init ek_add_regulators(void) {}
#endif
static struct i2c_board_info __initdata ek_i2c_devices[] = {
{
@ -294,6 +337,8 @@ static void __init ek_board_init(void)
ek_add_device_nand();
/* Ethernet */
at91_add_device_eth(&ek_macb_data);
/* Regulators */
ek_add_regulators();
/* MMC */
at91_add_device_mmc(0, &ek_mmc_data);
/* I2C */

189
arch/arm/mach-at91/board-snapper9260.c Normal file
View File

@ -0,0 +1,189 @@
/*
* linux/arch/arm/mach-at91/board-snapper9260.c
*
* Copyright (C) 2010 Bluewater System Ltd
*
* Author: Andre Renaud <andre@bluewatersys.com>
* Author: Ryan Mallon <ryan@bluewatersys.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/i2c/pca953x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/hardware.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include "sam9_smc.h"
#include "generic.h"
#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x))
static void __init snapper9260_map_io(void)
{
at91sam9260_initialize(18432000);
/* Debug on ttyS0 */
at91_register_uart(0, 0, 0);
at91_set_serial_console(0);
at91_register_uart(AT91SAM9260_ID_US0, 1,
ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_register_uart(AT91SAM9260_ID_US1, 2,
ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
}
static void __init snapper9260_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
static struct at91_usbh_data __initdata snapper9260_usbh_data = {
.ports = 2,
};
static struct at91_udc_data __initdata snapper9260_udc_data = {
.vbus_pin = SNAPPER9260_IO_EXP_GPIO(5),
.vbus_active_low = 1,
.vbus_polled = 1,
};
static struct at91_eth_data snapper9260_macb_data = {
.is_rmii = 1,
};
static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
{
.name = "Preboot",
.offset = 0,
.size = SZ_128K,
},
{
.name = "Bootloader",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K,
},
{
.name = "Environment",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
},
{
.name = "Kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
},
{
.name = "Filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct mtd_partition * __init
snapper9260_nand_partition_info(int size, int *num_partitions)
{
*num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
return snapper9260_nand_partitions;
}
static struct atmel_nand_data __initdata snapper9260_nand_data = {
.ale = 21,
.cle = 22,
.rdy_pin = AT91_PIN_PC13,
.partition_info = snapper9260_nand_partition_info,
.bus_width_16 = 0,
};
static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 0,
.ncs_write_setup = 0,
.nwe_setup = 0,
.ncs_read_pulse = 5,
.nrd_pulse = 2,
.ncs_write_pulse = 5,
.nwe_pulse = 2,
.read_cycle = 7,
.write_cycle = 7,
.mode = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE),
.tdf_cycles = 1,
};
static struct pca953x_platform_data snapper9260_io_expander_data = {
.gpio_base = SNAPPER9260_IO_EXP_GPIO(0),
};
static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
{
/* IO expander */
I2C_BOARD_INFO("max7312", 0x28),
.platform_data = &snapper9260_io_expander_data,
},
{
/* Audio codec */
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
{
/* RTC */
I2C_BOARD_INFO("isl1208", 0x6f),
},
};
static void __init snapper9260_add_device_nand(void)
{
at91_set_A_periph(AT91_PIN_PC14, 0);
sam9_smc_configure(3, &snapper9260_nand_smc_config);
at91_add_device_nand(&snapper9260_nand_data);
}
static void __init snapper9260_board_init(void)
{
at91_add_device_i2c(snapper9260_i2c_devices,
ARRAY_SIZE(snapper9260_i2c_devices));
at91_add_device_serial();
at91_add_device_usbh(&snapper9260_usbh_data);
at91_add_device_udc(&snapper9260_udc_data);
at91_add_device_eth(&snapper9260_macb_data);
at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
ATMEL_SSC_TD | ATMEL_SSC_RD));
snapper9260_add_device_nand();
}
MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = snapper9260_map_io,
.init_irq = snapper9260_init_irq,
.init_machine = snapper9260_board_init,
MACHINE_END

2
arch/arm/mach-at91/include/mach/at91cap9.h
View File

@ -84,7 +84,7 @@
*/
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)

22
arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
View File

@ -15,7 +15,7 @@
#ifndef AT91CAP9_DDRSDR_H
#define AT91CAP9_DDRSDR_H
#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */
#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
#define AT91_DDRSDRC_MODE_NORMAL 0
#define AT91_DDRSDRC_MODE_NOP 1
@ -25,10 +25,10 @@
#define AT91_DDRSDRC_MODE_EXT_LMR 5
#define AT91_DDRSDRC_MODE_DEEP 6
#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */
#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */
#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
@ -49,7 +49,7 @@
#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
@ -59,13 +59,13 @@
#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */
#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_DDRSDRC_LPCB_DISABLE 0
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@ -80,14 +80,14 @@
#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */
#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_DDR 2
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */
#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
@ -98,5 +98,11 @@
#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
/* Register access macros */
#define at91_ramc_read(num, reg) \
at91_sys_read(AT91_DDRSDRC##num + reg)
#define at91_ramc_write(num, reg, value) \
at91_sys_write(AT91_DDRSDRC##num + reg, value)
#endif

2
arch/arm/mach-at91/include/mach/at91sam9260.h
View File

@ -84,7 +84,7 @@
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)

2
arch/arm/mach-at91/include/mach/at91sam9261.h
View File

@ -68,7 +68,7 @@
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)

130
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h Normal file
View File

@ -0,0 +1,130 @@
/*
* Header file for the Atmel DDR/SDR SDRAM Controller
*
* Copyright (C) 2010 Atmel Corporation
* Nicolas Ferre <nicolas.ferre@atmel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9_DDRSDR_H
#define AT91SAM9_DDRSDR_H
#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
#define AT91_DDRSDRC_MODE_NORMAL 0
#define AT91_DDRSDRC_MODE_NOP 1
#define AT91_DDRSDRC_MODE_PRECHARGE 2
#define AT91_DDRSDRC_MODE_LMR 3
#define AT91_DDRSDRC_MODE_REFRESH 4
#define AT91_DDRSDRC_MODE_EXT_LMR 5
#define AT91_DDRSDRC_MODE_DEEP 6
#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
#define AT91_DDRSDRC_NR_11 (0 << 2)
#define AT91_DDRSDRC_NR_12 (1 << 2)
#define AT91_DDRSDRC_NR_13 (2 << 2)
#define AT91_DDRSDRC_NR_14 (3 << 2)
#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
#define AT91_DDRSDRC_CAS_2 (2 << 4)
#define AT91_DDRSDRC_CAS_3 (3 << 4)
#define AT91_DDRSDRC_CAS_25 (6 << 4)
#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_DDRSDRC_LPCB_DISABLE 0
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
#define AT91_DDRSDRC_MD_DDR2 6
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
/* Register access macros */
#define at91_ramc_read(num, reg) \
at91_sys_read(AT91_DDRSDRC##num + reg)
#define at91_ramc_write(num, reg, value) \
at91_sys_write(AT91_DDRSDRC##num + reg, value)
#endif

23
arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
View File

@ -17,7 +17,7 @@
#define AT91SAM9_SDRAMC_H
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
@ -27,10 +27,10 @@
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
@ -57,7 +57,7 @@
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
@ -71,16 +71,21 @@
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
/* Register access macros */
#define at91_ramc_read(num, reg) \
at91_sys_read(AT91_SDRAMC##num + reg)
#define at91_ramc_write(num, reg, value) \
at91_sys_write(AT91_SDRAMC##num + reg, value)
#endif

2
arch/arm/mach-at91/include/mach/at91sam9rl.h
View File

@ -74,7 +74,7 @@
*/
#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)

2
arch/arm/mach-at91/include/mach/board.h
View File

@ -44,6 +44,8 @@
/* USB Device */
struct at91_udc_data {
u8 vbus_pin; /* high == host powering us */
u8 vbus_active_low; /* vbus polarity */
u8 vbus_polled; /* Use polling, not interrupt */
u8 pullup_pin; /* active == D+ pulled up */
u8 pullup_active_low; /* true == pullup_pin is active low */
};

10
arch/arm/mach-at91/include/mach/cpu.h
View File

@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
#define ARCH_EXID_AT91SAM9M11 0x00000001
#define ARCH_EXID_AT91SAM9M10 0x00000002
#define ARCH_EXID_AT91SAM9G46 0x00000003
#define ARCH_EXID_AT91SAM9G45 0x00000004
static inline unsigned long at91_exid_identify(void)
@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void)
#ifdef CONFIG_ARCH_AT91SAM9G45
#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
#else
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
#define cpu_is_at91sam9m10() (0)
#define cpu_is_at91sam9g46() (0)
#define cpu_is_at91sam9m11() (0)
#endif
#ifdef CONFIG_ARCH_AT91CAP9

1
arch/arm/mach-at91/include/mach/gpio.h
View File

@ -19,6 +19,7 @@
#define PIN_BASE NR_AIC_IRQS
#define MAX_GPIO_BANKS 5
#define NR_BUILTIN_GPIO (PIN_BASE + (MAX_GPIO_BANKS * 32))
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */

49
arch/arm/mach-at91/pm.h
View File

@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
{
u32 saved_lpr, lpr;
saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
return saved_lpr;
}
#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
#elif defined(CONFIG_ARCH_AT91SAM9G45)
#include <mach/at91sam9_ddrsdr.h>
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember.
*/
static u32 saved_lpr1;
static inline u32 sdram_selfrefresh_enable(void)
{
/* Those tow values allow us to delay self-refresh activation
* to the maximum. */
u32 lpr0, lpr1;
u32 saved_lpr0;
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
/* self-refresh mode now */
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
return saved_lpr0;
}
#define sdram_selfrefresh_disable(saved_lpr0) \
do { \
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
} while (0)
#else
#include <mach/at91sam9_sdramc.h>
@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
* handle those cases both here and in the Suspend-To-RAM support.
*/
#define AT91_SDRAMC AT91_SDRAMC0
#warning Assuming EB1 SDRAM controller is *NOT* used
#endif
@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
{
u32 saved_lpr, lpr;
saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
return saved_lpr;
}
#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
#endif

74
arch/arm/mach-at91/pm_slowclock.S
View File

@ -16,10 +16,12 @@
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#ifdef CONFIG_ARCH_AT91RM9200
#if defined(CONFIG_ARCH_AT91RM9200)
#include <mach/at91rm9200_mc.h>
#elif defined(CONFIG_ARCH_AT91CAP9)
#include <mach/at91cap9_ddrsdr.h>
#elif defined(CONFIG_ARCH_AT91SAM9G45)
#include <mach/at91sam9_ddrsdr.h>
#else
#include <mach/at91sam9_sdramc.h>
#endif
@ -30,7 +32,6 @@
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
* handle those cases both here and in the Suspend-To-RAM support.
*/
#define AT91_SDRAMC AT91_SDRAMC0
#warning Assuming EB1 SDRAM controller is *NOT* used
#endif
@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
/*
* Register usage:
* R1 = Base address of AT91_PMC
* R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
* R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
* R3 = temporary register
* R4 = temporary register
* R5 = Base address of second RAM Controller or 0 if not present
*/
ldr r1, .at91_va_base_pmc
ldr r2, .at91_va_base_sdramc
ldr r5, .at91_va_base_ramc1
/* Drain write buffer */
mcr p15, 0, r0, c7, c10, 4
@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
/* Put SDRAM in self-refresh mode */
mov r3, #1
str r3, [r2, #AT91_SDRAMC_SRR]
#elif defined(CONFIG_ARCH_AT91CAP9)
/* Enable SDRAM self-refresh mode */
ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
str r3, .saved_sam9_lpr
#elif defined(CONFIG_ARCH_AT91CAP9) \
|| defined(CONFIG_ARCH_AT91SAM9G45)
mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
/* prepare for DDRAM self-refresh mode */
ldr r3, [r2, #AT91_DDRSDRC_LPR]
str r3, .saved_sam9_lpr
bic r3, #AT91_DDRSDRC_LPCB
orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
/* figure out if we use the second ram controller */
cmp r5, #0
ldrne r4, [r5, #AT91_DDRSDRC_LPR]
strne r4, .saved_sam9_lpr1
bicne r4, #AT91_DDRSDRC_LPCB
orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
/* Enable DDRAM self-refresh mode */
str r3, [r2, #AT91_DDRSDRC_LPR]
strne r4, [r5, #AT91_DDRSDRC_LPR]
#else
/* Enable SDRAM self-refresh mode */
ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
ldr r3, [r2, #AT91_SDRAMC_LPR]
str r3, .saved_sam9_lpr
mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
bic r3, #AT91_SDRAMC_LPCB
orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
str r3, [r2, #AT91_SDRAMC_LPR]
#endif
/* Save Master clock setting */
@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
#ifdef CONFIG_ARCH_AT91RM9200
/* Do nothing - self-refresh is automatically disabled. */
#elif defined(CONFIG_ARCH_AT91CAP9)
/* Restore LPR on AT91CAP9 */
#elif defined(CONFIG_ARCH_AT91CAP9) \
|| defined(CONFIG_ARCH_AT91SAM9G45)
/* Restore LPR on AT91 with DDRAM */
ldr r3, .saved_sam9_lpr
str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
str r3, [r2, #AT91_DDRSDRC_LPR]
/* if we use the second ram controller */
cmp r5, #0
ldrne r4, .saved_sam9_lpr1
strne r4, [r5, #AT91_DDRSDRC_LPR]
#else
/* Restore LPR on AT91SAM9 */
/* Restore LPR on AT91 with SDRAM */
ldr r3, .saved_sam9_lpr
str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
str r3, [r2, #AT91_SDRAMC_LPR]
#endif
/* Restore registers, and return */
@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
.saved_sam9_lpr:
.word 0
.saved_sam9_lpr1:
.word 0
.at91_va_base_pmc:
.word AT91_VA_BASE_SYS + AT91_PMC
#ifdef CONFIG_ARCH_AT91RM9200
.at91_va_base_sdramc:
.word AT91_VA_BASE_SYS
#elif defined(CONFIG_ARCH_AT91CAP9)
#elif defined(CONFIG_ARCH_AT91CAP9) \
|| defined(CONFIG_ARCH_AT91SAM9G45)
.at91_va_base_sdramc:
.word AT91_VA_BASE_SYS + AT91_DDRSDRC
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
#else
.at91_va_base_sdramc:
.word AT91_VA_BASE_SYS + AT91_SDRAMC
.word AT91_VA_BASE_SYS + AT91_SDRAMC0
#endif
.at91_va_base_ramc1:
#if defined(CONFIG_ARCH_AT91SAM9G45)
.word AT91_VA_BASE_SYS + AT91_DDRSDRC1
#else
.word 0
#endif
ENTRY(at91_slow_clock_sz)

23
arch/arm/mach-bcmring/core.c
View File

@ -91,14 +91,23 @@ static struct clk uart_clk = {
.parent = &pll1_clk,
};
static struct clk dummy_apb_pclk = {
.name = "BUSCLK",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
};
static struct clk_lookup lookups[] = {
{ /* UART0 */
.dev_id = "uarta",
.clk = &uart_clk,
}, { /* UART1 */
.dev_id = "uartb",
.clk = &uart_clk,
}
{ /* Bus clock */
.con_id = "apb_pclk",
.clk = &dummy_apb_pclk,
}, { /* UART0 */
.dev_id = "uarta",
.clk = &uart_clk,
}, { /* UART1 */
.dev_id = "uartb",
.clk = &uart_clk,
}
};
static struct amba_device *amba_devs[] __initdata = {

1
arch/arm/mach-clps711x/Kconfig
View File

@ -30,7 +30,6 @@ config ARCH_CLEP7312
config ARCH_EDB7211
bool "EDB7211"
select ISA
select ARCH_DISCONTIGMEM_ENABLE
select ARCH_SPARSEMEM_ENABLE
select ARCH_SELECT_MEMORY_MODEL
help

1
arch/arm/mach-clps711x/clep7312.c
View File

@ -32,7 +32,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
mi->nr_banks=1;
mi->bank[0].start = 0xc0000000;
mi->bank[0].size = 0x01000000;
mi->bank[0].node = 0;
}

10
arch/arm/mach-clps711x/edb7211-arch.c
View File

@ -18,6 +18,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/memblock.h>
#include <linux/types.h>
#include <linux/string.h>
@ -29,6 +30,12 @@
extern void edb7211_map_io(void);
/* Reserve screen memory region at the start of main system memory. */
static void __init edb7211_reserve(void)
{
memblock_reserve(PHYS_OFFSET, 0x00020000);
}
static void __init
fixup_edb7211(struct machine_desc *desc, struct tag *tags,
char **cmdline, struct meminfo *mi)
@ -43,10 +50,8 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
*/
mi->bank[0].start = 0xc0000000;
mi->bank[0].size = 8*1024*1024;
mi->bank[0].node = 0;
mi->bank[1].start = 0xc1000000;
mi->bank[1].size = 8*1024*1024;
mi->bank[1].node = 1;
mi->nr_banks = 2;
}
@ -57,6 +62,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
.boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */
.fixup = fixup_edb7211,
.map_io = edb7211_map_io,
.reserve = edb7211_reserve,
.init_irq = clps711x_init_irq,
.timer = &clps711x_timer,
MACHINE_END

1
arch/arm/mach-clps711x/fortunet.c
View File

@ -39,7 +39,6 @@ struct meminfo memmap = {
{
.start = 0xC0000000,
.size = 0x01000000,
.node = 0
},
},
};

2
arch/arm/mach-clps711x/include/mach/memory.h
View File

@ -20,7 +20,6 @@
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
@ -72,7 +71,6 @@
* node 2: 0xd0000000 - 0xd7ffffff
* node 3: 0xd8000000 - 0xdfffffff
*/
#define NODE_MEM_SIZE_BITS 24
#define SECTION_SIZE_BITS 24
#define MAX_PHYSMEM_BITS 32

9
arch/arm/mach-davinci/include/mach/memory.h
View File

@ -48,19 +48,16 @@
* below 128M
*/
static inline void
__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
__arch_adjust_zones(unsigned long *size, unsigned long *holes)
{
unsigned int sz = (128<<20) >> PAGE_SHIFT;
if (node != 0)
sz = 0;
size[1] = size[0] - sz;
size[0] = sz;
}
#define arch_adjust_zones(node, zone_size, holes) \
if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes)
#define arch_adjust_zones(zone_size, holes) \
if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))

24
arch/arm/mach-ep93xx/adssphere.c
View File

@ -13,7 +13,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <mach/hardware.h>
@ -21,26 +20,6 @@
#include <asm/mach/arch.h>
static struct physmap_flash_data adssphere_flash_data = {
.width = 4,
};
static struct resource adssphere_flash_resource = {
.start = EP93XX_CS6_PHYS_BASE,
.end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device adssphere_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &adssphere_flash_data,
},
.num_resources = 1,
.resource = &adssphere_flash_resource,
};
static struct ep93xx_eth_data __initdata adssphere_eth_data = {
.phy_id = 1,
};
@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
static void __init adssphere_init_machine(void)
{
ep93xx_init_devices();
platform_device_register(&adssphere_flash);
ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
ep93xx_register_eth(&adssphere_eth_data, 1);
}

2
arch/arm/mach-ep93xx/clock.c
View File

@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = {
INIT_CK(NULL, "pll1", &clk_pll1),
INIT_CK(NULL, "fclk", &clk_f),
INIT_CK(NULL, "hclk", &clk_h),
INIT_CK(NULL, "pclk", &clk_p),
INIT_CK(NULL, "apb_pclk", &clk_p),
INIT_CK(NULL, "pll2", &clk_pll2),
INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
INIT_CK("ep93xx-keypad", NULL, &clk_keypad),

46
arch/arm/mach-ep93xx/core.c
View File

@ -29,6 +29,7 @@
#include <linux/termios.h>
#include <linux/amba/bus.h>
#include <linux/amba/serial.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
@ -215,8 +216,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
spin_lock_irqsave(&syscon_swlock, flags);
val = __raw_readl(EP93XX_SYSCON_DEVCFG);
val |= set_bits;
val &= ~clear_bits;
val |= set_bits;
__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
__raw_writel(val, EP93XX_SYSCON_DEVCFG);
@ -347,6 +348,43 @@ static struct platform_device ep93xx_ohci_device = {
};
/*************************************************************************
* EP93xx physmap'ed flash
*************************************************************************/
static struct physmap_flash_data ep93xx_flash_data;
static struct resource ep93xx_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device ep93xx_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &ep93xx_flash_data,
},
.num_resources = 1,
.resource = &ep93xx_flash_resource,
};
/**
* ep93xx_register_flash() - Register the external flash device.
* @width: bank width in octets
* @start: resource start address
* @size: resource size
*/
void __init ep93xx_register_flash(unsigned int width,
resource_size_t start, resource_size_t size)
{
ep93xx_flash_data.width = width;
ep93xx_flash_resource.start = start;
ep93xx_flash_resource.end = start + size - 1;
platform_device_register(&ep93xx_flash);
}
/*************************************************************************
* EP93xx ethernet peripheral handling
*************************************************************************/
@ -620,6 +658,11 @@ static struct platform_device ep93xx_fb_device = {
.resource = ep93xx_fb_resource,
};
static struct platform_device ep93xx_bl_device = {
.name = "ep93xx-bl",
.id = -1,
};
/**
* ep93xx_register_fb - Register the framebuffer platform device.
* @data: platform specific framebuffer configuration (__initdata)
@ -628,6 +671,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
{
ep93xxfb_data = *data;
platform_device_register(&ep93xx_fb_device);
platform_device_register(&ep93xx_bl_device);
}

31
arch/arm/mach-ep93xx/edb93xx.c
View File

@ -27,7 +27,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
@ -38,39 +37,13 @@
#include <asm/mach/arch.h>
static struct physmap_flash_data edb93xx_flash_data;
static struct resource edb93xx_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device edb93xx_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &edb93xx_flash_data,
},
.num_resources = 1,
.resource = &edb93xx_flash_resource,
};
static void __init __edb93xx_register_flash(unsigned int width,
resource_size_t start, resource_size_t size)
{
edb93xx_flash_data.width = width;
edb93xx_flash_resource.start = start;
edb93xx_flash_resource.end = start + size - 1;
platform_device_register(&edb93xx_flash);
}
static void __init edb93xx_register_flash(void)
{
if (machine_is_edb9307() || machine_is_edb9312() ||
machine_is_edb9315()) {
__edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
} else {
__edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
}
}

24
arch/arm/mach-ep93xx/gesbc9312.c
View File

@ -13,7 +13,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <mach/hardware.h>
@ -21,26 +20,6 @@
#include <asm/mach/arch.h>
static struct physmap_flash_data gesbc9312_flash_data = {
.width = 4,
};
static struct resource gesbc9312_flash_resource = {
.start = EP93XX_CS6_PHYS_BASE,
.end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device gesbc9312_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &gesbc9312_flash_data,
},
.num_resources = 1,
.resource = &gesbc9312_flash_resource,
};
static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
.phy_id = 1,
};
@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
static void __init gesbc9312_init_machine(void)
{
ep93xx_init_devices();
platform_device_register(&gesbc9312_flash);
ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
ep93xx_register_eth(&gesbc9312_eth_data, 0);
}

3
arch/arm/mach-ep93xx/include/mach/platform.h
View File

@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
unsigned int ep93xx_chip_revision(void);
void ep93xx_register_flash(unsigned int width,
resource_size_t start, resource_size_t size);
void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
struct i2c_board_info *devices, int num);

37
arch/arm/mach-ep93xx/micro9.c
View File

@ -14,7 +14,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <mach/hardware.h>
@ -31,31 +30,6 @@
* Micro9-Lite uses a separate MTD map driver for flash support
* Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
*************************************************************************/
static struct physmap_flash_data micro9_flash_data;
static struct resource micro9_flash_resource = {
.start = EP93XX_CS1_PHYS_BASE,
.end = EP93XX_CS1_PHYS_BASE + SZ_64M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device micro9_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &micro9_flash_data,
},
.num_resources = 1,
.resource = &micro9_flash_resource,
};
static void __init __micro9_register_flash(unsigned int width)
{
micro9_flash_data.width = width;
platform_device_register(&micro9_flash);
}
static unsigned int __init micro9_detect_bootwidth(void)
{
u32 v;
@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void)
static void __init micro9_register_flash(void)
{
unsigned int width;
if (machine_is_micro9())
__micro9_register_flash(4);
width = 4;
else if (machine_is_micro9m() || machine_is_micro9s())
__micro9_register_flash(micro9_detect_bootwidth());
width = micro9_detect_bootwidth();
else
width = 0;
if (width)
ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
}

24
arch/arm/mach-ep93xx/simone.c
View File

@ -18,7 +18,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
@ -29,26 +28,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static struct physmap_flash_data simone_flash_data = {
.width = 2,
};
static struct resource simone_flash_resource = {
.start = EP93XX_CS6_PHYS_BASE,
.end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device simone_flash = {
.name = "physmap-flash",
.id = 0,
.num_resources = 1,
.resource = &simone_flash_resource,
.dev = {
.platform_data = &simone_flash_data,
},
};
static struct ep93xx_eth_data __initdata simone_eth_data = {
.phy_id = 1,
};
@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
static void __init simone_init_machine(void)
{
ep93xx_init_devices();
platform_device_register(&simone_flash);
ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
ep93xx_register_eth(&simone_eth_data, 1);
ep93xx_register_fb(&simone_fb_info);
ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,

27
arch/arm/mach-ep93xx/ts72xx.c
View File

@ -17,7 +17,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/m48t86.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = {
};
/*************************************************************************
* NOR flash (TS-7200 only)
*************************************************************************/
static struct physmap_flash_data ts72xx_nor_data = {
.width = 2,
};
static struct resource ts72xx_nor_resource = {
.start = EP93XX_CS6_PHYS_BASE,
.end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device ts72xx_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev.platform_data = &ts72xx_nor_data,
.resource = &ts72xx_nor_resource,
.num_resources = 1,
};
static void __init ts72xx_register_flash(void)
{
/*
* TS7200 has NOR flash all other TS72xx board have NAND flash.
*/
if (board_is_ts7200()) {
platform_device_register(&ts72xx_nor_flash);
ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
} else {
resource_size_t start;

1
arch/arm/mach-integrator/common.h Normal file
View File

@ -0,0 +1 @@
void integrator_reserve(void);

19
arch/arm/mach-integrator/core.c
View File

@ -14,6 +14,7 @@
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/memblock.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/termios.h>
@ -30,6 +31,7 @@
#include <asm/system.h>
#include <asm/leds.h>
#include <asm/mach/time.h>
#include <asm/pgtable.h>
static struct amba_pl010_data integrator_uart_data;
@ -119,8 +121,13 @@ static struct clk uartclk = {
.rate = 14745600,
};
static struct clk dummy_apb_pclk;
static struct clk_lookup lookups[] = {
{ /* UART0 */
{ /* Bus clock */
.con_id = "apb_pclk",
.clk = &dummy_apb_pclk,
}, { /* UART0 */
.dev_id = "mb:16",
.clk = &uartclk,
}, { /* UART1 */
@ -215,3 +222,13 @@ void cm_control(u32 mask, u32 set)
}
EXPORT_SYMBOL(cm_control);
/*
* We need to stop things allocating the low memory; ideally we need a
* better implementation of GFP_DMA which does not assume that DMA-able
* memory starts at zero.
*/
void __init integrator_reserve(void)
{
memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
}

3
arch/arm/mach-integrator/integrator_ap.c
View File

@ -48,6 +48,8 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include "common.h"
/*
* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
* is the (PA >> 12).
@ -502,6 +504,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
.io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.map_io = ap_map_io,
.reserve = integrator_reserve,
.init_irq = ap_init_irq,
.timer = &ap_timer,
.init_machine = ap_init,

3
arch/arm/mach-integrator/integrator_cp.c
View File

@ -43,6 +43,8 @@
#include <plat/timer-sp.h>
#include "common.h"
#define INTCP_PA_FLASH_BASE 0x24000000
#define INTCP_FLASH_SIZE SZ_32M
@ -601,6 +603,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
.io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.map_io = intcp_map_io,
.reserve = integrator_reserve,
.init_irq = intcp_init_irq,
.timer = &cp_timer,
.init_machine = intcp_init,

2
arch/arm/mach-iop13xx/include/mach/memory.h
View File

@ -69,6 +69,4 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
#endif /* CONFIG_ARCH_IOP13XX */
#endif /* !ASSEMBLY */
#define PFN_TO_NID(addr) (0)
#endif

4
arch/arm/mach-ixp4xx/common-pci.c
View File

@ -348,7 +348,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
* This is really ugly and we need a better way of specifying
* DMA-capable regions of memory.
*/
void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
void __init ixp4xx_adjust_zones(unsigned long *zone_size,
unsigned long *zhole_size)
{
unsigned int sz = SZ_64M >> PAGE_SHIFT;
@ -356,7 +356,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
/*
* Only adjust if > 64M on current system
*/
if (node || (zone_size[0] <= sz))
if (zone_size[0] <= sz)
return;
zone_size[1] = zone_size[0] - sz;

6
arch/arm/mach-ixp4xx/include/mach/memory.h
View File

@ -16,10 +16,10 @@
#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
#define arch_adjust_zones(node, size, holes) \
ixp4xx_adjust_zones(node, size, holes)
#define arch_adjust_zones(size, holes) \
ixp4xx_adjust_zones(size, holes)
#define ISA_DMA_THRESHOLD (SZ_64M - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)

44
arch/arm/mach-lh7a40x/include/mach/memory.h
View File

@ -19,50 +19,6 @@
*/
#define PHYS_OFFSET UL(0xc0000000)
#ifdef CONFIG_DISCONTIGMEM
/*
* Given a kernel address, find the home node of the underlying memory.
*/
# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
# define KVADDR_TO_NID(addr) \
( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\
| ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
# else /* 2 banks per node */
# define KVADDR_TO_NID(addr) \
(((unsigned long) (addr) - PAGE_OFFSET) >> 26)
# endif
/*
* Given a page frame number, convert it to a node id.
*/
# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
# define PFN_TO_NID(pfn) \
(((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\
| ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
# else /* 2 banks per node */
# define PFN_TO_NID(pfn) \
(((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
#endif
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
# define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
# else /* 2 banks per node */
# define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
# endif
#endif
/*
* Sparsemem version of the above
*/

1
arch/arm/mach-msm/board-trout.c
View File

@ -50,7 +50,6 @@ static void __init trout_fixup(struct machine_desc *desc, struct tag *tags,
{
mi->nr_banks = 1;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
mi->bank[0].size = (101*1024*1024);
}

4
arch/arm/mach-nomadik/clock.c
View File

@ -53,6 +53,10 @@ static struct clk clk_default;
}
static struct clk_lookup lookups[] = {
{
.con_id = "apb_pclk",
.clk = &clk_default,
},
CLK(&clk_24, "mtu0"),
CLK(&clk_24, "mtu1"),
CLK(&clk_48, "uart0"),

1
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -301,6 +301,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = ams_delta_map_io,
.reserve = omap_reserve,
.init_irq = ams_delta_init_irq,
.init_machine = ams_delta_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-fsample.c
View File

@ -378,6 +378,7 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_fsample_map_io,
.reserve = omap_reserve,
.init_irq = omap_fsample_init_irq,
.init_machine = omap_fsample_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-generic.c
View File

@ -98,6 +98,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_generic_map_io,
.reserve = omap_reserve,
.init_irq = omap_generic_init_irq,
.init_machine = omap_generic_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-h2.c
View File

@ -467,6 +467,7 @@ MACHINE_START(OMAP_H2, "TI-H2")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = h2_map_io,
.reserve = omap_reserve,
.init_irq = h2_init_irq,
.init_machine = h2_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-h3.c
View File

@ -437,6 +437,7 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = h3_map_io,
.reserve = omap_reserve,
.init_irq = h3_init_irq,
.init_machine = h3_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-htcherald.c
View File

@ -304,6 +304,7 @@ MACHINE_START(HERALD, "HTC Herald")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = htcherald_map_io,
.reserve = omap_reserve,
.init_irq = htcherald_init_irq,
.init_machine = htcherald_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-innovator.c
View File

@ -463,6 +463,7 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = innovator_map_io,
.reserve = omap_reserve,
.init_irq = innovator_init_irq,
.init_machine = innovator_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-nokia770.c
View File

@ -400,6 +400,7 @@ MACHINE_START(NOKIA770, "Nokia 770")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_nokia770_map_io,
.reserve = omap_reserve,
.init_irq = omap_nokia770_init_irq,
.init_machine = omap_nokia770_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-osk.c
View File

@ -584,6 +584,7 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = osk_map_io,
.reserve = omap_reserve,
.init_irq = osk_init_irq,
.init_machine = osk_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-palmte.c
View File

@ -373,6 +373,7 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_palmte_map_io,
.reserve = omap_reserve,
.init_irq = omap_palmte_init_irq,
.init_machine = omap_palmte_init,
.timer = &omap_timer,

1
arch/arm/mach-omap1/board-palmtt.c
View File

@ -321,6 +321,7 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_palmtt_map_io,
.reserve = omap_reserve,
.init_irq = omap_palmtt_init_irq,
.init_machine = omap_palmtt_init,
.timer = &omap_timer,

14
arch/arm/mach-omap1/board-palmz71.c
View File

@ -338,10 +338,12 @@ omap_palmz71_map_io(void)
}
MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
.phys_io = 0xfff00000,
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,.map_io = omap_palmz71_map_io,
.init_irq = omap_palmz71_init_irq,
.init_machine = omap_palmz71_init,
.timer = &omap_timer,
.phys_io = 0xfff00000,
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_palmz71_map_io,
.reserve = omap_reserve,
.init_irq = omap_palmz71_init_irq,
.init_machine = omap_palmz71_init,
.timer = &omap_timer,
MACHINE_END

1
arch/arm/mach-omap1/board-perseus2.c
View File

@ -339,6 +339,7 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_perseus2_map_io,
.reserve = omap_reserve,
.init_irq = omap_perseus2_init_irq,
.init_machine = omap_perseus2_init,
.timer = &omap_timer,

3
arch/arm/mach-omap1/board-sx1.c
View File

@ -423,7 +423,8 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_sx1_map_io,
.init_irq = omap_sx1_init_irq,
.reserve = omap_reserve,
.init_irq = omap_sx1_init_irq,
.init_machine = omap_sx1_init,
.timer = &omap_timer,
MACHINE_END

1
arch/arm/mach-omap1/board-voiceblue.c
View File

@ -287,6 +287,7 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = voiceblue_map_io,
.reserve = omap_reserve,
.init_irq = voiceblue_init_irq,
.init_machine = voiceblue_init,
.timer = &omap_timer,

2
arch/arm/mach-omap1/io.c
View File

@ -22,7 +22,6 @@
extern void omap_check_revision(void);
extern void omap_sram_init(void);
extern void omapfb_reserve_sdram(void);
/*
* The machine specific code may provide the extra mapping besides the
@ -122,7 +121,6 @@ void __init omap1_map_common_io(void)
#endif
omap_sram_init();
omapfb_reserve_sdram();
}
/*

1
arch/arm/mach-omap2/board-2430sdp.c
View File

@ -248,6 +248,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_2430sdp_map_io,
.reserve = omap_reserve,
.init_irq = omap_2430sdp_init_irq,
.init_machine = omap_2430sdp_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-3430sdp.c
View File

@ -815,6 +815,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_3430sdp_map_io,
.reserve = omap_reserve,
.init_irq = omap_3430sdp_init_irq,
.init_machine = omap_3430sdp_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-3630sdp.c
View File

@ -108,6 +108,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_sdp_map_io,
.reserve = omap_reserve,
.init_irq = omap_sdp_init_irq,
.init_machine = omap_sdp_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-4430sdp.c
View File

@ -402,6 +402,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_4430sdp_map_io,
.reserve = omap_reserve,
.init_irq = omap_4430sdp_init_irq,
.init_machine = omap_4430sdp_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-am3517evm.c
View File

@ -472,6 +472,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = am3517_evm_map_io,
.reserve = omap_reserve,
.init_irq = am3517_evm_init_irq,
.init_machine = am3517_evm_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-apollon.c
View File

@ -346,6 +346,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_apollon_map_io,
.reserve = omap_reserve,
.init_irq = omap_apollon_init_irq,
.init_machine = omap_apollon_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-cm-t35.c
View File

@ -837,6 +837,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = cm_t35_map_io,
.reserve = omap_reserve,
.init_irq = cm_t35_init_irq,
.init_machine = cm_t35_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -825,6 +825,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = devkit8000_map_io,
.reserve = omap_reserve,
.init_irq = devkit8000_init_irq,
.init_machine = devkit8000_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-generic.c
View File

@ -59,6 +59,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_generic_map_io,
.reserve = omap_reserve,
.init_irq = omap_generic_init_irq,
.init_machine = omap_generic_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-h4.c
View File

@ -378,6 +378,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_h4_map_io,
.reserve = omap_reserve,
.init_irq = omap_h4_init_irq,
.init_machine = omap_h4_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-igep0020.c
View File

@ -543,6 +543,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = igep2_map_io,
.reserve = omap_reserve,
.init_irq = igep2_init_irq,
.init_machine = igep2_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-ldp.c
View File

@ -417,6 +417,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_ldp_map_io,
.reserve = omap_reserve,
.init_irq = omap_ldp_init_irq,
.init_machine = omap_ldp_init,
.timer = &omap_timer,

3
arch/arm/mach-omap2/board-n8x0.c
View File

@ -667,6 +667,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.reserve = omap_reserve,
.init_irq = n8x0_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
@ -677,6 +678,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.reserve = omap_reserve,
.init_irq = n8x0_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
@ -687,6 +689,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.reserve = omap_reserve,
.init_irq = n8x0_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-omap3beagle.c
View File

@ -519,6 +519,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap3_beagle_map_io,
.reserve = omap_reserve,
.init_irq = omap3_beagle_init_irq,
.init_machine = omap3_beagle_init,
.timer = &omap_timer,

1
arch/arm/mach-omap2/board-omap3evm.c
View File

@ -727,6 +727,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
.io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap3_evm_map_io,
.reserve = omap_reserve,
.init_irq = omap3_evm_init_irq,
.init_machine = omap3_evm_init,
.timer = &omap_timer,

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