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ARM: l2c: tegra: convert to common l2c310 early resume functionality

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Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2014-04-05 11:50:38 +01:00
parent f9040550be
commit b16cee70fd
4 changed files with 4 additions and 46 deletions
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2
arch/arm/mach-tegra/pm.h
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@ -35,8 +35,6 @@ void tegra20_sleep_core_init(void);
void tegra30_lp1_iram_hook(void); void tegra30_lp1_iram_hook(void);
void tegra30_sleep_core_init(void); void tegra30_sleep_core_init(void);
extern unsigned long l2x0_saved_regs_addr;
void tegra_clear_cpu_in_lp2(void); void tegra_clear_cpu_in_lp2(void);
bool tegra_set_cpu_in_lp2(void); bool tegra_set_cpu_in_lp2(void);

11
arch/arm/mach-tegra/reset-handler.S
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@ -19,7 +19,6 @@
#include <asm/cache.h> #include <asm/cache.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/hardware/cache-l2x0.h>
#include "flowctrl.h" #include "flowctrl.h"
#include "fuse.h" #include "fuse.h"
@ -78,8 +77,10 @@ ENTRY(tegra_resume)
str r1, [r0] str r1, [r0]
#endif #endif
#ifdef CONFIG_CACHE_L2X0
/* L2 cache resume & re-enable */ /* L2 cache resume & re-enable */
l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr bl l2c310_early_resume
#endif
end_ca9_scu_l2_resume: end_ca9_scu_l2_resume:
mov32 r9, 0xc0f mov32 r9, 0xc0f
cmp r8, r9 cmp r8, r9
@ -89,12 +90,6 @@ end_ca9_scu_l2_resume:
ENDPROC(tegra_resume) ENDPROC(tegra_resume)
#endif #endif
#ifdef CONFIG_CACHE_L2X0
.globl l2x0_saved_regs_addr
l2x0_saved_regs_addr:
.long 0
#endif
.align L1_CACHE_SHIFT .align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler_start) ENTRY(__tegra_cpu_reset_handler_start)

31
arch/arm/mach-tegra/sleep.h
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@ -120,37 +120,6 @@
mov \tmp1, \tmp1, lsr #8 mov \tmp1, \tmp1, lsr #8
.endm .endm
/* Macro to resume & re-enable L2 cache */
#ifndef L2X0_CTRL_EN
#define L2X0_CTRL_EN 1
#endif
#ifdef CONFIG_CACHE_L2X0
.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
W(adr) \tmp1, \phys_l2x0_saved_regs
ldr \tmp1, [\tmp1]
ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
ldr \tmp3, [\tmp2, #L2X0_CTRL]
tst \tmp3, #L2X0_CTRL_EN
bne exit_l2_resume
ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
str \tmp3, [\tmp2, #L310_TAG_LATENCY_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
str \tmp3, [\tmp2, #L310_DATA_LATENCY_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
str \tmp3, [\tmp2, #L310_PREFETCH_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
str \tmp3, [\tmp2, #L310_POWER_CTRL]
ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
str \tmp3, [\tmp2, #L2X0_AUX_CTRL]
mov \tmp3, #L2X0_CTRL_EN
str \tmp3, [\tmp2, #L2X0_CTRL]
exit_l2_resume:
.endm
#else /* CONFIG_CACHE_L2X0 */
.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
.endm
#endif /* CONFIG_CACHE_L2X0 */
#else #else
void tegra_pen_lock(void); void tegra_pen_lock(void);
void tegra_pen_unlock(void); void tegra_pen_unlock(void);

6
arch/arm/mach-tegra/tegra.c
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@ -73,11 +73,7 @@ u32 tegra_uart_config[3] = {
static void __init tegra_init_cache(void) static void __init tegra_init_cache(void)
{ {
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
int ret; l2x0_of_init(0x3c400001, 0xc20fc3fe);
ret = l2x0_of_init(0x3c400001, 0xc20fc3fe);
if (!ret)
l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
#endif #endif
} }