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ASoC: qcom: Add regmap config support for codec dma driver
Update regmap configuration for supporting headset playback and capture and DMIC capture using codec dma interface Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/1645716828-15305-6-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivasa Rao Mandadapu
Mark Brown
parent
dc8d9766bc
commit
b138706225
@ -28,6 +28,8 @@
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#define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
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#define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
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#define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
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#define LPASS_REG_READ 1
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#define LPASS_REG_WRITE 0
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/*
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* Channel maps for Quad channel playbacks on MI2S Secondary
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@ -798,6 +800,189 @@ static struct regmap_config lpass_hdmi_regmap_config = {
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.cache_type = REGCACHE_FLAT,
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};
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static bool __lpass_rxtx_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
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{
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struct lpass_data *drvdata = dev_get_drvdata(dev);
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struct lpass_variant *v = drvdata->variant;
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int i;
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for (i = 0; i < v->rxtx_irq_ports; ++i) {
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if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
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return true;
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if (reg == LPAIF_RXTX_IRQEN_REG(v, i))
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return true;
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if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
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return true;
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}
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for (i = 0; i < v->rxtx_rdma_channels; ++i) {
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if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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if (rw == LPASS_REG_READ) {
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if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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}
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if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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}
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for (i = 0; i < v->rxtx_wrdma_channels; ++i) {
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if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start,
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LPASS_CDC_DMA_TX3))
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return true;
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if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start,
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LPASS_CDC_DMA_TX3))
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return true;
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if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start,
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LPASS_CDC_DMA_TX3))
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return true;
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if (rw == LPASS_REG_READ) {
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if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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}
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if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start,
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LPASS_CDC_DMA_TX3))
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return true;
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if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start,
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LPASS_CDC_DMA_TX3))
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return true;
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}
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return false;
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}
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static bool lpass_rxtx_regmap_writeable(struct device *dev, unsigned int reg)
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{
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return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_WRITE);
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}
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static bool lpass_rxtx_regmap_readable(struct device *dev, unsigned int reg)
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{
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return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_READ);
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}
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static bool lpass_rxtx_regmap_volatile(struct device *dev, unsigned int reg)
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{
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struct lpass_data *drvdata = dev_get_drvdata(dev);
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struct lpass_variant *v = drvdata->variant;
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int i;
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for (i = 0; i < v->rxtx_irq_ports; ++i) {
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if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
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return true;
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if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
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return true;
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}
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for (i = 0; i < v->rxtx_rdma_channels; ++i)
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if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
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return true;
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for (i = 0; i < v->rxtx_wrdma_channels; ++i)
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if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start,
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LPASS_CDC_DMA_TX3))
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return true;
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return false;
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}
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static bool __lpass_va_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
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{
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struct lpass_data *drvdata = dev_get_drvdata(dev);
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struct lpass_variant *v = drvdata->variant;
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int i;
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for (i = 0; i < v->va_irq_ports; ++i) {
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if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
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return true;
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if (reg == LPAIF_VA_IRQEN_REG(v, i))
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return true;
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if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
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return true;
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}
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for (i = 0; i < v->va_wrdma_channels; ++i) {
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if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start,
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LPASS_CDC_DMA_VA_TX0))
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return true;
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if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start,
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LPASS_CDC_DMA_VA_TX0))
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return true;
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if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start,
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LPASS_CDC_DMA_VA_TX0))
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return true;
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if (rw == LPASS_REG_READ) {
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if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
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LPASS_CDC_DMA_VA_TX0))
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return true;
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}
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if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start,
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LPASS_CDC_DMA_VA_TX0))
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return true;
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if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start,
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LPASS_CDC_DMA_VA_TX0))
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return true;
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}
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return false;
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}
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static bool lpass_va_regmap_writeable(struct device *dev, unsigned int reg)
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{
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return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_WRITE);
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}
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static bool lpass_va_regmap_readable(struct device *dev, unsigned int reg)
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{
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return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_READ);
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}
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static bool lpass_va_regmap_volatile(struct device *dev, unsigned int reg)
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{
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struct lpass_data *drvdata = dev_get_drvdata(dev);
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struct lpass_variant *v = drvdata->variant;
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int i;
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for (i = 0; i < v->va_irq_ports; ++i) {
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if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
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return true;
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if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
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return true;
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}
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for (i = 0; i < v->va_wrdma_channels; ++i) {
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if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
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LPASS_CDC_DMA_VA_TX0))
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return true;
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}
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return false;
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}
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static struct regmap_config lpass_rxtx_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.writeable_reg = lpass_rxtx_regmap_writeable,
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.readable_reg = lpass_rxtx_regmap_readable,
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.volatile_reg = lpass_rxtx_regmap_volatile,
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.cache_type = REGCACHE_FLAT,
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};
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static struct regmap_config lpass_va_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.writeable_reg = lpass_va_regmap_writeable,
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.readable_reg = lpass_va_regmap_readable,
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.volatile_reg = lpass_va_regmap_volatile,
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.cache_type = REGCACHE_FLAT,
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};
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static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
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struct device_node *node,
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const char *name)
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@ -857,6 +1042,8 @@ static void of_lpass_cpu_parse_dai_data(struct device *dev,
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}
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if (id == LPASS_DP_RX) {
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data->hdmi_port_enable = 1;
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} else if (is_cdc_dma_port(id)) {
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data->codec_dma_enable = 1;
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} else {
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data->mi2s_playback_sd_mode[id] =
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of_lpass_cpu_parse_sd_lines(dev, node,
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@ -868,10 +1055,33 @@ static void of_lpass_cpu_parse_dai_data(struct device *dev,
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}
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}
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static int of_lpass_cdc_dma_clks_parse(struct device *dev,
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struct lpass_data *data)
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{
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data->codec_mem0 = devm_clk_get(dev, "audio_cc_codec_mem0");
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if (IS_ERR(data->codec_mem0))
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return PTR_ERR(data->codec_mem0);
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data->codec_mem1 = devm_clk_get(dev, "audio_cc_codec_mem1");
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if (IS_ERR(data->codec_mem1))
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return PTR_ERR(data->codec_mem1);
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data->codec_mem2 = devm_clk_get(dev, "audio_cc_codec_mem2");
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if (IS_ERR(data->codec_mem2))
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return PTR_ERR(data->codec_mem2);
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data->va_mem0 = devm_clk_get(dev, "aon_cc_va_mem0");
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if (IS_ERR(data->va_mem0))
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return PTR_ERR(data->va_mem0);
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return 0;
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}
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int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
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{
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struct lpass_data *drvdata;
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struct device_node *dsp_of_node;
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struct resource *res;
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struct lpass_variant *variant;
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struct device *dev = &pdev->dev;
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const struct of_device_id *match;
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@ -897,6 +1107,47 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
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of_lpass_cpu_parse_dai_data(dev, drvdata);
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if (drvdata->codec_dma_enable) {
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drvdata->rxtx_lpaif =
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devm_platform_ioremap_resource_byname(pdev, "lpass-rxtx-lpaif");
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if (IS_ERR(drvdata->rxtx_lpaif))
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return PTR_ERR(drvdata->rxtx_lpaif);
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drvdata->va_lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-va-lpaif");
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if (IS_ERR(drvdata->va_lpaif))
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return PTR_ERR(drvdata->va_lpaif);
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lpass_rxtx_regmap_config.max_register = LPAIF_CDC_RXTX_WRDMAPER_REG(variant,
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variant->rxtx_wrdma_channels +
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variant->rxtx_wrdma_channel_start, LPASS_CDC_DMA_TX3);
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drvdata->rxtx_lpaif_map = devm_regmap_init_mmio(dev, drvdata->rxtx_lpaif,
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&lpass_rxtx_regmap_config);
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if (IS_ERR(drvdata->rxtx_lpaif_map))
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return PTR_ERR(drvdata->rxtx_lpaif_map);
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lpass_va_regmap_config.max_register = LPAIF_CDC_VA_WRDMAPER_REG(variant,
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variant->va_wrdma_channels +
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variant->va_wrdma_channel_start, LPASS_CDC_DMA_VA_TX0);
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drvdata->va_lpaif_map = devm_regmap_init_mmio(dev, drvdata->va_lpaif,
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&lpass_va_regmap_config);
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if (IS_ERR(drvdata->va_lpaif_map))
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return PTR_ERR(drvdata->va_lpaif_map);
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ret = of_lpass_cdc_dma_clks_parse(dev, drvdata);
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if (ret) {
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dev_err(dev, "failed to get cdc dma clocks %d\n", ret);
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return ret;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-rxtx-cdc-dma-lpm");
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drvdata->rxtx_cdc_dma_lpm_buf = res->start;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-va-cdc-dma-lpm");
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drvdata->va_cdc_dma_lpm_buf = res->start;
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}
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drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif");
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if (IS_ERR(drvdata->lpaif))
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return PTR_ERR(drvdata->lpaif);
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@ -939,7 +1190,7 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
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for (i = 0; i < variant->num_dai; i++) {
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dai_id = variant->dai_driver[i].id;
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if (dai_id == LPASS_DP_RX)
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if (dai_id == LPASS_DP_RX || is_cdc_dma_port(dai_id))
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continue;
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drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
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