powerpc: dts: add power management nodes to FSL chips

Enable Power Management feature on device tree, including MPC8536,
MPC8544, MPC8548, MPC8572, P1010, P1020, P1021, P1022, P2020, P2041,
P3041, T104X, T1024.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20240119203911.3143928-1-Frank.Li@nxp.com
This commit is contained in:
Ran Wang 2024-01-19 15:38:54 -05:00 committed by Michael Ellerman
parent 554da5e0f7
commit b12ba096b8
14 changed files with 83 additions and 12 deletions

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@ -199,6 +199,10 @@
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-etsec1-0.dtsi"
enet0: ethernet@24000 {
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec1-timer-0.dtsi"
usb@22000 {
@ -222,9 +226,10 @@
};
/include/ "pq3-etsec1-2.dtsi"
ethernet@26000 {
enet2: ethernet@26000 {
cell-index = <1>;
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec3_clk>;
};
usb@2b000 {
@ -249,4 +254,9 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
power@e0070 {
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
};
};

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@ -188,4 +188,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

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@ -156,4 +156,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

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@ -193,4 +193,6 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

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@ -183,9 +183,23 @@
/include/ "pq3-etsec2-1.dtsi"
/include/ "pq3-etsec2-2.dtsi"
enet0: ethernet@b0000 {
fsl,pmc-handle = <&etsec1_clk>;
};
enet1: ethernet@b1000 {
fsl,pmc-handle = <&etsec2_clk>;
};
enet2: ethernet@b2000 {
fsl,pmc-handle = <&etsec3_clk>;
};
global-utilities@e0000 {
compatible = "fsl,p1010-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};

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@ -163,14 +163,17 @@
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
fsl,pmc-handle = <&etsec2_clk>;
};
/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {
fsl,pmc-handle = <&etsec3_clk>;
};
global-utilities@e0000 {
@ -178,6 +181,8 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};
/include/ "pq3-etsec2-grp2-0.dtsi"

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@ -159,14 +159,17 @@
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
fsl,pmc-handle = <&etsec2_clk>;
};
/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {
fsl,pmc-handle = <&etsec3_clk>;
};
global-utilities@e0000 {
@ -174,6 +177,8 @@
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
};
&qe {

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@ -225,11 +225,13 @@
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
fsl,wake-on-filer;
fsl,pmc-handle = <&etsec2_clk>;
};
global-utilities@e0000 {
@ -238,9 +240,10 @@
fsl,has-rstcr;
};
/include/ "pq3-power.dtsi"
power@e0070 {
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
reg = <0xe0070 0x20>;
compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc",
"fsl,mpc8548-pmc";
};
};

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@ -178,6 +178,10 @@
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-etsec1-0.dtsi"
enet0: ethernet@24000 {
fsl,pmc-handle = <&etsec1_clk>;
};
/include/ "pq3-etsec1-timer-0.dtsi"
ptp_clock@24e00 {
@ -186,7 +190,15 @@
/include/ "pq3-etsec1-1.dtsi"
enet1: ethernet@25000 {
fsl,pmc-handle = <&etsec2_clk>;
};
/include/ "pq3-etsec1-2.dtsi"
enet2: ethernet@26000 {
fsl,pmc-handle = <&etsec3_clk>;
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
@ -202,8 +214,5 @@
fsl,has-rstcr;
};
pmc: power@e0070 {
compatible = "fsl,mpc8548-pmc";
reg = <0xe0070 0x20>;
};
/include/ "pq3-power.dtsi"
};

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@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright 2024 NXP
*/
power@e0070 {
compatible = "fsl,mpc8548-pmc";
reg = <0xe0070 0x20>;
etsec1_clk: soc-clk@24 {
fsl,pmcdr-mask = <0x00000080>;
};
etsec2_clk: soc-clk@25 {
fsl,pmcdr-mask = <0x00000040>;
};
etsec3_clk: soc-clk@26 {
fsl,pmcdr-mask = <0x00000020>;
};
};

View File

@ -91,7 +91,7 @@
board-control@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,t1024-cpld";
compatible = "fsl,t1024-cpld", "fsl,deepsleep-cpld";
reg = <3 0 0x300>;
ranges = <0 3 0 0x300>;
bank-width = <1>;

View File

@ -104,7 +104,7 @@
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1040rdb-cpld";
compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld";
};
};
};

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@ -68,7 +68,7 @@
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1042rdb-cpld";
compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld";
};
};
};

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@ -41,7 +41,7 @@
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1042rdb_pi-cpld";
compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld";
};
};