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riscv: dts: add clock generator for Sophgo SG2042 SoC

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Add clock generator node to device tree for SG2042, and enable clock for
uart.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
This commit is contained in:
Chen Wang 2023-11-24 14:26:02 +08:00
parent 1613e604df
commit b1240a3951
2 changed files with 66 additions and 1 deletions
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12
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
View File

@ -14,6 +14,18 @@
};
};
&cgi_main {
clock-frequency = <25000000>;
};
&cgi_dpll0 {
clock-frequency = <25000000>;
};
&cgi_dpll1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};

55
arch/riscv/boot/dts/sophgo/sg2042.dtsi
View File

@ -4,8 +4,10 @@
*/
/dts-v1/;
#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include <dt-bindings/clock/sophgo,sg2042-pll.h>
#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sophgo,sg2042-reset.h>
#include "sg2042-cpus.dtsi"
@ -20,12 +22,60 @@
serial0 = &uart0;
};
cgi_main: oscillator0 {
compatible = "fixed-clock";
clock-output-names = "cgi_main";
#clock-cells = <0>;
};
cgi_dpll0: oscillator1 {
compatible = "fixed-clock";
clock-output-names = "cgi_dpll0";
#clock-cells = <0>;
};
cgi_dpll1: oscillator2 {
compatible = "fixed-clock";
clock-output-names = "cgi_dpll1";
#clock-cells = <0>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
pllclk: clock-controller@70300100c0 {
compatible = "sophgo,sg2042-pll";
reg = <0x70 0x300100c0 0x0 0x40>;
clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
#clock-cells = <1>;
};
rpgate: clock-controller@7030010368 {
compatible = "sophgo,sg2042-rpgate";
reg = <0x70 0x30010368 0x0 0x98>;
clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
clock-names = "rpgate";
#clock-cells = <1>;
};
clkgen: clock-controller@7030012000 {
compatible = "sophgo,sg2042-clkgen";
reg = <0x70 0x30012000 0x0 0x1000>;
clocks = <&pllclk MPLL_CLK>,
<&pllclk FPLL_CLK>,
<&pllclk DPLL0_CLK>,
<&pllclk DPLL1_CLK>;
clock-names = "mpll",
"fpll",
"dpll0",
"dpll1";
#clock-cells = <1>;
};
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
@ -341,6 +391,9 @@
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clkgen GATE_CLK_UART_500M>,
<&clkgen GATE_CLK_APB_UART>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rstgen RST_UART0>;