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net: ethernet: rtsn: Add support for Renesas Ethernet-TSN
Add initial support for Renesas Ethernet-TSN End-station device of R-Car V4H. The Ethernet End-station can connect to an Ethernet network using a 10 Mbps, 100 Mbps, or 1 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY. The driver supports Rx checksum and offload and hardware timestamps. While full power management and suspend/resume is not yet supported the driver enables runtime PM in order to enable the module clock. While explicit clock management using clk_enable() would suffice for the supported SoC, the module could be reused on SoCs where the module is part of a power domain. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Niklas Söderlund
David S. Miller
parent
d7527fe98d
commit
b0d3969d2b
@ -19032,6 +19032,14 @@ F: drivers/net/ethernet/renesas/Makefile
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F: drivers/net/ethernet/renesas/rcar_gen4*
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F: drivers/net/ethernet/renesas/rswitch*
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RENESAS ETHERNET TSN DRIVER
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M: Niklas Söderlund <niklas.soderlund@ragnatech.se>
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L: netdev@vger.kernel.org
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L: linux-renesas-soc@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/net/renesas,ethertsn.yaml
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F: drivers/net/ethernet/renesas/rtsn.*
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RENESAS IDT821034 ASoC CODEC
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M: Herve Codina <herve.codina@bootlin.com>
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L: alsa-devel@alsa-project.org (moderated for non-subscribers)
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@ -59,4 +59,14 @@ config RENESAS_GEN4_PTP
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help
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Renesas R-Car Gen4 gPTP device driver.
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config RTSN
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tristate "Renesas Ethernet-TSN support"
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depends on ARCH_RENESAS || COMPILE_TEST
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depends on PTP_1588_CLOCK
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select CRC32
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select PHYLIB
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select RENESAS_GEN4_PTP
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help
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Renesas Ethernet-TSN device driver.
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endif # NET_VENDOR_RENESAS
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@ -11,3 +11,5 @@ obj-$(CONFIG_RAVB) += ravb.o
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obj-$(CONFIG_RENESAS_ETHER_SWITCH) += rswitch.o
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obj-$(CONFIG_RENESAS_GEN4_PTP) += rcar_gen4_ptp.o
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obj-$(CONFIG_RTSN) += rtsn.o
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1391
drivers/net/ethernet/renesas/rtsn.c
Normal file
1391
drivers/net/ethernet/renesas/rtsn.c
Normal file
File diff suppressed because it is too large
Load Diff
464
drivers/net/ethernet/renesas/rtsn.h
Normal file
464
drivers/net/ethernet/renesas/rtsn.h
Normal file
@ -0,0 +1,464 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Renesas Ethernet-TSN device driver
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*
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* Copyright (C) 2022 Renesas Electronics Corporation
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* Copyright (C) 2023 Niklas Söderlund <niklas.soderlund@ragnatech.se>
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*/
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#ifndef __RTSN_H__
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#define __RTSN_H__
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#include <linux/types.h>
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#define AXIBMI 0x0000
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#define TSNMHD 0x1000
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#define RMSO 0x2000
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#define RMRO 0x3800
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enum rtsn_reg {
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AXIWC = AXIBMI + 0x0000,
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AXIRC = AXIBMI + 0x0004,
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TDPC0 = AXIBMI + 0x0010,
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TFT = AXIBMI + 0x0090,
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TATLS0 = AXIBMI + 0x00a0,
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TATLS1 = AXIBMI + 0x00a4,
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TATLR = AXIBMI + 0x00a8,
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RATLS0 = AXIBMI + 0x00b0,
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RATLS1 = AXIBMI + 0x00b4,
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RATLR = AXIBMI + 0x00b8,
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TSA0 = AXIBMI + 0x00c0,
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TSS0 = AXIBMI + 0x00c4,
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TRCR0 = AXIBMI + 0x0140,
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RIDAUAS0 = AXIBMI + 0x0180,
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RR = AXIBMI + 0x0200,
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TATS = AXIBMI + 0x0210,
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TATSR0 = AXIBMI + 0x0214,
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TATSR1 = AXIBMI + 0x0218,
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TATSR2 = AXIBMI + 0x021c,
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RATS = AXIBMI + 0x0220,
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RATSR0 = AXIBMI + 0x0224,
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RATSR1 = AXIBMI + 0x0228,
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RATSR2 = AXIBMI + 0x022c,
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RIDASM0 = AXIBMI + 0x0240,
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RIDASAM0 = AXIBMI + 0x0244,
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RIDACAM0 = AXIBMI + 0x0248,
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EIS0 = AXIBMI + 0x0300,
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EIE0 = AXIBMI + 0x0304,
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EID0 = AXIBMI + 0x0308,
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EIS1 = AXIBMI + 0x0310,
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EIE1 = AXIBMI + 0x0314,
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EID1 = AXIBMI + 0x0318,
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TCEIS0 = AXIBMI + 0x0340,
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TCEIE0 = AXIBMI + 0x0344,
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TCEID0 = AXIBMI + 0x0348,
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RFSEIS0 = AXIBMI + 0x04c0,
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RFSEIE0 = AXIBMI + 0x04c4,
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RFSEID0 = AXIBMI + 0x04c8,
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RFEIS0 = AXIBMI + 0x0540,
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RFEIE0 = AXIBMI + 0x0544,
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RFEID0 = AXIBMI + 0x0548,
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RCEIS0 = AXIBMI + 0x05c0,
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RCEIE0 = AXIBMI + 0x05c4,
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RCEID0 = AXIBMI + 0x05c8,
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RIDAOIS = AXIBMI + 0x0640,
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RIDAOIE = AXIBMI + 0x0644,
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RIDAOID = AXIBMI + 0x0648,
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TSFEIS = AXIBMI + 0x06c0,
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TSFEIE = AXIBMI + 0x06c4,
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TSFEID = AXIBMI + 0x06c8,
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TSCEIS = AXIBMI + 0x06d0,
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TSCEIE = AXIBMI + 0x06d4,
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TSCEID = AXIBMI + 0x06d8,
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DIS = AXIBMI + 0x0b00,
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DIE = AXIBMI + 0x0b04,
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DID = AXIBMI + 0x0b08,
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TDIS0 = AXIBMI + 0x0b10,
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TDIE0 = AXIBMI + 0x0b14,
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TDID0 = AXIBMI + 0x0b18,
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RDIS0 = AXIBMI + 0x0b90,
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RDIE0 = AXIBMI + 0x0b94,
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RDID0 = AXIBMI + 0x0b98,
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TSDIS = AXIBMI + 0x0c10,
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TSDIE = AXIBMI + 0x0c14,
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TSDID = AXIBMI + 0x0c18,
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GPOUT = AXIBMI + 0x6000,
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OCR = TSNMHD + 0x0000,
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OSR = TSNMHD + 0x0004,
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SWR = TSNMHD + 0x0008,
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SIS = TSNMHD + 0x000c,
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GIS = TSNMHD + 0x0010,
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GIE = TSNMHD + 0x0014,
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GID = TSNMHD + 0x0018,
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TIS1 = TSNMHD + 0x0020,
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TIE1 = TSNMHD + 0x0024,
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TID1 = TSNMHD + 0x0028,
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TIS2 = TSNMHD + 0x0030,
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TIE2 = TSNMHD + 0x0034,
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TID2 = TSNMHD + 0x0038,
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RIS = TSNMHD + 0x0040,
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RIE = TSNMHD + 0x0044,
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RID = TSNMHD + 0x0048,
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TGC1 = TSNMHD + 0x0050,
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TGC2 = TSNMHD + 0x0054,
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TFS0 = TSNMHD + 0x0060,
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TCF0 = TSNMHD + 0x0070,
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TCR1 = TSNMHD + 0x0080,
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TCR2 = TSNMHD + 0x0084,
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TCR3 = TSNMHD + 0x0088,
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TCR4 = TSNMHD + 0x008c,
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TMS0 = TSNMHD + 0x0090,
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TSR1 = TSNMHD + 0x00b0,
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TSR2 = TSNMHD + 0x00b4,
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TSR3 = TSNMHD + 0x00b8,
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TSR4 = TSNMHD + 0x00bc,
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TSR5 = TSNMHD + 0x00c0,
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RGC = TSNMHD + 0x00d0,
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RDFCR = TSNMHD + 0x00d4,
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RCFCR = TSNMHD + 0x00d8,
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REFCNCR = TSNMHD + 0x00dc,
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RSR1 = TSNMHD + 0x00e0,
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RSR2 = TSNMHD + 0x00e4,
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RSR3 = TSNMHD + 0x00e8,
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TCIS = TSNMHD + 0x01e0,
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TCIE = TSNMHD + 0x01e4,
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TCID = TSNMHD + 0x01e8,
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TPTPC = TSNMHD + 0x01f0,
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TTML = TSNMHD + 0x01f4,
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TTJ = TSNMHD + 0x01f8,
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TCC = TSNMHD + 0x0200,
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TCS = TSNMHD + 0x0204,
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TGS = TSNMHD + 0x020c,
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TACST0 = TSNMHD + 0x0210,
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TACST1 = TSNMHD + 0x0214,
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TACST2 = TSNMHD + 0x0218,
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TALIT0 = TSNMHD + 0x0220,
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TALIT1 = TSNMHD + 0x0224,
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TALIT2 = TSNMHD + 0x0228,
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TAEN0 = TSNMHD + 0x0230,
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TAEN1 = TSNMHD + 0x0234,
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TASFE = TSNMHD + 0x0240,
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TACLL0 = TSNMHD + 0x0250,
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TACLL1 = TSNMHD + 0x0254,
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TACLL2 = TSNMHD + 0x0258,
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CACC = TSNMHD + 0x0260,
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CCS = TSNMHD + 0x0264,
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CAIV0 = TSNMHD + 0x0270,
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CAUL0 = TSNMHD + 0x0290,
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TOCST0 = TSNMHD + 0x0300,
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TOCST1 = TSNMHD + 0x0304,
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TOCST2 = TSNMHD + 0x0308,
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TOLIT0 = TSNMHD + 0x0310,
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TOLIT1 = TSNMHD + 0x0314,
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TOLIT2 = TSNMHD + 0x0318,
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TOEN0 = TSNMHD + 0x0320,
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TOEN1 = TSNMHD + 0x0324,
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TOSFE = TSNMHD + 0x0330,
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TCLR0 = TSNMHD + 0x0340,
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TCLR1 = TSNMHD + 0x0344,
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TCLR2 = TSNMHD + 0x0348,
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TSMS = TSNMHD + 0x0350,
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COCC = TSNMHD + 0x0360,
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COIV0 = TSNMHD + 0x03b0,
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COUL0 = TSNMHD + 0x03d0,
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QSTMACU0 = TSNMHD + 0x0400,
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QSTMACD0 = TSNMHD + 0x0404,
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QSTMAMU0 = TSNMHD + 0x0408,
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QSTMAMD0 = TSNMHD + 0x040c,
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QSFTVL0 = TSNMHD + 0x0410,
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QSFTVLM0 = TSNMHD + 0x0414,
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QSFTMSD0 = TSNMHD + 0x0418,
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QSFTGMI0 = TSNMHD + 0x041c,
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QSFTLS = TSNMHD + 0x0600,
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QSFTLIS = TSNMHD + 0x0604,
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QSFTLIE = TSNMHD + 0x0608,
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QSFTLID = TSNMHD + 0x060c,
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QSMSMC = TSNMHD + 0x0610,
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QSGTMC = TSNMHD + 0x0614,
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QSEIS = TSNMHD + 0x0618,
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QSEIE = TSNMHD + 0x061c,
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QSEID = TSNMHD + 0x0620,
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QGACST0 = TSNMHD + 0x0630,
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QGACST1 = TSNMHD + 0x0634,
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QGACST2 = TSNMHD + 0x0638,
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QGALIT1 = TSNMHD + 0x0640,
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QGALIT2 = TSNMHD + 0x0644,
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QGAEN0 = TSNMHD + 0x0648,
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QGAEN1 = TSNMHD + 0x074c,
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QGIGS = TSNMHD + 0x0650,
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QGGC = TSNMHD + 0x0654,
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QGATL0 = TSNMHD + 0x0664,
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QGATL1 = TSNMHD + 0x0668,
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QGATL2 = TSNMHD + 0x066c,
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QGOCST0 = TSNMHD + 0x0670,
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QGOCST1 = TSNMHD + 0x0674,
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QGOCST2 = TSNMHD + 0x0678,
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QGOLIT0 = TSNMHD + 0x067c,
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QGOLIT1 = TSNMHD + 0x0680,
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QGOLIT2 = TSNMHD + 0x0684,
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QGOEN0 = TSNMHD + 0x0688,
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QGOEN1 = TSNMHD + 0x068c,
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QGTRO = TSNMHD + 0x0690,
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QGTR1 = TSNMHD + 0x0694,
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QGTR2 = TSNMHD + 0x0698,
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QGFSMS = TSNMHD + 0x069c,
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QTMIS = TSNMHD + 0x06e0,
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QTMIE = TSNMHD + 0x06e4,
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QTMID = TSNMHD + 0x06e8,
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QMEC = TSNMHD + 0x0700,
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QMMC = TSNMHD + 0x0704,
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QRFDC = TSNMHD + 0x0708,
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QYFDC = TSNMHD + 0x070c,
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QVTCMC0 = TSNMHD + 0x0710,
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QMCBSC0 = TSNMHD + 0x0750,
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QMCIRC0 = TSNMHD + 0x0790,
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QMEBSC0 = TSNMHD + 0x07d0,
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QMEIRC0 = TSNMHD + 0x0710,
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QMCFC = TSNMHD + 0x0850,
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QMEIS = TSNMHD + 0x0860,
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QMEIE = TSNMHD + 0x0864,
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QMEID = TSNMHD + 0x086c,
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QSMFC0 = TSNMHD + 0x0870,
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QMSPPC0 = TSNMHD + 0x08b0,
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QMSRPC0 = TSNMHD + 0x08f0,
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QGPPC0 = TSNMHD + 0x0930,
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QGRPC0 = TSNMHD + 0x0950,
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QMDPC0 = TSNMHD + 0x0970,
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QMGPC0 = TSNMHD + 0x09b0,
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QMYPC0 = TSNMHD + 0x09f0,
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QMRPC0 = TSNMHD + 0x0a30,
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MQSTMACU = TSNMHD + 0x0a70,
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MQSTMACD = TSNMHD + 0x0a74,
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MQSTMAMU = TSNMHD + 0x0a78,
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MQSTMAMD = TSNMHD + 0x0a7c,
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MQSFTVL = TSNMHD + 0x0a80,
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MQSFTVLM = TSNMHD + 0x0a84,
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MQSFTMSD = TSNMHD + 0x0a88,
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MQSFTGMI = TSNMHD + 0x0a8c,
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CFCR0 = RMSO + 0x0800,
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FMSCR = RMSO + 0x0c10,
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MMC = RMRO + 0x0000,
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MPSM = RMRO + 0x0010,
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MPIC = RMRO + 0x0014,
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MTFFC = RMRO + 0x0020,
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MTPFC = RMRO + 0x0024,
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MTATC0 = RMRO + 0x0040,
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MRGC = RMRO + 0x0080,
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MRMAC0 = RMRO + 0x0084,
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MRMAC1 = RMRO + 0x0088,
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MRAFC = RMRO + 0x008c,
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MRSCE = RMRO + 0x0090,
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MRSCP = RMRO + 0x0094,
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MRSCC = RMRO + 0x0098,
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MRFSCE = RMRO + 0x009c,
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MRFSCP = RMRO + 0x00a0,
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MTRC = RMRO + 0x00a4,
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MPFC = RMRO + 0x0100,
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MLVC = RMRO + 0x0340,
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MEEEC = RMRO + 0x0350,
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MLBC = RMRO + 0x0360,
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MGMR = RMRO + 0x0400,
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MMPFTCT = RMRO + 0x0410,
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MAPFTCT = RMRO + 0x0414,
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MPFRCT = RMRO + 0x0418,
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MFCICT = RMRO + 0x041c,
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MEEECT = RMRO + 0x0420,
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MEIS = RMRO + 0x0500,
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MEIE = RMRO + 0x0504,
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MEID = RMRO + 0x0508,
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MMIS0 = RMRO + 0x0510,
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MMIE0 = RMRO + 0x0514,
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MMID0 = RMRO + 0x0518,
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MMIS1 = RMRO + 0x0520,
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MMIE1 = RMRO + 0x0524,
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MMID1 = RMRO + 0x0528,
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MMIS2 = RMRO + 0x0530,
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MMIE2 = RMRO + 0x0534,
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MMID2 = RMRO + 0x0538,
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MXMS = RMRO + 0x0600,
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};
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/* AXIBMI */
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#define RR_RATRR BIT(0)
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#define RR_TATRR BIT(1)
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#define RR_RST (RR_RATRR | RR_TATRR)
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#define RR_RST_COMPLETE 0x03
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#define AXIWC_DEFAULT 0xffff
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#define AXIRC_DEFAULT 0xffff
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#define TATLS0_TEDE BIT(1)
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#define TATLS0_TATEN_SHIFT 24
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#define TATLS0_TATEN(n) ((n) << TATLS0_TATEN_SHIFT)
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#define TATLR_TATL BIT(31)
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#define RATLS0_RETS BIT(2)
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#define RATLS0_REDE BIT(3)
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#define RATLS0_RATEN_SHIFT 24
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#define RATLS0_RATEN(n) ((n) << RATLS0_RATEN_SHIFT)
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#define RATLR_RATL BIT(31)
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#define DIE_DID_TDICX(n) BIT((n))
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#define DIE_DID_RDICX(n) BIT((n) + 8)
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#define TDIE_TDID_TDX(n) BIT(n)
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#define RDIE_RDID_RDX(n) BIT(n)
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#define TDIS_TDS(n) BIT(n)
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#define RDIS_RDS(n) BIT(n)
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/* MHD */
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#define OSR_OPS 0x07
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#define SWR_SWR BIT(0)
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#define TGC1_TQTM_SFM 0xff00
|
||||
#define TGC1_STTV_DEFAULT 0x03
|
||||
|
||||
#define TMS_MFS_MAX 0x2800
|
||||
|
||||
/* RMAC System */
|
||||
#define CFCR_SDID(n) ((n) << 16)
|
||||
#define FMSCR_FMSIE(n) ((n) << 0)
|
||||
|
||||
/* RMAC */
|
||||
#define MPIC_PIS_MASK GENMASK(1, 0)
|
||||
#define MPIC_PIS_MII 0
|
||||
#define MPIC_PIS_RMII 0x01
|
||||
#define MPIC_PIS_GMII 0x02
|
||||
#define MPIC_PIS_RGMII 0x03
|
||||
#define MPIC_LSC_SHIFT 2
|
||||
#define MPIC_LSC_MASK GENMASK(3, MPIC_LSC_SHIFT)
|
||||
#define MPIC_LSC_10M (0 << MPIC_LSC_SHIFT)
|
||||
#define MPIC_LSC_100M (0x01 << MPIC_LSC_SHIFT)
|
||||
#define MPIC_LSC_1G (0x02 << MPIC_LSC_SHIFT)
|
||||
#define MPIC_PSMCS_SHIFT 16
|
||||
#define MPIC_PSMCS_MASK GENMASK(21, MPIC_PSMCS_SHIFT)
|
||||
#define MPIC_PSMCS_DEFAULT (0x0a << MPIC_PSMCS_SHIFT)
|
||||
#define MPIC_PSMHT_SHIFT 24
|
||||
#define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT)
|
||||
#define MPIC_PSMHT_DEFAULT (0x07 << MPIC_PSMHT_SHIFT)
|
||||
|
||||
#define MLVC_PASE BIT(8)
|
||||
#define MLVC_PSE BIT(16)
|
||||
#define MLVC_PLV BIT(17)
|
||||
|
||||
#define MPSM_PSME BIT(0)
|
||||
#define MPSM_PSMAD BIT(1)
|
||||
#define MPSM_PDA_SHIFT 3
|
||||
#define MPSM_PDA_MASK GENMASK(7, 3)
|
||||
#define MPSM_PDA(n) (((n) << MPSM_PDA_SHIFT) & MPSM_PDA_MASK)
|
||||
#define MPSM_PRA_SHIFT 8
|
||||
#define MPSM_PRA_MASK GENMASK(12, 8)
|
||||
#define MPSM_PRA(n) (((n) << MPSM_PRA_SHIFT) & MPSM_PRA_MASK)
|
||||
#define MPSM_PRD_SHIFT 16
|
||||
#define MPSM_PRD_SET(n) ((n) << MPSM_PRD_SHIFT)
|
||||
#define MPSM_PRD_GET(n) ((n) >> MPSM_PRD_SHIFT)
|
||||
|
||||
#define GPOUT_RDM BIT(13)
|
||||
#define GPOUT_TDM BIT(14)
|
||||
|
||||
/* RTSN */
|
||||
#define RTSN_INTERVAL_US 1000
|
||||
#define RTSN_TIMEOUT_US 1000000
|
||||
|
||||
#define TX_NUM_CHAINS 1
|
||||
#define RX_NUM_CHAINS 1
|
||||
|
||||
#define TX_CHAIN_SIZE 1024
|
||||
#define RX_CHAIN_SIZE 1024
|
||||
|
||||
#define TX_CHAIN_IDX 0
|
||||
#define RX_CHAIN_IDX 0
|
||||
|
||||
#define TX_CHAIN_ADDR_OFFSET (sizeof(struct rtsn_desc) * TX_CHAIN_IDX)
|
||||
#define RX_CHAIN_ADDR_OFFSET (sizeof(struct rtsn_desc) * RX_CHAIN_IDX)
|
||||
|
||||
#define PKT_BUF_SZ 1584
|
||||
#define RTSN_ALIGN 128
|
||||
|
||||
enum rtsn_mode {
|
||||
OCR_OPC_DISABLE,
|
||||
OCR_OPC_CONFIG,
|
||||
OCR_OPC_OPERATION,
|
||||
};
|
||||
|
||||
/* Descriptors */
|
||||
enum RX_DS_CC_BIT {
|
||||
RX_DS = 0x0fff, /* Data size */
|
||||
RX_TR = 0x1000, /* Truncation indication */
|
||||
RX_EI = 0x2000, /* Error indication */
|
||||
RX_PS = 0xc000, /* Padding selection */
|
||||
};
|
||||
|
||||
enum TX_FS_TAGL_BIT {
|
||||
TX_DS = 0x0fff, /* Data size */
|
||||
TX_TAGL = 0xf000, /* Frame tag LSBs */
|
||||
};
|
||||
|
||||
enum DIE_DT {
|
||||
/* HW/SW arbitration */
|
||||
DT_FEMPTY_IS = 0x10,
|
||||
DT_FEMPTY_IC = 0x20,
|
||||
DT_FEMPTY_ND = 0x30,
|
||||
DT_FEMPTY = 0x40,
|
||||
DT_FEMPTY_START = 0x50,
|
||||
DT_FEMPTY_MID = 0x60,
|
||||
DT_FEMPTY_END = 0x70,
|
||||
|
||||
/* Frame data */
|
||||
DT_FSINGLE = 0x80,
|
||||
DT_FSTART = 0x90,
|
||||
DT_FMID = 0xa0,
|
||||
DT_FEND = 0xb0,
|
||||
|
||||
/* Chain control */
|
||||
DT_LEMPTY = 0xc0,
|
||||
DT_EEMPTY = 0xd0,
|
||||
DT_LINK = 0xe0,
|
||||
DT_EOS = 0xf0,
|
||||
|
||||
DT_MASK = 0xf0,
|
||||
D_DIE = 0x08,
|
||||
};
|
||||
|
||||
struct rtsn_desc {
|
||||
__le16 info_ds;
|
||||
__u8 info;
|
||||
u8 die_dt;
|
||||
__le32 dptr;
|
||||
} __packed;
|
||||
|
||||
struct rtsn_ts_desc {
|
||||
__le16 info_ds;
|
||||
__u8 info;
|
||||
u8 die_dt;
|
||||
__le32 dptr;
|
||||
__le32 ts_nsec;
|
||||
__le32 ts_sec;
|
||||
} __packed;
|
||||
|
||||
struct rtsn_ext_desc {
|
||||
__le16 info_ds;
|
||||
__u8 info;
|
||||
u8 die_dt;
|
||||
__le32 dptr;
|
||||
__le64 info1;
|
||||
} __packed;
|
||||
|
||||
struct rtsn_ext_ts_desc {
|
||||
__le16 info_ds;
|
||||
__u8 info;
|
||||
u8 die_dt;
|
||||
__le32 dptr;
|
||||
__le64 info1;
|
||||
__le32 ts_nsec;
|
||||
__le32 ts_sec;
|
||||
} __packed;
|
||||
|
||||
enum EXT_INFO_DS_BIT {
|
||||
TXC = 0x4000,
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user