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phy: nxp-c45: add driver for tja1103
Add driver for tja1103 driver and for future NXP C45 PHYs. Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Radu Pirea (NXP OSS)
David S. Miller
parent
da702f34e3
commit
b050f2f15e
@ -12840,6 +12840,12 @@ F: drivers/nvmem/
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F: include/linux/nvmem-consumer.h
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F: include/linux/nvmem-provider.h
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NXP C45 TJA11XX PHY DRIVER
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M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
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L: netdev@vger.kernel.org
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S: Maintained
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F: drivers/net/phy/nxp-c45-tja11xx.c
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NXP FSPI DRIVER
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M: Ashish Kumar <ashish.kumar@nxp.com>
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R: Yogesh Gaur <yogeshgaur.83@gmail.com>
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@ -234,6 +234,12 @@ config NATIONAL_PHY
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help
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Currently supports the DP83865 PHY.
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config NXP_C45_TJA11XX_PHY
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tristate "NXP C45 TJA11XX PHYs"
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help
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Enable support for NXP C45 TJA11XX PHYs.
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Currently supports only the TJA1103 PHY.
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config NXP_TJA11XX_PHY
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tristate "NXP TJA11xx PHYs support"
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depends on HWMON
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@ -71,6 +71,7 @@ obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
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obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o
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obj-$(CONFIG_MICROSEMI_PHY) += mscc/
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obj-$(CONFIG_NATIONAL_PHY) += national.o
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obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o
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obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
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obj-$(CONFIG_QSEMI_PHY) += qsemi.o
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obj-$(CONFIG_REALTEK_PHY) += realtek.o
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588
drivers/net/phy/nxp-c45-tja11xx.c
Normal file
588
drivers/net/phy/nxp-c45-tja11xx.c
Normal file
@ -0,0 +1,588 @@
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// SPDX-License-Identifier: GPL-2.0
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/* NXP C45 PHY driver
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* Copyright (C) 2021 NXP
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* Author: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
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*/
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#include <linux/delay.h>
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#include <linux/ethtool.h>
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#include <linux/ethtool_netlink.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/processor.h>
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#include <linux/property.h>
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#define PHY_ID_TJA_1103 0x001BB010
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#define PMAPMD_B100T1_PMAPMD_CTL 0x0834
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#define B100T1_PMAPMD_CONFIG_EN BIT(15)
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#define B100T1_PMAPMD_MASTER BIT(14)
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#define MASTER_MODE (B100T1_PMAPMD_CONFIG_EN | \
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B100T1_PMAPMD_MASTER)
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#define SLAVE_MODE (B100T1_PMAPMD_CONFIG_EN)
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#define VEND1_DEVICE_CONTROL 0x0040
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#define DEVICE_CONTROL_RESET BIT(15)
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#define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14)
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#define DEVICE_CONTROL_CONFIG_ALL_EN BIT(13)
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#define VEND1_PHY_CONTROL 0x8100
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#define PHY_CONFIG_EN BIT(14)
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#define PHY_START_OP BIT(0)
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#define VEND1_PHY_CONFIG 0x8108
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#define PHY_CONFIG_AUTO BIT(0)
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#define VEND1_SIGNAL_QUALITY 0x8320
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#define SQI_VALID BIT(14)
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#define SQI_MASK GENMASK(2, 0)
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#define MAX_SQI SQI_MASK
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#define VEND1_CABLE_TEST 0x8330
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#define CABLE_TEST_ENABLE BIT(15)
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#define CABLE_TEST_START BIT(14)
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#define CABLE_TEST_VALID BIT(13)
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#define CABLE_TEST_OK 0x00
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#define CABLE_TEST_SHORTED 0x01
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#define CABLE_TEST_OPEN 0x02
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#define CABLE_TEST_UNKNOWN 0x07
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#define VEND1_PORT_CONTROL 0x8040
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#define PORT_CONTROL_EN BIT(14)
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#define VEND1_PORT_INFRA_CONTROL 0xAC00
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#define PORT_INFRA_CONTROL_EN BIT(14)
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#define VEND1_RXID 0xAFCC
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#define VEND1_TXID 0xAFCD
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#define ID_ENABLE BIT(15)
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#define VEND1_ABILITIES 0xAFC4
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#define RGMII_ID_ABILITY BIT(15)
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#define RGMII_ABILITY BIT(14)
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#define RMII_ABILITY BIT(10)
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#define REVMII_ABILITY BIT(9)
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#define MII_ABILITY BIT(8)
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#define SGMII_ABILITY BIT(0)
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#define VEND1_MII_BASIC_CONFIG 0xAFC6
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#define MII_BASIC_CONFIG_REV BIT(8)
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#define MII_BASIC_CONFIG_SGMII 0x9
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#define MII_BASIC_CONFIG_RGMII 0x7
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#define MII_BASIC_CONFIG_RMII 0x5
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#define MII_BASIC_CONFIG_MII 0x4
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#define VEND1_SYMBOL_ERROR_COUNTER 0x8350
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#define VEND1_LINK_DROP_COUNTER 0x8352
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#define VEND1_LINK_LOSSES_AND_FAILURES 0x8353
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#define VEND1_R_GOOD_FRAME_CNT 0xA950
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#define VEND1_R_BAD_FRAME_CNT 0xA952
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#define VEND1_R_RXER_FRAME_CNT 0xA954
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#define VEND1_RX_PREAMBLE_COUNT 0xAFCE
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#define VEND1_TX_PREAMBLE_COUNT 0xAFCF
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#define VEND1_RX_IPG_LENGTH 0xAFD0
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#define VEND1_TX_IPG_LENGTH 0xAFD1
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#define COUNTER_EN BIT(15)
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#define RGMII_PERIOD_PS 8000U
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#define PS_PER_DEGREE div_u64(RGMII_PERIOD_PS, 360)
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#define MIN_ID_PS 1644U
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#define MAX_ID_PS 2260U
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#define DEFAULT_ID_PS 2000U
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struct nxp_c45_phy {
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u32 tx_delay;
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u32 rx_delay;
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};
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struct nxp_c45_phy_stats {
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const char *name;
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u8 mmd;
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u16 reg;
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u8 off;
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u16 mask;
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};
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static const struct nxp_c45_phy_stats nxp_c45_hw_stats[] = {
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{ "phy_symbol_error_cnt", MDIO_MMD_VEND1,
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VEND1_SYMBOL_ERROR_COUNTER, 0, GENMASK(15, 0) },
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{ "phy_link_status_drop_cnt", MDIO_MMD_VEND1,
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VEND1_LINK_DROP_COUNTER, 8, GENMASK(13, 8) },
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{ "phy_link_availability_drop_cnt", MDIO_MMD_VEND1,
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VEND1_LINK_DROP_COUNTER, 0, GENMASK(5, 0) },
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{ "phy_link_loss_cnt", MDIO_MMD_VEND1,
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VEND1_LINK_LOSSES_AND_FAILURES, 10, GENMASK(15, 10) },
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{ "phy_link_failure_cnt", MDIO_MMD_VEND1,
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VEND1_LINK_LOSSES_AND_FAILURES, 0, GENMASK(9, 0) },
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{ "r_good_frame_cnt", MDIO_MMD_VEND1,
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VEND1_R_GOOD_FRAME_CNT, 0, GENMASK(15, 0) },
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{ "r_bad_frame_cnt", MDIO_MMD_VEND1,
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VEND1_R_BAD_FRAME_CNT, 0, GENMASK(15, 0) },
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{ "r_rxer_frame_cnt", MDIO_MMD_VEND1,
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VEND1_R_RXER_FRAME_CNT, 0, GENMASK(15, 0) },
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{ "rx_preamble_count", MDIO_MMD_VEND1,
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VEND1_RX_PREAMBLE_COUNT, 0, GENMASK(5, 0) },
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{ "tx_preamble_count", MDIO_MMD_VEND1,
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VEND1_TX_PREAMBLE_COUNT, 0, GENMASK(5, 0) },
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{ "rx_ipg_length", MDIO_MMD_VEND1,
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VEND1_RX_IPG_LENGTH, 0, GENMASK(8, 0) },
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{ "tx_ipg_length", MDIO_MMD_VEND1,
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VEND1_TX_IPG_LENGTH, 0, GENMASK(8, 0) },
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};
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static int nxp_c45_get_sset_count(struct phy_device *phydev)
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{
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return ARRAY_SIZE(nxp_c45_hw_stats);
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}
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static void nxp_c45_get_strings(struct phy_device *phydev, u8 *data)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(nxp_c45_hw_stats); i++) {
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strncpy(data + i * ETH_GSTRING_LEN,
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nxp_c45_hw_stats[i].name, ETH_GSTRING_LEN);
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}
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}
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static void nxp_c45_get_stats(struct phy_device *phydev,
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struct ethtool_stats *stats, u64 *data)
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{
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size_t i;
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int ret;
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for (i = 0; i < ARRAY_SIZE(nxp_c45_hw_stats); i++) {
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ret = phy_read_mmd(phydev, nxp_c45_hw_stats[i].mmd,
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nxp_c45_hw_stats[i].reg);
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if (ret < 0) {
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data[i] = U64_MAX;
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} else {
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data[i] = ret & nxp_c45_hw_stats[i].mask;
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data[i] >>= nxp_c45_hw_stats[i].off;
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}
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}
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}
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static int nxp_c45_config_enable(struct phy_device *phydev)
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{
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
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DEVICE_CONTROL_CONFIG_GLOBAL_EN |
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DEVICE_CONTROL_CONFIG_ALL_EN);
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usleep_range(400, 450);
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL,
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PORT_CONTROL_EN);
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
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PHY_CONFIG_EN);
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL,
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PORT_INFRA_CONTROL_EN);
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return 0;
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}
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static int nxp_c45_start_op(struct phy_device *phydev)
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{
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return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
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PHY_START_OP);
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}
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static int nxp_c45_soft_reset(struct phy_device *phydev)
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{
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int ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
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DEVICE_CONTROL_RESET);
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if (ret)
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return ret;
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return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
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VEND1_DEVICE_CONTROL, ret,
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!(ret & DEVICE_CONTROL_RESET), 20000,
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240000, false);
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}
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static int nxp_c45_cable_test_start(struct phy_device *phydev)
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{
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return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST,
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CABLE_TEST_ENABLE | CABLE_TEST_START);
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}
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static int nxp_c45_cable_test_get_status(struct phy_device *phydev,
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bool *finished)
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{
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int ret;
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u8 cable_test_result;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST);
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if (!(ret & CABLE_TEST_VALID)) {
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*finished = false;
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return 0;
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}
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*finished = true;
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cable_test_result = ret & GENMASK(2, 0);
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switch (cable_test_result) {
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case CABLE_TEST_OK:
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
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ETHTOOL_A_CABLE_RESULT_CODE_OK);
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break;
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case CABLE_TEST_SHORTED:
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
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ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT);
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break;
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case CABLE_TEST_OPEN:
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
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ETHTOOL_A_CABLE_RESULT_CODE_OPEN);
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break;
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default:
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
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ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
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}
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phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST,
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CABLE_TEST_ENABLE);
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return nxp_c45_start_op(phydev);
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}
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static int nxp_c45_setup_master_slave(struct phy_device *phydev)
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{
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switch (phydev->master_slave_set) {
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case MASTER_SLAVE_CFG_MASTER_FORCE:
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case MASTER_SLAVE_CFG_MASTER_PREFERRED:
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL,
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MASTER_MODE);
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break;
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case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
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case MASTER_SLAVE_CFG_SLAVE_FORCE:
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL,
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SLAVE_MODE);
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break;
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case MASTER_SLAVE_CFG_UNKNOWN:
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case MASTER_SLAVE_CFG_UNSUPPORTED:
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return 0;
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default:
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phydev_warn(phydev, "Unsupported Master/Slave mode\n");
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int nxp_c45_read_master_slave(struct phy_device *phydev)
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{
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int reg;
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phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
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phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
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reg = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL);
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if (reg < 0)
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return reg;
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if (reg & B100T1_PMAPMD_MASTER) {
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phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
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phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
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} else {
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phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
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phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
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}
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return 0;
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}
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static int nxp_c45_config_aneg(struct phy_device *phydev)
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{
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return nxp_c45_setup_master_slave(phydev);
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}
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static int nxp_c45_read_status(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_c45_read_status(phydev);
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if (ret)
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return ret;
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ret = nxp_c45_read_master_slave(phydev);
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if (ret)
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return ret;
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return 0;
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}
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static int nxp_c45_get_sqi(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY);
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if (!(reg & SQI_VALID))
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return -EINVAL;
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reg &= SQI_MASK;
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return reg;
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}
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static int nxp_c45_get_sqi_max(struct phy_device *phydev)
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{
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return MAX_SQI;
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}
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static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay)
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{
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if (delay < MIN_ID_PS) {
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phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS);
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return -EINVAL;
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}
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if (delay > MAX_ID_PS) {
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phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS);
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return -EINVAL;
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}
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return 0;
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}
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static u64 nxp_c45_get_phase_shift(u64 phase_offset_raw)
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{
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/* The delay in degree phase is 73.8 + phase_offset_raw * 0.9.
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* To avoid floating point operations we'll multiply by 10
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* and get 1 decimal point precision.
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*/
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phase_offset_raw *= 10;
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phase_offset_raw -= phase_offset_raw;
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return div_u64(phase_offset_raw, 9);
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}
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static void nxp_c45_disable_delays(struct phy_device *phydev)
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{
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phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE);
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phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE);
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}
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static void nxp_c45_set_delays(struct phy_device *phydev)
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{
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struct nxp_c45_phy *priv = phydev->priv;
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u64 tx_delay = priv->tx_delay;
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u64 rx_delay = priv->rx_delay;
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u64 degree;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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degree = div_u64(tx_delay, PS_PER_DEGREE);
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
|
||||
ID_ENABLE | nxp_c45_get_phase_shift(degree));
|
||||
} else {
|
||||
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
|
||||
ID_ENABLE);
|
||||
}
|
||||
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
|
||||
degree = div_u64(rx_delay, PS_PER_DEGREE);
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
|
||||
ID_ENABLE | nxp_c45_get_phase_shift(degree));
|
||||
} else {
|
||||
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
|
||||
ID_ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
static int nxp_c45_get_delays(struct phy_device *phydev)
|
||||
{
|
||||
struct nxp_c45_phy *priv = phydev->priv;
|
||||
int ret;
|
||||
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
|
||||
ret = device_property_read_u32(&phydev->mdio.dev,
|
||||
"tx-internal-delay-ps",
|
||||
&priv->tx_delay);
|
||||
if (ret)
|
||||
priv->tx_delay = DEFAULT_ID_PS;
|
||||
|
||||
ret = nxp_c45_check_delay(phydev, priv->tx_delay);
|
||||
if (ret) {
|
||||
phydev_err(phydev,
|
||||
"tx-internal-delay-ps invalid value\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
|
||||
ret = device_property_read_u32(&phydev->mdio.dev,
|
||||
"rx-internal-delay-ps",
|
||||
&priv->rx_delay);
|
||||
if (ret)
|
||||
priv->rx_delay = DEFAULT_ID_PS;
|
||||
|
||||
ret = nxp_c45_check_delay(phydev, priv->rx_delay);
|
||||
if (ret) {
|
||||
phydev_err(phydev,
|
||||
"rx-internal-delay-ps invalid value\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nxp_c45_set_phy_mode(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES);
|
||||
phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret);
|
||||
|
||||
switch (phydev->interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
if (!(ret & RGMII_ABILITY)) {
|
||||
phydev_err(phydev, "rgmii mode not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
|
||||
MII_BASIC_CONFIG_RGMII);
|
||||
nxp_c45_disable_delays(phydev);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
if (!(ret & RGMII_ID_ABILITY)) {
|
||||
phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
|
||||
MII_BASIC_CONFIG_RGMII);
|
||||
ret = nxp_c45_get_delays(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nxp_c45_set_delays(phydev);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
if (!(ret & MII_ABILITY)) {
|
||||
phydev_err(phydev, "mii mode not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
|
||||
MII_BASIC_CONFIG_MII);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_REVMII:
|
||||
if (!(ret & REVMII_ABILITY)) {
|
||||
phydev_err(phydev, "rev-mii mode not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
|
||||
MII_BASIC_CONFIG_MII | MII_BASIC_CONFIG_REV);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
if (!(ret & RMII_ABILITY)) {
|
||||
phydev_err(phydev, "rmii mode not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
|
||||
MII_BASIC_CONFIG_RMII);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
if (!(ret & SGMII_ABILITY)) {
|
||||
phydev_err(phydev, "sgmii mode not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
|
||||
MII_BASIC_CONFIG_SGMII);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_INTERNAL:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nxp_c45_config_init(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = nxp_c45_config_enable(phydev);
|
||||
if (ret) {
|
||||
phydev_err(phydev, "Failed to enable config\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
|
||||
PHY_CONFIG_AUTO);
|
||||
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER,
|
||||
COUNTER_EN);
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT,
|
||||
COUNTER_EN);
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT,
|
||||
COUNTER_EN);
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH,
|
||||
COUNTER_EN);
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH,
|
||||
COUNTER_EN);
|
||||
|
||||
ret = nxp_c45_set_phy_mode(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
phydev->autoneg = AUTONEG_DISABLE;
|
||||
|
||||
return nxp_c45_start_op(phydev);
|
||||
}
|
||||
|
||||
static int nxp_c45_probe(struct phy_device *phydev)
|
||||
{
|
||||
struct nxp_c45_phy *priv;
|
||||
|
||||
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
phydev->priv = priv;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy_driver nxp_c45_driver[] = {
|
||||
{
|
||||
PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103),
|
||||
.name = "NXP C45 TJA1103",
|
||||
.features = PHY_BASIC_T1_FEATURES,
|
||||
.probe = nxp_c45_probe,
|
||||
.soft_reset = nxp_c45_soft_reset,
|
||||
.config_aneg = nxp_c45_config_aneg,
|
||||
.config_init = nxp_c45_config_init,
|
||||
.read_status = nxp_c45_read_status,
|
||||
.suspend = genphy_c45_pma_suspend,
|
||||
.resume = genphy_c45_pma_resume,
|
||||
.get_sset_count = nxp_c45_get_sset_count,
|
||||
.get_strings = nxp_c45_get_strings,
|
||||
.get_stats = nxp_c45_get_stats,
|
||||
.cable_test_start = nxp_c45_cable_test_start,
|
||||
.cable_test_get_status = nxp_c45_cable_test_get_status,
|
||||
.set_loopback = genphy_c45_loopback,
|
||||
.get_sqi = nxp_c45_get_sqi,
|
||||
.get_sqi_max = nxp_c45_get_sqi_max,
|
||||
},
|
||||
};
|
||||
|
||||
module_phy_driver(nxp_c45_driver);
|
||||
|
||||
static struct mdio_device_id __maybe_unused nxp_c45_tbl[] = {
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103) },
|
||||
{ /*sentinel*/ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(mdio, nxp_c45_tbl);
|
||||
|
||||
MODULE_AUTHOR("Radu Pirea <radu-nicolae.pirea@oss.nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP C45 PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user