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[IA64] SGI Altix : fix bug in sn_io_late_init()
When initializing pci_controller->node to point to the closest node we need to take into consideration that a PIC PCI Bridge ASIC can be connected to a headless/memless node just like the TIOCP and TIOCE Bridge ASICs Signed-off-by: Mike Habeck <habeck@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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@ -545,19 +545,18 @@ sn_io_late_init(void)
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nasid = NASID_GET(bussoft->bs_base);
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cnode = nasid_to_cnodeid(nasid);
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if ((bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) ||
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(bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCE)) {
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/* TIO PCI Bridge: find nearest node with CPUs */
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(bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCE) ||
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(bussoft->bs_asic_type == PCIIO_ASIC_TYPE_PIC)) {
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/* PCI Bridge: find nearest node with CPUs */
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int e = sn_hwperf_get_nearest_node(cnode, NULL,
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&near_cnode);
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if (e < 0) {
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near_cnode = (cnodeid_t)-1; /* use any node */
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printk(KERN_WARNING "pcibr_bus_fixup: failed "
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"to find near node with CPUs to TIO "
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printk(KERN_WARNING "sn_io_late_init: failed "
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"to find near node with CPUs for "
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"node %d, err=%d\n", cnode, e);
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}
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PCI_CONTROLLER(bus)->node = near_cnode;
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} else if (bussoft->bs_asic_type == PCIIO_ASIC_TYPE_PIC) {
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PCI_CONTROLLER(bus)->node = cnode;
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}
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}
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