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Merge branch 'remotes/lorenzo/pci/keembay'
- Add Intel Keem Bay PCIe controller driver and DT binding (Srikanth Thokala) * remotes/lorenzo/pci/keembay: PCI: keembay: Add support for Intel Keem Bay dt-bindings: PCI: Add Intel Keem Bay PCIe controller
This commit is contained in:
Bjorn Helgaas
commit
af42a0d4a8
@ -0,0 +1,69 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel Keem Bay PCIe controller Endpoint mode
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maintainers:
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- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
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- Srikanth Thokala <srikanth.thokala@intel.com>
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properties:
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compatible:
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const: intel,keembay-pcie-ep
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reg:
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maxItems: 5
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: addr_space
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- const: apb
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interrupts:
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maxItems: 4
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interrupt-names:
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items:
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- const: pcie
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- const: pcie_ev
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- const: pcie_err
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- const: pcie_mem_access
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num-lanes:
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description: Number of lanes to use.
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enum: [ 1, 2 ]
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie-ep@37000000 {
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compatible = "intel,keembay-pcie-ep";
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reg = <0x37000000 0x00001000>,
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<0x37100000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36000000 0x01000000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
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num-lanes = <2>;
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};
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@ -0,0 +1,97 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel Keem Bay PCIe controller Root Complex mode
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maintainers:
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- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
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- Srikanth Thokala <srikanth.thokala@intel.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: intel,keembay-pcie
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ranges:
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maxItems: 1
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reset-gpios:
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maxItems: 1
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: dbi
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- const: atu
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- const: config
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- const: apb
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: master
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- const: aux
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interrupts:
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maxItems: 3
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interrupt-names:
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items:
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- const: pcie
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- const: pcie_ev
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- const: pcie_err
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num-lanes:
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description: Number of lanes to use.
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enum: [ 1, 2 ]
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required:
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- compatible
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- reg
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- reg-names
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- ranges
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#define KEEM_BAY_A53_PCIE
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#define KEEM_BAY_A53_AUX_PCIE
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pcie@37000000 {
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compatible = "intel,keembay-pcie";
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reg = <0x37000000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36e00000 0x00200000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "atu", "config", "apb";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err";
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clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
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<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
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clock-names = "master", "aux";
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reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
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num-lanes = <2>;
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};
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@ -14424,6 +14424,13 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
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F: drivers/pci/controller/dwc/pcie-histb.c
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PCIE DRIVER FOR INTEL KEEM BAY
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M: Srikanth Thokala <srikanth.thokala@intel.com>
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L: linux-pci@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/pci/intel,keembay-pcie*
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F: drivers/pci/controller/dwc/pcie-keembay.c
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PCIE DRIVER FOR MEDIATEK
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M: Ryder Lee <ryder.lee@mediatek.com>
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M: Jianjun Wang <jianjun.wang@mediatek.com>
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@ -236,6 +236,34 @@ config PCIE_INTEL_GW
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The PCIe controller uses the DesignWare core plus Intel-specific
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hardware wrappers.
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config PCIE_KEEMBAY
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bool
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config PCIE_KEEMBAY_HOST
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bool "Intel Keem Bay PCIe controller - Host mode"
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depends on ARCH_KEEMBAY || COMPILE_TEST
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depends on PCI && PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCIE_KEEMBAY
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help
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Say 'Y' here to enable support for the PCIe controller in Keem Bay
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to work in host mode.
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The PCIe controller is based on DesignWare Hardware and uses
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DesignWare core functions.
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config PCIE_KEEMBAY_EP
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bool "Intel Keem Bay PCIe controller - Endpoint mode"
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depends on ARCH_KEEMBAY || COMPILE_TEST
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depends on PCI && PCI_MSI_IRQ_DOMAIN
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_KEEMBAY
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help
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Say 'Y' here to enable support for the PCIe controller in Keem Bay
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to work in endpoint mode.
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The PCIe controller is based on DesignWare Hardware and uses
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DesignWare core functions.
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config PCIE_KIRIN
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depends on OF && (ARM64 || COMPILE_TEST)
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bool "HiSilicon Kirin series SoCs PCIe controllers"
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@ -16,6 +16,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o
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obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
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obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
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obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
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obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
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obj-$(CONFIG_PCI_MESON) += pci-meson.o
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460
drivers/pci/controller/dwc/pcie-keembay.c
Normal file
460
drivers/pci/controller/dwc/pcie-keembay.c
Normal file
@ -0,0 +1,460 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PCIe controller driver for Intel Keem Bay
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* Copyright (C) 2020 Intel Corporation
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio/consumer.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include "pcie-designware.h"
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/* PCIE_REGS_APB_SLV Registers */
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#define PCIE_REGS_PCIE_CFG 0x0004
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#define PCIE_DEVICE_TYPE BIT(8)
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#define PCIE_RSTN BIT(0)
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#define PCIE_REGS_PCIE_APP_CNTRL 0x0008
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#define APP_LTSSM_ENABLE BIT(0)
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#define PCIE_REGS_INTERRUPT_ENABLE 0x0028
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#define MSI_CTRL_INT_EN BIT(8)
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#define EDMA_INT_EN GENMASK(7, 0)
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#define PCIE_REGS_INTERRUPT_STATUS 0x002c
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#define MSI_CTRL_INT BIT(8)
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#define PCIE_REGS_PCIE_SII_PM_STATE 0x00b0
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#define SMLH_LINK_UP BIT(19)
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#define RDLH_LINK_UP BIT(8)
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#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP)
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#define PCIE_REGS_PCIE_PHY_CNTL 0x0164
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#define PHY0_SRAM_BYPASS BIT(8)
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#define PCIE_REGS_PCIE_PHY_STAT 0x0168
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#define PHY0_MPLLA_STATE BIT(1)
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#define PCIE_REGS_LJPLL_STA 0x016c
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#define LJPLL_LOCK BIT(0)
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#define PCIE_REGS_LJPLL_CNTRL_0 0x0170
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#define LJPLL_EN BIT(29)
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#define LJPLL_FOUT_EN GENMASK(24, 21)
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#define PCIE_REGS_LJPLL_CNTRL_2 0x0178
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#define LJPLL_REF_DIV GENMASK(17, 12)
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#define LJPLL_FB_DIV GENMASK(11, 0)
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#define PCIE_REGS_LJPLL_CNTRL_3 0x017c
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#define LJPLL_POST_DIV3A GENMASK(24, 22)
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#define LJPLL_POST_DIV2A GENMASK(18, 16)
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#define PERST_DELAY_US 1000
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#define AUX_CLK_RATE_HZ 24000000
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struct keembay_pcie {
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struct dw_pcie pci;
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void __iomem *apb_base;
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enum dw_pcie_device_mode mode;
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struct clk *clk_master;
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struct clk *clk_aux;
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struct gpio_desc *reset;
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};
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struct keembay_pcie_of_data {
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enum dw_pcie_device_mode mode;
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};
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static void keembay_ep_reset_assert(struct keembay_pcie *pcie)
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{
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gpiod_set_value_cansleep(pcie->reset, 1);
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usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
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}
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static void keembay_ep_reset_deassert(struct keembay_pcie *pcie)
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{
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/*
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* Ensure that PERST# is asserted for a minimum of 100ms.
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*
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* For more details, refer to PCI Express Card Electromechanical
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* Specification Revision 1.1, Table-2.4.
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*/
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msleep(100);
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gpiod_set_value_cansleep(pcie->reset, 0);
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usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
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}
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static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable)
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{
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u32 val;
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val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL);
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if (enable)
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val |= APP_LTSSM_ENABLE;
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else
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val &= ~APP_LTSSM_ENABLE;
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writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL);
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}
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static int keembay_pcie_link_up(struct dw_pcie *pci)
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{
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struct keembay_pcie *pcie = dev_get_drvdata(pci->dev);
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u32 val;
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val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE);
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return (val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP;
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}
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static int keembay_pcie_start_link(struct dw_pcie *pci)
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{
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struct keembay_pcie *pcie = dev_get_drvdata(pci->dev);
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u32 val;
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int ret;
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if (pcie->mode == DW_PCIE_EP_TYPE)
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return 0;
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keembay_pcie_ltssm_set(pcie, false);
|
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|
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ret = readl_poll_timeout(pcie->apb_base + PCIE_REGS_PCIE_PHY_STAT,
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val, val & PHY0_MPLLA_STATE, 20,
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500 * USEC_PER_MSEC);
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if (ret) {
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dev_err(pci->dev, "MPLLA is not locked\n");
|
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return ret;
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}
|
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|
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keembay_pcie_ltssm_set(pcie, true);
|
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|
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return 0;
|
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}
|
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|
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static void keembay_pcie_stop_link(struct dw_pcie *pci)
|
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{
|
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struct keembay_pcie *pcie = dev_get_drvdata(pci->dev);
|
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|
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keembay_pcie_ltssm_set(pcie, false);
|
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}
|
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|
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static const struct dw_pcie_ops keembay_pcie_ops = {
|
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.link_up = keembay_pcie_link_up,
|
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.start_link = keembay_pcie_start_link,
|
||||
.stop_link = keembay_pcie_stop_link,
|
||||
};
|
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|
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static inline struct clk *keembay_pcie_probe_clock(struct device *dev,
|
||||
const char *id, u64 rate)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
clk = devm_clk_get(dev, id);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
|
||||
if (rate) {
|
||||
ret = clk_set_rate(clk, rate);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
ret = devm_add_action_or_reset(dev,
|
||||
(void(*)(void *))clk_disable_unprepare,
|
||||
clk);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static int keembay_pcie_probe_clocks(struct keembay_pcie *pcie)
|
||||
{
|
||||
struct dw_pcie *pci = &pcie->pci;
|
||||
struct device *dev = pci->dev;
|
||||
|
||||
pcie->clk_master = keembay_pcie_probe_clock(dev, "master", 0);
|
||||
if (IS_ERR(pcie->clk_master))
|
||||
return dev_err_probe(dev, PTR_ERR(pcie->clk_master),
|
||||
"Failed to enable master clock");
|
||||
|
||||
pcie->clk_aux = keembay_pcie_probe_clock(dev, "aux", AUX_CLK_RATE_HZ);
|
||||
if (IS_ERR(pcie->clk_aux))
|
||||
return dev_err_probe(dev, PTR_ERR(pcie->clk_aux),
|
||||
"Failed to enable auxiliary clock");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the internal PCIe PLL in Host mode.
|
||||
* See the following sections in Keem Bay data book,
|
||||
* (1) 6.4.6.1 PCIe Subsystem Example Initialization,
|
||||
* (2) 6.8 PCIe Low Jitter PLL for Ref Clk Generation.
|
||||
*/
|
||||
static int keembay_pcie_pll_init(struct keembay_pcie *pcie)
|
||||
{
|
||||
struct dw_pcie *pci = &pcie->pci;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
val = FIELD_PREP(LJPLL_REF_DIV, 0) | FIELD_PREP(LJPLL_FB_DIV, 0x32);
|
||||
writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_2);
|
||||
|
||||
val = FIELD_PREP(LJPLL_POST_DIV3A, 0x2) |
|
||||
FIELD_PREP(LJPLL_POST_DIV2A, 0x2);
|
||||
writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_3);
|
||||
|
||||
val = FIELD_PREP(LJPLL_EN, 0x1) | FIELD_PREP(LJPLL_FOUT_EN, 0xc);
|
||||
writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_0);
|
||||
|
||||
ret = readl_poll_timeout(pcie->apb_base + PCIE_REGS_LJPLL_STA,
|
||||
val, val & LJPLL_LOCK, 20,
|
||||
500 * USEC_PER_MSEC);
|
||||
if (ret)
|
||||
dev_err(pci->dev, "Low jitter PLL is not locked\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void keembay_pcie_msi_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct keembay_pcie *pcie = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
u32 val, mask, status;
|
||||
struct pcie_port *pp;
|
||||
|
||||
/*
|
||||
* Keem Bay PCIe Controller provides an additional IP logic on top of
|
||||
* standard DWC IP to clear MSI IRQ by writing '1' to the respective
|
||||
* bit of the status register.
|
||||
*
|
||||
* So, a chained irq handler is defined to handle this additional
|
||||
* IP logic.
|
||||
*/
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
pp = &pcie->pci.pp;
|
||||
val = readl(pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS);
|
||||
mask = readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE);
|
||||
|
||||
status = val & mask;
|
||||
|
||||
if (status & MSI_CTRL_INT) {
|
||||
dw_handle_msi_irq(pp);
|
||||
writel(status, pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS);
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static int keembay_pcie_setup_msi_irq(struct keembay_pcie *pcie)
|
||||
{
|
||||
struct dw_pcie *pci = &pcie->pci;
|
||||
struct device *dev = pci->dev;
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
int irq;
|
||||
|
||||
irq = platform_get_irq_byname(pdev, "pcie");
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
irq_set_chained_handler_and_data(irq, keembay_pcie_msi_irq_handler,
|
||||
pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void keembay_pcie_ep_init(struct dw_pcie_ep *ep)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
struct keembay_pcie *pcie = dev_get_drvdata(pci->dev);
|
||||
|
||||
writel(EDMA_INT_EN, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE);
|
||||
}
|
||||
|
||||
static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
enum pci_epc_irq_type type,
|
||||
u16 interrupt_num)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
|
||||
switch (type) {
|
||||
case PCI_EPC_IRQ_LEGACY:
|
||||
/* Legacy interrupts are not supported in Keem Bay */
|
||||
dev_err(pci->dev, "Legacy IRQ is not supported\n");
|
||||
return -EINVAL;
|
||||
case PCI_EPC_IRQ_MSI:
|
||||
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
|
||||
case PCI_EPC_IRQ_MSIX:
|
||||
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
|
||||
default:
|
||||
dev_err(pci->dev, "Unknown IRQ type %d\n", type);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pci_epc_features keembay_pcie_epc_features = {
|
||||
.linkup_notifier = false,
|
||||
.msi_capable = true,
|
||||
.msix_capable = true,
|
||||
.reserved_bar = BIT(BAR_1) | BIT(BAR_3) | BIT(BAR_5),
|
||||
.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
|
||||
.align = SZ_16K,
|
||||
};
|
||||
|
||||
static const struct pci_epc_features *
|
||||
keembay_pcie_get_features(struct dw_pcie_ep *ep)
|
||||
{
|
||||
return &keembay_pcie_epc_features;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_ep_ops keembay_pcie_ep_ops = {
|
||||
.ep_init = keembay_pcie_ep_init,
|
||||
.raise_irq = keembay_pcie_ep_raise_irq,
|
||||
.get_features = keembay_pcie_get_features,
|
||||
};
|
||||
|
||||
static const struct dw_pcie_host_ops keembay_pcie_host_ops = {
|
||||
};
|
||||
|
||||
static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct dw_pcie *pci = &pcie->pci;
|
||||
struct pcie_port *pp = &pci->pp;
|
||||
struct device *dev = &pdev->dev;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
pp->ops = &keembay_pcie_host_ops;
|
||||
pp->msi_irq = -ENODEV;
|
||||
|
||||
ret = keembay_pcie_setup_msi_irq(pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pcie->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(pcie->reset))
|
||||
return PTR_ERR(pcie->reset);
|
||||
|
||||
ret = keembay_pcie_probe_clocks(pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val = readl(pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL);
|
||||
val |= PHY0_SRAM_BYPASS;
|
||||
writel(val, pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL);
|
||||
|
||||
writel(PCIE_DEVICE_TYPE, pcie->apb_base + PCIE_REGS_PCIE_CFG);
|
||||
|
||||
ret = keembay_pcie_pll_init(pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val = readl(pcie->apb_base + PCIE_REGS_PCIE_CFG);
|
||||
writel(val | PCIE_RSTN, pcie->apb_base + PCIE_REGS_PCIE_CFG);
|
||||
keembay_ep_reset_deassert(pcie);
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
keembay_ep_reset_assert(pcie);
|
||||
dev_err(dev, "Failed to initialize host: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
val = readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE);
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
val |= MSI_CTRL_INT_EN;
|
||||
writel(val, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int keembay_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct keembay_pcie_of_data *data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct keembay_pcie *pcie;
|
||||
struct dw_pcie *pci;
|
||||
enum dw_pcie_device_mode mode;
|
||||
|
||||
data = device_get_match_data(dev);
|
||||
if (!data)
|
||||
return -ENODEV;
|
||||
|
||||
mode = (enum dw_pcie_device_mode)data->mode;
|
||||
|
||||
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pci = &pcie->pci;
|
||||
pci->dev = dev;
|
||||
pci->ops = &keembay_pcie_ops;
|
||||
|
||||
pcie->mode = mode;
|
||||
|
||||
pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
|
||||
if (IS_ERR(pcie->apb_base))
|
||||
return PTR_ERR(pcie->apb_base);
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
switch (pcie->mode) {
|
||||
case DW_PCIE_RC_TYPE:
|
||||
if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_HOST))
|
||||
return -ENODEV;
|
||||
|
||||
return keembay_pcie_add_pcie_port(pcie, pdev);
|
||||
case DW_PCIE_EP_TYPE:
|
||||
if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_EP))
|
||||
return -ENODEV;
|
||||
|
||||
pci->ep.ops = &keembay_pcie_ep_ops;
|
||||
return dw_pcie_ep_init(&pci->ep);
|
||||
default:
|
||||
dev_err(dev, "Invalid device type %d\n", pcie->mode);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct keembay_pcie_of_data keembay_pcie_rc_of_data = {
|
||||
.mode = DW_PCIE_RC_TYPE,
|
||||
};
|
||||
|
||||
static const struct keembay_pcie_of_data keembay_pcie_ep_of_data = {
|
||||
.mode = DW_PCIE_EP_TYPE,
|
||||
};
|
||||
|
||||
static const struct of_device_id keembay_pcie_of_match[] = {
|
||||
{
|
||||
.compatible = "intel,keembay-pcie",
|
||||
.data = &keembay_pcie_rc_of_data,
|
||||
},
|
||||
{
|
||||
.compatible = "intel,keembay-pcie-ep",
|
||||
.data = &keembay_pcie_ep_of_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver keembay_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "keembay-pcie",
|
||||
.of_match_table = keembay_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = keembay_pcie_probe,
|
||||
};
|
||||
builtin_platform_driver(keembay_pcie_driver);
|
||||
Loading…
Reference in New Issue
Block a user