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drm/sun4i: DW HDMI PHY: Add support for second PLL

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Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select
between two clock parents.

Add code which reads second PLL from DT.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-19-jernej.skrabec@siol.net
This commit is contained in:
Jernej Skrabec 2018-06-25 14:02:58 +02:00 committed by Maxime Ripard
parent 09f380e3ba
commit aef13fd842
No known key found for this signature in database
GPG Key ID: D2B4C094214DAF74
2 changed files with 17 additions and 5 deletions
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2
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
View File

@ -147,6 +147,7 @@ struct sun8i_hdmi_phy;
struct sun8i_hdmi_phy_variant { struct sun8i_hdmi_phy_variant {
bool has_phy_clk; bool has_phy_clk;
bool has_second_pll;
void (*phy_init)(struct sun8i_hdmi_phy *phy); void (*phy_init)(struct sun8i_hdmi_phy *phy);
void (*phy_disable)(struct dw_hdmi *hdmi, void (*phy_disable)(struct dw_hdmi *hdmi,
struct sun8i_hdmi_phy *phy); struct sun8i_hdmi_phy *phy);
@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
struct clk *clk_mod; struct clk *clk_mod;
struct clk *clk_phy; struct clk *clk_phy;
struct clk *clk_pll0; struct clk *clk_pll0;
struct clk *clk_pll1;
unsigned int rcal; unsigned int rcal;
struct regmap *regs; struct regmap *regs;
struct reset_control *rst_phy; struct reset_control *rst_phy;

20
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
View File

@ -482,10 +482,19 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
goto err_put_clk_mod; goto err_put_clk_mod;
} }
if (phy->variant->has_second_pll) {
phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");
if (IS_ERR(phy->clk_pll1)) {
dev_err(dev, "Could not get pll-1 clock\n");
ret = PTR_ERR(phy->clk_pll1);
goto err_put_clk_pll0;
}
}
ret = sun8i_phy_clk_create(phy, dev); ret = sun8i_phy_clk_create(phy, dev);
if (ret) { if (ret) {
dev_err(dev, "Couldn't create the PHY clock\n"); dev_err(dev, "Couldn't create the PHY clock\n");
goto err_put_clk_pll0; goto err_put_clk_pll1;
} }
clk_prepare_enable(phy->clk_phy); clk_prepare_enable(phy->clk_phy);
@ -528,9 +537,10 @@ err_put_rst_phy:
reset_control_put(phy->rst_phy); reset_control_put(phy->rst_phy);
err_disable_clk_phy: err_disable_clk_phy:
clk_disable_unprepare(phy->clk_phy); clk_disable_unprepare(phy->clk_phy);
err_put_clk_pll1:
clk_put(phy->clk_pll1);
err_put_clk_pll0: err_put_clk_pll0:
if (phy->variant->has_phy_clk) clk_put(phy->clk_pll0);
clk_put(phy->clk_pll0);
err_put_clk_mod: err_put_clk_mod:
clk_put(phy->clk_mod); clk_put(phy->clk_mod);
err_put_clk_bus: err_put_clk_bus:
@ -551,8 +561,8 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
reset_control_put(phy->rst_phy); reset_control_put(phy->rst_phy);
if (phy->variant->has_phy_clk) clk_put(phy->clk_pll0);
clk_put(phy->clk_pll0); clk_put(phy->clk_pll1);
clk_put(phy->clk_mod); clk_put(phy->clk_mod);
clk_put(phy->clk_bus); clk_put(phy->clk_bus);
} }