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ALSA: hda/ca0132 - Add stream port remapping function.
Add function for remapping a ChipIO stream's ports. Also include some documentation as to how this works. Signed-off-by: Connor McAdams <conmanx360@gmail.com> Link: https://lore.kernel.org/r/20201210160658.461739-3-conmanx360@gmail.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Connor McAdams
Takashi Iwai
parent
4a6d3b4e7a
commit
aedeb64211
@ -788,6 +788,40 @@ static const struct ae5_filter_set ae5_filter_presets[] = {
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}
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};
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/*
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* Data structures for storing audio router remapping data. These are used to
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* remap a currently active streams ports.
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*/
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struct chipio_stream_remap_data {
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unsigned int stream_id;
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unsigned int count;
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unsigned int offset[16];
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unsigned int value[16];
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};
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static const struct chipio_stream_remap_data stream_remap_data[] = {
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{ .stream_id = 0x14,
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.count = 0x04,
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.offset = { 0x00, 0x04, 0x08, 0x0c },
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.value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
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},
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{ .stream_id = 0x0c,
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.count = 0x0c,
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.offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
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0x20, 0x24, 0x28, 0x2c },
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.value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
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0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
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0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
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},
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{ .stream_id = 0x0c,
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.count = 0x08,
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.offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
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.value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
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0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
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}
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};
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enum hda_cmd_vendor_io {
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/* for DspIO node */
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VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
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@ -7423,6 +7457,104 @@ static void ca0132_refresh_widget_caps(struct hda_codec *codec)
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}
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}
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/*
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* The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
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* router', where each entry represents a 48khz audio channel, with a format
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* of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
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* value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
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* and 3 if it's using Sample Rate Converter ports.
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* An example is:
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* 0x0001f8c0
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* In this case, f8 is the destination, and c0 is the source. The number value
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* is 1.
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* This region of memory is normally managed internally by the 8051, where
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* the region of exram memory from 0x1477-0x1575 has each byte represent an
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* entry within the 0x190000 range, and when a range of entries is in use, the
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* ending value is overwritten with 0xff.
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* 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
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* streamID's, where each entry is a starting 0x190000 port offset.
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* 0x159d in exram is the same as 0x1578, except it contains the ending port
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* offset for the corresponding streamID.
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*
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* On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
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* the 8051, then manually overwritten to remap the ports to work with the
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* new DACs.
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*
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* Currently known portID's:
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* 0x00-0x1f: HDA audio stream input/output ports.
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* 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
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* have the lower-nibble set to 0x1, 0x2, and 0x9.
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* 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
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* 0xe0-0xff: DAC/ADC audio input/output ports.
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*
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* Currently known streamID's:
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* 0x03: Mic1 ADC to DSP.
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* 0x04: Mic2 ADC to DSP.
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* 0x05: HDA node 0x02 audio stream to DSP.
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* 0x0f: DSP Mic exit to HDA node 0x07.
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* 0x0c: DSP processed audio to DACs.
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* 0x14: DAC0, front L/R.
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*
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* It is possible to route the HDA audio streams directly to the DAC and
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* bypass the DSP entirely, with the only downside being that since the DSP
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* does volume control, the only volume control you'll get is through PCM on
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* the PC side, in the same way volume is handled for optical out. This may be
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* useful for debugging.
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*/
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static void chipio_remap_stream(struct hda_codec *codec,
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const struct chipio_stream_remap_data *remap_data)
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{
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unsigned int i, stream_offset, tmp;
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/* Get the starting port for the stream to be remapped. */
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tmp = 0x1578 + remap_data->stream_id;
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for (i = 0; i < 2; i++) {
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW + i,
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((tmp >> (i * 8)) & 0xff));
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}
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stream_offset = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_DATA_READ, 0);
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/*
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* Check if the stream's port value is 0xff, because the 8051 may not
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* have gotten around to setting up the stream yet. Wait until it's
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* setup to remap it's ports.
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*/
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if (stream_offset == 0xff) {
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for (i = 0; i < 5; i++) {
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msleep(25);
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stream_offset = snd_hda_codec_read(codec,
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WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_DATA_READ, 0);
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if (stream_offset != 0xff)
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break;
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}
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}
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if (stream_offset == 0xff) {
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codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
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__func__, remap_data->stream_id);
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return;
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}
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/* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
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stream_offset *= 0x04;
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stream_offset += 0x190000;
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for (i = 0; i < remap_data->count; i++) {
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chipio_write_no_mutex(codec,
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stream_offset + remap_data->offset[i],
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remap_data->value[i]);
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}
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/* Update stream map configuration. */
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chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
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}
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/*
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* Default speaker tuning values setup for alternative codecs.
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*/
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@ -7570,46 +7702,35 @@ static void sbz_connect_streams(struct hda_codec *codec)
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*/
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static void sbz_chipio_startup_data(struct hda_codec *codec)
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{
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const struct chipio_stream_remap_data *dsp_out_remap_data;
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struct ca0132_spec *spec = codec->spec;
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mutex_lock(&spec->chipio_mutex);
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codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
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/* These control audio output */
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chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
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chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
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chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
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chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
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/* Signal to update I think */
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chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
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/* Remap DAC0's output ports. */
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chipio_remap_stream(codec, &stream_remap_data[0]);
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chipio_set_stream_channels(codec, 0x0C, 6);
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chipio_set_stream_control(codec, 0x0C, 1);
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/* No clue what these control */
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if (ca0132_quirk(spec) == QUIRK_SBZ) {
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chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
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chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
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chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
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chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
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chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
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chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
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chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
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chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
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chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
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chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
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chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
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chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
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} else if (ca0132_quirk(spec) == QUIRK_ZXR) {
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chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
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chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
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chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
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chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
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chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
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chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
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chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
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chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
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/* Remap DSP audio output stream ports. */
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switch (ca0132_quirk(spec)) {
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case QUIRK_SBZ:
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dsp_out_remap_data = &stream_remap_data[1];
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break;
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case QUIRK_ZXR:
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dsp_out_remap_data = &stream_remap_data[2];
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break;
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default:
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dsp_out_remap_data = NULL;
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break;
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}
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chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
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chipio_set_stream_channels(codec, 0x0c, 6);
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chipio_set_stream_control(codec, 0x0c, 1);
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if (dsp_out_remap_data)
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chipio_remap_stream(codec, dsp_out_remap_data);
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codec_dbg(codec, "Startup Data exited, mutex released.\n");
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mutex_unlock(&spec->chipio_mutex);
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@ -7842,34 +7963,17 @@ static void ae5_post_dsp_startup_data(struct hda_codec *codec)
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mutex_unlock(&spec->chipio_mutex);
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}
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static const unsigned int ae7_port_set_data[] = {
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0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5,
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0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb
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};
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static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
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{
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struct ca0132_spec *spec = codec->spec;
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unsigned int i, count, addr;
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mutex_lock(&spec->chipio_mutex);
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chipio_set_stream_channels(codec, 0x0c, 6);
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chipio_set_stream_control(codec, 0x0c, 1);
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count = ARRAY_SIZE(ae7_port_set_data);
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addr = 0x190030;
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for (i = 0; i < count; i++) {
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chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]);
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/* Addresses are incremented by 4-bytes. */
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addr += 0x04;
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}
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/*
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* Port setting always ends with a write of 0x1 to address 0x19042c.
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*/
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chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
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/* Seems to share the same port remapping as the SBZ. */
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chipio_remap_stream(codec, &stream_remap_data[1]);
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ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
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ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
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