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Amlogic clock fixes for v6.5
* Fix PLL scheduling while atomic following a1 locking sequence update -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmS+QfMACgkQ5vwPHDfy 2oW2CA//VnwEsS2uHSJ8Cx7DW+3CCmnwPRtVpWHMVgXITsh0/lIIAaR/BVRg5oCG TLwmY2xeb7HNs56eZhtyW5C4W6CDr8UT6pAU+4adpt46zcOT+dqMPeU9/K0m8+KP vsU7+Y7HM+T9V6yIi6CO5OV6XzHtWn4QAgiDI5aeuCbL1LzMnp39MAsJPCk+uWG3 NjmuoD3/+DgO5kbPE36Z9WpTcyZyexrnu/T0ff4ffcXhN0Kc41KAis4IXa0euVJS mmSPa/YHLM7R2dlTGxwJI1UGq+Cb/qL9wtGnhfkOQIaQJtf30S3cuFkaJu9KvabG 3+7JXq88qxFnautSfPuoQWMr0/tzQ/nMKKGam6IY2yCSvSclGa8sx0gSnA8Uwkrq REuxH0PnYZJqezsZy+3RWYXw4hHFVKTEHyIWXFNvydyEjuMsYiCN1vU0Sm8Nt7pH jf6IIk9G/Z2BNm478mThAwYUmL/jYindmkZ3u5uoUAH/piNxzOF9LcpOlsBN8/Kx axwRVftveVRvNS4oQqPisuUdjlb4SFmJG8GcoBo16m4QblTjG4doea09AkRg/gz7 c2SdYT4VRVk828k97mfTuPn5V30OWMPpE4vxA+hisAW2Y+QtsRoiLg2gbvJFUEJ5 RbujZN5QxBHRaLsoj/0FXF3DyfkaxaI2fYjpXOFaYJG9rv7iB+o= =H3+g -----END PGP SIGNATURE----- Merge tag 'clk-meson-fixes-v6.5-1' of https://github.com/BayLibre/clk-meson into clk-fixes Pull an Amlogic clk driver fix from Jerome Brunet: - Fix PLL scheduling while atomic following a1 locking sequence update * tag 'clk-meson-fixes-v6.5-1' of https://github.com/BayLibre/clk-meson: clk: meson: change usleep_range() to udelay() for atomic context
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@ -367,9 +367,9 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
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* 3. enable the lock detect module
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*/
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if (MESON_PARM_APPLICABLE(&pll->current_en)) {
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usleep_range(10, 20);
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udelay(10);
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meson_parm_write(clk->map, &pll->current_en, 1);
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usleep_range(40, 50);
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udelay(40);
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}
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if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
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