From 7e5a7e39d767b60d8631792bd3d7820a6f4a43f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:52:10 +0200 Subject: [PATCH 001/791] ARM: dts: rockchip: correct interrupt flags on rk3188 boards GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags without affecting the code: ACTIVE_HIGH => IRQ_TYPE_NONE Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200917185211.5483-1-krzk@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 85d3fce0142f..35b7a5798eee 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include +#include #include "rk3188.dtsi" / { @@ -485,7 +486,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio3>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; From 146c9a346fdd0506228cace62cf324e4c1e3705a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 31 Mar 2022 14:56:44 +0200 Subject: [PATCH 002/791] ARM: dts: rockchip: use generic node name for dma rk3036/rk322x The node names should be generic, so fix this for the rk3036 and rk322x dma node and rename it to "dma-controller". Signed-off-by: Johan Jonker Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220331125644.6841-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 2 +- arch/arm/boot/dts/rk322x.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index ba2b8891bbb7..477a8d0030c2 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -556,7 +556,7 @@ status = "disabled"; }; - pdma: pdma@20078000 { + pdma: dma-controller@20078000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20078000 0x4000>; interrupts = , diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 5868eb512f69..6513ffcaac92 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -501,7 +501,7 @@ <75000000>; }; - pdma: pdma@110f0000 { + pdma: dma-controller@110f0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x110f0000 0x4000>; interrupts = , From 2bda08dfc501967a7a7bd6f77f04afef14dc7271 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:07 +0300 Subject: [PATCH 003/791] arm64: meson: add dts bluetooth node for JetHub H1 Add bluetooth node for RTL8822CS uart to JetHub H1 dts file. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-2-adeep@lexina.in --- .../boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index 6eafb908695f..fcb304c5a40f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -213,6 +213,12 @@ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; uart-has-rtscts; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; }; &uart_C { From cf94e26508ad411c2a618b00dfaae515affd0ca7 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:08 +0300 Subject: [PATCH 004/791] arm64: meson: dts: update serial alias in dts for JetHub D1 Change zigbee serial port alias to ttyAML2 for backward compatibility. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-3-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 561eec21b4de..9951217ef997 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -18,7 +18,7 @@ model = "JetHome JetHub J100"; aliases { serial0 = &uart_AO; /* Console */ - serial1 = &uart_AO_B; /* External UART (Wireless Module) */ + serial2 = &uart_AO_B; /* External UART (Wireless Module) */ ethernet0 = ðmac; }; From 81bbd2bd24a9ebac3871b293060df50445458c79 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:09 +0300 Subject: [PATCH 005/791] arm64: meson: update SDIO voltage in dts for JetHub D1 Fix the dts to match board's reference design: - update vddio_boot regulator to 3.3v (Wi-Fi SDIO module) - add vccq_1v8 regulator with 1.8v for eMMC SDIO In the first revision of JetHub D1 the vccq_1v8 regulator was 3.3v. All installed eMMC modules were tested to work in HS200 mode at 3.3v supply voltage. In the next revisions of the board eMMC will be powered with 1.8v according to the standard. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-4-adeep@lexina.in --- .../dts/amlogic/meson-axg-jethome-jethub-j100.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 9951217ef997..1ab3cedfbee5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -81,6 +81,15 @@ vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vccq_1v8: regulator-vccq_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCCQ_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&vddao_3v3>; @@ -282,7 +291,7 @@ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; + vqmmc-supply = <&vccq_1v8>; }; /* UART Bluetooth */ From 87a87657249316616138c103c2bdb7525c34d987 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:10 +0300 Subject: [PATCH 006/791] arm64: meson: update WiFi SDIO in dts for JetHub D1 Fix the dts to match board's reference design: - update the maximum SDIO frequency to match 3.3v regulator (Wi-Fi SDIO module) Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-5-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 1ab3cedfbee5..8b0d586aa84e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -257,8 +257,7 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; + max-frequency = <50000000>; non-removable; disable-wp; From 4246d0bab2a8685e3d4aec2cb0ef8c526689ce96 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 15 Mar 2022 17:27:06 +0800 Subject: [PATCH 007/791] arm64: dts: rockchip: Move drive-impedance-ohm to emmc phy on rk3399 drive-impedance-ohm is introduced for emmc phy instead of pcie phy. Fixes: fb8b7460c995 ("arm64: dts: rockchip: Define drive-impedance-ohm for RK3399's emmc-phy.") Signed-off-by: Shawn Lin Link: https://lore.kernel.org/r/1647336426-154797-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 080457a68e3c..88f26d89eea1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1534,6 +1534,7 @@ reg = <0xf780 0x24>; clocks = <&sdhci>; clock-names = "emmcclk"; + drive-impedance-ohm = <50>; #phy-cells = <0>; status = "disabled"; }; @@ -1544,7 +1545,6 @@ clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; - drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; From 16c0f95d9ed14f033b5f1bd37e96d257b60c198c Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 11 Mar 2022 22:03:57 +0100 Subject: [PATCH 008/791] arm64: dts: rockchip: Add sata nodes to rk356x RK356x supports up to 3 sata controllers which were compatible with the existing snps,dwc-ahci binding. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220311210357.222830-7-linux@fw-web.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5b0f528d6818..3e07d9f6a2d1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,20 @@ / { compatible = "rockchip,rk3568"; + sata0: sata@fc000000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc000000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, + <&cru CLK_SATA0_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy0 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + pipe_phy_grf0: syscon@fdc70000 { compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; reg = <0x0 0xfdc70000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 7cdef800cb3c..264dd030e703 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -230,6 +230,34 @@ }; }; + sata1: sata@fc400000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, + <&cru CLK_SATA1_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata2: sata@fc800000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc800000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, + <&cru CLK_SATA2_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy2 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + gic: interrupt-controller@fd400000 { compatible = "arm,gic-v3"; reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ From a070d3b857d4961e1202754f7a86a0f796f808cd Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 15 Mar 2022 22:08:10 +0000 Subject: [PATCH 009/791] arm64: dts: rockchip: Add some pins for NanoPi4 The NanoPi4 boards have the RK808's always-on 32KHz clock wired to the SoC, so have it claim the relevant pinctrl to actually enable the CLK32K_IN input. The RK808's SLEEP pin is also wired to the SoC's AP_PWROFF output, so we may as well claim that too. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/e870284a872567f163868b77267c01b77ed6f22a.1647381986.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 8c0ff6c96e03..248ad41a976b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -267,7 +267,7 @@ interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; + pinctrl-0 = <&pmic_int_l>, <&ap_pwroff>, <&clk_32k>; rockchip,system-power-controller; wakeup-source; From 6383f5a212a6b569ff15bc98ba8b3041a35db6ee Mon Sep 17 00:00:00 2001 From: Qianggui Song Date: Thu, 10 Mar 2022 11:04:10 +0800 Subject: [PATCH 010/791] arm64: dts: meson-s4: add pinctrl node Add pinctrl node for mesonn-s4 Signed-off-by: Qianggui Song Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220310030410.718-1-qianggui.song@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index bf9ae1e1016b..e440efcf7a92 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { cpus { @@ -85,6 +86,22 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,meson-s4-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4000 { + reg = <0x0 0x4000 0x0 0x004c>, + <0x0 0x40c0 0x0 0x0220>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 82>; + }; + }; + uart_B: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; From 393633936976fb8bd2c26ae76fa8d30822bb7fee Mon Sep 17 00:00:00 2001 From: Qianggui Song Date: Thu, 10 Mar 2022 17:26:45 +0800 Subject: [PATCH 011/791] arm64: dts: meson-s4: add gpio_intc node Add gpio interrupt controller node Signed-off-by: Qianggui Song Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220310092645.4303-1-qianggui.song@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index e440efcf7a92..dcaf7d98a6f1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -102,6 +102,16 @@ }; }; + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,meson-s4-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + uart_B: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; From 085f7a298a14ed2a088c8ba01d2feda2499cbc72 Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Fri, 1 Apr 2022 19:03:06 +0800 Subject: [PATCH 012/791] arm64: dts: add support for S4 power domain controller Enable power domain controller for Meson s4 SoC Signed-off-by: Shunzhou Jiang Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220401110306.3364551-1-shunzhou.jiang@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index dcaf7d98a6f1..2e45a8ecd9a0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -61,6 +61,12 @@ #clock-cells = <0>; }; + pwrc: power-controller { + compatible = "amlogic,meson-s4-pwrc"; + #power-domain-cells = <1>; + status = "okay"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; From 8eb5092e64de30c003d8fe16a7eeacbfe29b7b84 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 24 Feb 2022 12:58:43 +0000 Subject: [PATCH 013/791] arm64: dts: renesas: r9a07g054: Fillup the ADC stub node Fillup the ADC stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220224125843.29733-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 39 +++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 5d39e765c291..3ddf0f24071c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -260,8 +260,45 @@ }; adc: adc@10059000 { + compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G054_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G054_ADC_PRESETN>, + <&cpg R9A07G054_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; }; sbc: spi@10060000 { From ffe3f135dd28295114233d2a8073b3b15774b528 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:33 +0000 Subject: [PATCH 014/791] arm64: dts: renesas: r9a07g054: Fillup the SDHI{0,1} stub nodes Fillup the SDHI{0,1} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 26 ++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 3ddf0f24071c..0b0e924e28ae 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -398,13 +398,35 @@ }; sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; eth0: ethernet@11c20000 { From b0bb96e5162368814acdc76da7fdb2cd574f58c2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:34 +0000 Subject: [PATCH 015/791] arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting gpio-hog pins related to SDHI Drop deleting gpio-hog pins related to SDHI0/1 so that SDHI functionality gets enabled on Renesas RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index fc334b4c2aa4..191ce17fbeac 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -20,7 +20,4 @@ &pinctrl { /delete-node/ can0-stb-hog; /delete-node/ can1-stb-hog; - /delete-node/ gpio-sd0-pwr-en-hog; - /delete-node/ sd0-dev-sel-hog; - /delete-node/ sd1-pwr-en-hog; }; From 791b7e1dcb9fe9f9e7f7dd1b6714cd8e0f6ee349 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:35 +0000 Subject: [PATCH 016/791] arm64: dts: renesas: r9a07g054: Fillup the CANFD stub node Fillup the CANFD stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 31 +++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0b0e924e28ae..6e89bd126788 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -234,8 +234,37 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G054_CANFD_RSTP_N>, + <&cpg R9A07G054_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { From e3ab4573761418ba1b853ec33e5db723db279ff5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:36 +0000 Subject: [PATCH 017/791] arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog nodes Drop deleting can{0,1}-stb-hog nodes so that CAN becomes operational on Renesas RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 191ce17fbeac..4e07e1a0fb66 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -16,8 +16,3 @@ model = "Renesas SMARC EVK based on r9a07g054l2"; compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; }; - -&pinctrl { - /delete-node/ can0-stb-hog; - /delete-node/ can1-stb-hog; -}; From 3f285c301cd788164fa776e1f95458c56e68a6ee Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Mar 2022 14:26:38 +0000 Subject: [PATCH 018/791] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's. SYSC controller found on the RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55 core0 reset vector address configuration register. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220315142644.17660-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index bb433e75a0ee..c31eeb66319f 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -10,8 +10,8 @@ maintainers: - Geert Uytterhoeven description: - The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI - and supports following functions, + The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of + the LSI and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -20,6 +20,7 @@ description: properties: compatible: enum: + - renesas,r9a07g043-sysc # RZ/G2UL - renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g054-sysc # RZ/V2L From e46a72e0398e570fbab5905ea6be67dc76d678f4 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:37 +0000 Subject: [PATCH 019/791] arm64: dts: renesas: r9a07g054: Fillup the I2C{0,1,2,3} stub nodes Fillup the I2C{0,1,2,3} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 73 +++++++++++++++++++++- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 6e89bd126788..fafb986fe3bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -270,22 +270,89 @@ i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { From 8d3da65c4c40d77977799f58fa6465bdc723536f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:38 +0000 Subject: [PATCH 020/791] arm64: dts: renesas: r9a07g054: Fillup the sbc stub node Fillup the sbc stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index fafb986fe3bc..1207a99bf3fe 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -398,12 +398,20 @@ }; sbc: spi@10060000 { + compatible = "renesas,r9a07g054-rpc-if", + "renesas,rzg2l-rpc-if"; reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, + <&cpg CPG_MOD R9A07G054_SPI_CLK>; + resets = <&cpg R9A07G054_SPI_RST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; }; cpg: clock-controller@11010000 { From f458b7707c9c4acabb7cdf6c0fcfde1a506b360f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:39 +0000 Subject: [PATCH 021/791] arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 24 +++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 1207a99bf3fe..50cb2f0e6e73 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -629,18 +629,36 @@ }; ostm0: timer@12801000 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; + resets = <&cpg R9A07G054_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm1: timer@12801400 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; + resets = <&cpg R9A07G054_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm2: timer@12801800 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; + resets = <&cpg R9A07G054_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; }; From f35a868bcf95c066a00dcae9e7ee42d85eaf05b2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:40 +0000 Subject: [PATCH 022/791] arm64: dts: renesas: r9a07g054: Fillup the WDT{0,1,2} stub nodes Fillup the WDT{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 50cb2f0e6e73..a3623e70f02c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -614,18 +614,48 @@ }; wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800800 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800C00 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800400 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; ostm0: timer@12801000 { From cd0339ec25895c0be45656908442bc121bbadacb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:41 +0000 Subject: [PATCH 023/791] arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 80 +++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index a3623e70f02c..e3a9f78b7fb8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -96,9 +96,87 @@ ranges; ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; #sound-dai-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; }; spi1: spi@1004b000 { From a8e2a77b644ac23319f0e7c3e8d9dcd6dc9aebd1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:42 +0000 Subject: [PATCH 024/791] arm64: dts: renesas: r9a07g054: Add USB2.0 phy and host support Add USB2.0 phy and host support to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 74 ++++++++++++++++++++-- 1 file changed, 67 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e3a9f78b7fb8..7d9ea17352a4 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -652,38 +652,98 @@ }; phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g054-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; reg = <0 0x11c40000 0 0x10000>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; + resets = <&cpg R9A07G054_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; }; ohci0: usb@11c50000 { + compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ohci1: usb@11c70000 { + compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ehci0: usb@11c50100 { + compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; }; ehci1: usb@11c70100 { + compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; hsusb: usb@11c60000 { From c9c4e5b7d202cce2f488a56c06332016380890b3 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:43 +0000 Subject: [PATCH 025/791] arm64: dts: renesas: r9a07g054: Add USB2.0 device support Fillup the hsusb stub node in RZ/V2L (R9A07G054) SoC DTSI which enables USB2.0 device support. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 7d9ea17352a4..8bbdcf48bb61 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -747,8 +747,22 @@ }; hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g054", + "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; wdt0: watchdog@12800800 { From 3f3c46d4e2cb38bfa7d1f24c2099a20229867d9d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:44 +0000 Subject: [PATCH 026/791] arm64: dts: renesas: r9a07g054: Add SPI{0,2} nodes and fillup SPI1 stub node Add SPI{0,2} nodes and fillup SPI1 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-13-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 47 ++++++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 8bbdcf48bb61..9e730171efa8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -179,11 +179,52 @@ status = "disabled"; }; - spi1: spi@1004b000 { - reg = <0 0x1004b000 0 0x400>; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; + resets = <&cpg R9A07G054_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + spi1: spi@1004b000 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; + resets = <&cpg R9A07G054_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; + resets = <&cpg R9A07G054_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; scif0: serial@1004b800 { From 1889f4798c443dfd4993ba9bbbf4ed7bf801d94b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 2 Mar 2022 07:40:43 +0000 Subject: [PATCH 027/791] arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0 Enable usb2.0 host/device functionality on RZ/G2LC SMARC EVK by deleting phyrst, usb2_phy{0,1}, ehci/ohci{0,1} and hsusb entries from board DT, so that entries from common dtsi kick in and make USB2.0 functionality operational. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220302074043.21525-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 46 ------------------- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 11 +++++ 2 files changed, 11 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 5a5cea82a5d9..d5254b16b0b3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,24 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&ehci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ehci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&hsusb { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &i2c0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; @@ -50,22 +32,6 @@ status = "disabled"; }; -&ohci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&phyrst { - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; @@ -77,15 +43,3 @@ /delete-property/ pinctrl-names; status = "disabled"; }; - -&usb2_phy0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&usb2_phy1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 37ff2091582e..5f5ec21e655c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -90,5 +90,16 @@ pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; }; + + usb0_pins: usb0 { + pinmux = , /* VBUS */ + , /* OVC */ + ; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = , /* VBUS */ + ; /* OVC */ + }; }; From a2b642d89e4beeddbfbd7be6108db2b7aaef78b6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:52 +0000 Subject: [PATCH 028/791] arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodes Sort the pinctrl nodes alphabetically. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 5f5ec21e655c..53759c3ddecb 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -12,11 +12,6 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { - pinmux = , /* TxD */ - ; /* RxD */ - }; - #if SW_SCIF_CAN /* SW8 should be at position 2->1 */ can1_pins: can1 { @@ -25,13 +20,6 @@ }; #endif - scif1_pins: scif1 { - pinmux = , /* TxD */ - , /* RxD */ - , /* CTS# */ - ; /* RTS# */ - }; - #if SW_RSPI_CAN /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ can1-stb-hog { @@ -47,6 +35,18 @@ }; #endif + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + scif1_pins: scif1 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = ; From 0a7c1c888a0c0276837f2cd7190683474a136506 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:53 +0000 Subject: [PATCH 029/791] arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from common dtsi On RZ/G2L SoM module, the Audio codec is connected to i2c3 bus whereas on RZ/G2LC, it is connected to i2c2 bus. So move out i2c3 and wm8978 nodes from common dtsi to soc specific dtsi. While at it add wm8978 node to RZ/G2LC SoC specific dtsi to fix the build error. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 15 --------------- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 11 +++++++++++ 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index d5254b16b0b3..dc39b05e9256 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -26,12 +26,6 @@ status = "disabled"; }; -&i2c3 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 588117aafaca..8dd1c69a6749 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -26,7 +26,6 @@ serial0 = &scif0; i2c0 = &i2c0; i2c1 = &i2c1; - i2c3 = &i2c3; }; chosen { @@ -131,20 +130,6 @@ status = "okay"; }; -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - &ohci0 { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 33ddfd18bd56..c934cd3633a4 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -14,6 +14,21 @@ / { aliases { serial1 = &scif2; + i2c3 = &i2c3; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; }; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index df7631fe5fac..55d3b73f84e7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -43,6 +43,7 @@ / { aliases { serial1 = &scif1; + i2c2 = &i2c2; }; }; @@ -59,6 +60,16 @@ }; #endif +&i2c2 { + status = "disabled"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated From 4fa1edc83b2b2b467ed47bd682c7beab81a38ef5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:54 +0000 Subject: [PATCH 030/791] arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2} Enable i2c{0,1} on RZ/G2LC SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable i2c2 by adding to soc dtsi. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 12 ------------ .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 6 +++++- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index dc39b05e9256..52b834205126 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,18 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&i2c0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 53759c3ddecb..1322e5bcd456 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -35,6 +35,21 @@ }; #endif + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 55d3b73f84e7..f73b4acb8f9e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -61,7 +61,11 @@ #endif &i2c2 { - status = "disabled"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; wm8978: codec@1a { compatible = "wlf,wm8978"; From 4eb6a6bb8ef31491c217167ecce2c0a26fd4f34e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:55 +0000 Subject: [PATCH 031/791] arm64: dts: renesas: rzg2lc-smarc: Enable Audio Enable Audio on RZ/G2LC SMARC EVK by deleting ssi0 entries from board DT and adding pincontrol entries to the soc-pinctrl dtsi, so that entries from common dtsi kick in and make audio functionality operational. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 52b834205126..74a2f2bade10 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -19,9 +19,3 @@ /delete-property/ pinctrl-names; status = "disabled"; }; - -&ssi0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 1322e5bcd456..d275a55333e3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -106,6 +106,13 @@ input-enable; }; + ssi0_pins: ssi0 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; + usb0_pins: usb0 { pinmux = , /* VBUS */ , /* OVC */ From 018d7b93477fbb04ba7b4bc4c355793d644e45da Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:33 +0000 Subject: [PATCH 032/791] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash Enable mt25qu512a flash connected to QSPI0. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 88a7938017aa..80c9a1146cb7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -110,6 +110,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -175,6 +187,34 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if (!SW_SD0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_pins>; From a081c4fe98f6662fbddb1597a6203be669641af1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:34 +0000 Subject: [PATCH 033/791] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM Enable OSTM{1, 2} interfaces on RZ/G2LC SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 80c9a1146cb7..05b117ac414c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -84,6 +84,14 @@ clock-frequency = <24000000>; }; +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { eth0_pins: eth0 { pinmux = , /* ET0_LINKSTA */ From 6f57895c49bc36a6ba125b9926d4b9699376e656 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:35 +0000 Subject: [PATCH 034/791] arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulator Add vdd core regulator (1.1 V) for GPU. This patch add regulator support for GPU. The H/W manual mentions nothing about a GPU regulator. So using vdd core regulator for GPU. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 05b117ac414c..959a0ad1d367 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -41,6 +41,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; @@ -84,6 +93,10 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + &ostm1 { status = "okay"; }; From 809823b853a2559d04948ea43800408f00c8db23 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:22 +0000 Subject: [PATCH 035/791] arm64: dts: renesas: r9a07g054: Fillup the GPU node Renesas RZ/V2L SoC has Mali-G31 GPU, this patch fills up the GPU node and adds opp table to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 62 +++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 9e730171efa8..e4f1defa0ff8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -83,6 +83,50 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -606,8 +650,24 @@ }; gpu: gpu@11840000 { + compatible = "renesas,r9a07g054-mali", + "arm,mali-bifrost"; reg = <0x0 0x11840000 0x0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPU_RESETN>, + <&cpg R9A07G054_GPU_AXI_RESETN>, + <&cpg R9A07G054_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; }; gic: interrupt-controller@11900000 { From 4b7e7f10835a504501a04a82498234da78c4117e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:23 +0000 Subject: [PATCH 036/791] arm64: dts: renesas: r9a07g054: Add OPP table Add OPP table for RZ/V2L SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e4f1defa0ff8..bdf0a104e82c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +92,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -74,6 +102,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From f6a2f28ab19ca5ce5bbd3a821fe19468d7c921dc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:24 +0000 Subject: [PATCH 037/791] arm64: dts: renesas: r9a07g054: Add TSU node Add TSU and thermal-zones nodes to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index bdf0a104e82c..f35aa0311e9c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -589,6 +589,16 @@ }; }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g054-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; + resets = <&cpg R9A07G054_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { compatible = "renesas,r9a07g054-rpc-if", "renesas,rzg2l-rpc-if"; @@ -974,6 +984,37 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, From 9a4259e59694136add708608fce861a1beff9635 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 9 Mar 2022 19:06:31 +0000 Subject: [PATCH 038/791] arm64: dts: renesas: falcon-cpu: Use INTC_EX for SN65DSI86 The INTC block is a better choice for handling the interrupts on the V3U as the INTC will always be powered, while the GPIO block may be de-clocked if not in use. Further more, it may be likely to have a lower power consumption as it does not need to drive the pins. Switch the interrupt parent and interrupts definition from gpio1 to irq0 on intc_ex, and configure the PFC accordingly. Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20220309190631.1576372-1-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index 6af3f4f4f268..53c4a26198e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -192,14 +192,17 @@ clock-frequency = <400000>; bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + compatible = "ti,sn65dsi86"; reg = <0x2c>; clocks = <&sn65dsi86_refclk>; clock-names = "refclk"; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; vccio-supply = <®_1p8v>; vpll-supply = <®_1p8v>; @@ -271,6 +274,11 @@ function = "i2c6"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + keys_pins: keys { pins = "GP_6_18", "GP_6_19", "GP_6_20"; bias-pull-up; From d63833b8699c585d9ed32d968563b5eba69df9f6 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 9 Mar 2022 17:26:07 +0100 Subject: [PATCH 039/791] arm64: dts: renesas: r8a779a0: Add CANFD device node This patch adds a CANFD device node for r8a779a0. Based on patch by Kazuya Mizuguchi. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20220309162609.3726306-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index c4be288b1912..c80f4584035e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -24,6 +24,13 @@ i2c6 = &i2c6; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -596,6 +603,55 @@ status = "disabled"; }; + canfd: can@e6660000 { + compatible = "renesas,r8a779a0-canfd"; + reg = <0 0xe6660000 0 0x8000>; + interrupts = , + ; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 328>, + <&cpg CPG_CORE R8A779A0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>; + assigned-clock-rates = <80000000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + + channel2 { + status = "disabled"; + }; + + channel3 { + status = "disabled"; + }; + + channel4 { + status = "disabled"; + }; + + channel5 { + status = "disabled"; + }; + + channel6 { + status = "disabled"; + }; + + channel7 { + status = "disabled"; + }; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen3"; From d2194187aa4f9a4c2df010962e4e008efc3f930b Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 9 Mar 2022 17:26:08 +0100 Subject: [PATCH 040/791] arm64: dts: renesas: falcon: Enable CANFD 0 and 1 Enables confirmed-working CAN interfaces 0 and 1 on the Falcon board. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20220309162609.3726306-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a779a0-falcon.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index e46dc9aa0a43..b2e67b82caf6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -37,6 +37,20 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + &i2c0 { eeprom@51 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -65,4 +79,14 @@ }; }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; }; From 0182581a9f63764bcbdbc68e98881b50e03fc4c4 Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Sat, 19 Mar 2022 23:33:05 +0100 Subject: [PATCH 041/791] arm64: dts: renesas: r8a77961: Add CAN-FD node Add the device node for the CAN-FD device on R-Car M3-W+. Signed-off-by: Koji Matsuoka Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220319223306.60782-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 68cbbb322acf..7d522ea5fca2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1222,6 +1222,31 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77961-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77961_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; From 33c7874b44324fe9657d19ca01ef4ae4403a5a4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Tue, 1 Mar 2022 15:31:47 -0500 Subject: [PATCH 042/791] arm64: dts: mediatek: Format mediatek,larbs as an array of phandles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas") updated the mediatek,larbs property in the mediatek,iommu.yaml dt-binding to make it clearer that the phandles passed to the property are independent, rather than subsequent arguments to the first phandle. Update the mediatek,larbs property in the arm64 Devicetrees to use the same formatting. This change doesn't impact any behavior: the compiled dtb is exactly the same. It does however fix the warnings generated by dtbs_check. Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220301203147.1143782-2-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 6 +++--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index a27b7628c5f7..86579330a8bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -329,8 +329,8 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb6>; #iommu-cells = <1>; }; @@ -346,7 +346,7 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb4 &larb5 &larb7>; + mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 9029051624a6..54655f2feb04 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -174,7 +174,7 @@ iommu: m4u@10203000 { compatible = "mediatek,mt8167-m4u"; reg = <0 0x10203000 0 0x1000>; - mediatek,larbs = <&larb0 &larb1 &larb2>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; interrupts = ; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 2b7d331a4588..042feaedda4a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -588,8 +588,8 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb4 &larb5>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb4>, <&larb5>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4b08691ed39e..5d4a1dd55adc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -682,8 +682,8 @@ compatible = "mediatek,mt8183-m4u"; reg = <0 0x10205000 0 0x1000>; interrupts = ; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 - &larb4 &larb5 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, + <&larb4>, <&larb5>, <&larb6>; #iommu-cells = <1>; }; From 261691b40128e6b76bb94d562457d8a5236cc7fa Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:13 +0800 Subject: [PATCH 043/791] arm64: dts: mt8192: Add pwrap node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pwrap node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 411feb294613..76428599444e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -523,6 +523,18 @@ clock-names = "clk13m"; }; + pwrap: pwrap@10026000 { + compatible = "mediatek,mt6873-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; From c63556ec6bfe21cde6ab2fb0b651112bc5e99e56 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:16 +0800 Subject: [PATCH 044/791] arm64: dts: mt8192: Add SCP node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SCP node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 76428599444e..4f26a398d970 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -679,6 +679,18 @@ status = "disabled"; }; + scp: scp@10500000 { + compatible = "mediatek,mt8192-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10700000 0 0x8000>, + <0 0x10720000 0 0xe0000>; + reg-names = "sram", "l1tcm", "cfg"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + status = "disabled"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; From 40de66b8bbbb6137022652954167d5c570bb93c2 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:17 +0800 Subject: [PATCH 045/791] arm64: dts: mt8192: Add usb-phy node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 4f26a398d970..946ebcb2bb5f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -848,6 +848,28 @@ #clock-cells = <1>; }; + u3phy0: t-phy@11e40000 { + compatible = "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11e40000 0x1000>; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, From e5aac2258e666cdfe7e027766b89af639cd5fb08 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:18 +0800 Subject: [PATCH 046/791] arm64: dts: mt8192: Add xhci node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 946ebcb2bb5f..be82e0766129 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -691,6 +692,29 @@ status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "host"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg CLK_INFRA_SSUSB>, + <&infracfg CLK_INFRA_SSUSB_XHCI>, + <&apmixedsys CLK_APMIXED_USBPLL>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x420 102>; + status = "disabled"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; From 27f0eb16b0d417c155e96b5d3b89074699944e09 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:22 +0800 Subject: [PATCH 047/791] arm64: dts: mt8192: Fix nor_flash status disable typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct nor_flash status disable typo of mt8192 SoC. Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node") Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-11-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index be82e0766129..a3721f442138 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -727,7 +727,7 @@ assigned-clock-parents = <&clk26m>; #address-cells = <1>; #size-cells = <0>; - status = "disable"; + status = "disabled"; }; audsys: clock-controller@11210000 { From 4d50a433d0fde2c610628a7b40a0291899861482 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:23 +0800 Subject: [PATCH 048/791] arm64: dts: mt8192: Add efuse node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add efuse node for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-12-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a3721f442138..3d51e1ef7a6f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -736,6 +736,21 @@ #clock-cells = <1>; }; + efuse: efuse@11c10000 { + compatible = "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_e_data1: data1@1c0 { + reg = <0x1c0 0x58>; + }; + + svs_calibration: calib@580 { + reg = <0x580 0x68>; + }; + }; + i2c3: i2c@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>, From 4a65b0f1bec51872b406a8f74a66c0e6e298423c Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:26 +0800 Subject: [PATCH 049/791] arm64: dts: mt8192: Add m4u and smi nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add m4u and smi nodes for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-15-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 3d51e1ef7a6f..579abbf4488e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -967,24 +968,114 @@ #clock-cells = <1>; }; + smi_common: smi@14002000 { + compatible = "mediatek,mt8192-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb0: larb@14003000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb1: larb@14004000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14004000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + iommu0: m4u@1401d000 { + compatible = "mediatek,mt8192-m4u"; + reg = <0 0x1401d000 0 0x1000>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb4>, <&larb5>, <&larb7>, + <&larb9>, <&larb11>, <&larb13>, + <&larb14>, <&larb16>, <&larb17>, + <&larb18>, <&larb19>, <&larb20>; + interrupts = ; + clocks = <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + #iommu-cells = <1>; + }; + imgsys: clock-controller@15020000 { compatible = "mediatek,mt8192-imgsys"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; + larb9: larb@1502e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1502e000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; + }; + imgsys2: clock-controller@15820000 { compatible = "mediatek,mt8192-imgsys2"; reg = <0 0x15820000 0 0x1000>; #clock-cells = <1>; }; + larb11: larb@1582e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1582e000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_LARB11>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; + }; + + larb5: larb@1600d000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1600d000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + vdecsys_soc: clock-controller@1600f000 { compatible = "mediatek,mt8192-vdecsys_soc"; reg = <0 0x1600f000 0 0x1000>; #clock-cells = <1>; }; + larb4: larb@1602e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1602e000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + vdecsys: clock-controller@1602f000 { compatible = "mediatek,mt8192-vdecsys"; reg = <0 0x1602f000 0 0x1000>; @@ -997,12 +1088,78 @@ #clock-cells = <1>; }; + larb7: larb@17010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_SET0_LARB>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + larb13: larb@1a001000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB13>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb14: larb@1a002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb16: larb@1a00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a00f000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@1a010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; + }; + + larb18: larb@1a011000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a011000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_CAM>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible = "mediatek,mt8192-camsys_rawa"; reg = <0 0x1a04f000 0 0x1000>; @@ -1027,10 +1184,43 @@ #clock-cells = <1>; }; + larb20: larb@1b00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b00f000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB20>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + larb19: larb@1b10f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b10f000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB19>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + mdpsys: clock-controller@1f000000 { compatible = "mediatek,mt8192-mdpsys"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; }; + + larb2: larb@1f002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1f002000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common>; + clocks = <&mdpsys CLK_MDP_SMI0>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; + }; }; }; From 19c66219e4d5b813ebbd28621cfe9c450659ded7 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:31 +0800 Subject: [PATCH 050/791] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220318144534.17996-20-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- include/dt-bindings/reset/mt8192-resets.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index be9a7ca245b9..764ca9910fa9 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -27,4 +27,7 @@ #define MT8192_TOPRGU_SW_RST_NUM 23 +/* MMSYS resets */ +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ From 7663f7a26b335a53102a0893824689182ac64e42 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Wed, 16 Feb 2022 19:31:29 +0800 Subject: [PATCH 051/791] dt-bindings: arm: mediatek: Add mt8195 pericfg compatible Add mt8195 pericfg compatible to binding document. Signed-off-by: Tinghan Shen Acked-by: Rob Herring Acked-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220216113131.13145-2-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- .../devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 8723dfe34bab..611f666f359d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon - items: From b2edd51979d2861e75a9b20ac0e566e9a0770d81 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:29 +0800 Subject: [PATCH 052/791] arm64: dts: mt8192: Add dpi node Add dpi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-18-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 579abbf4488e..c6439a010e06 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -999,6 +999,17 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + dpi0: dpi@14016000 { + compatible = "mediatek,mt8192-dpi"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + iommu0: m4u@1401d000 { compatible = "mediatek,mt8192-m4u"; reg = <0 0x1401d000 0 0x1000>; From e530d080932d0db52071c9bec20d60b4a3d9035c Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Wed, 30 Mar 2022 21:38:13 +0800 Subject: [PATCH 053/791] arm64: dts: mt8192: Add PCIe node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PCIe node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220330133816.30806-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c6439a010e06..0d32df382f10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -716,6 +716,41 @@ status = "disabled"; }; + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + reg = <0 0x11230000 0 0x2000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, + <&infracfg CLK_INFRA_PCIE_TL_26M>, + <&infracfg CLK_INFRA_PCIE_TL_96M>, + <&infracfg CLK_INFRA_PCIE_TL_32K>, + <&infracfg CLK_INFRA_PCIE_PERI_26M>, + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "top_133m"; + assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; From aa8f3711fc87f7d9b8edee6f09e44b3f9113f081 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Wed, 30 Mar 2022 21:38:15 +0800 Subject: [PATCH 054/791] arm64: dts: mt8192: Add H264 venc device node Adds H264 venc node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220330133816.30806-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 0d32df382f10..a6da7b04b9d4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1145,6 +1145,29 @@ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; }; + vcodec_enc: vcodec@17020000 { + compatible = "mediatek,mt8192-vcodec-enc"; + reg = <0 0x17020000 0 0x2000>; + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, + <&iommu0 M4U_PORT_L7_VENC_REC>, + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; + interrupts = ; + mediatek,scp = <&scp>; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc-set1"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0 0x1a000000 0 0x1000>; From c1ed0f41032f54e47c03088f096f8b37cae40d8e Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:23 +0100 Subject: [PATCH 055/791] ARM: dts: exynos: fix ethernet node name for different odroid boards The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20220216074927.3619425-6-o.rempel@pengutronix.de Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 2 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index efaf7533e84f..5ddbb6cbe1bf 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -119,7 +119,7 @@ phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; - ethernet: usbether@2 { + ethernet: ethernet@2 { compatible = "usb0424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index a9fada51eb50..eb063f24b2bb 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -81,7 +81,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb0424,ec00"; reg = <1>; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index e54a3391854d..c1715123bea0 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -655,7 +655,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@2 { + ethernet: ethernet@2 { compatible = "usb0424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 62c5928aa994..749f051ffe70 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -118,7 +118,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb0424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index cecaeb69e623..8cf3d644a4c1 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -85,7 +85,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb0424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ From 2e33a7b5fdb3930a9b1051bc792dbdc6a7490aae Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:24 +0100 Subject: [PATCH 056/791] ARM: dts: exynos: fix compatible strings for Ethernet USB devices Fix compatible string for Ethernet USB device as required by USB device schema: Documentation/devicetree/bindings/usb/usb-device.yaml The textual representation of VID and PID shall be in lower case hexadecimal with leading zeroes suppressed. Since there are no kernel driver matching against this compatibles, I expect no regressions with this patch. At the same time, without this fix, we are not be able to validate this device nodes with newly provided DT schema. Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20220216074927.3619425-7-o.rempel@pengutronix.de Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 2 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 6 +++--- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 4 ++-- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 5ddbb6cbe1bf..36c369c42b77 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -120,7 +120,7 @@ phy-names = "hsic0", "hsic1"; ethernet: ethernet@2 { - compatible = "usb0424,9730"; + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index eb063f24b2bb..1f17cc30ed14 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -70,19 +70,19 @@ phy-names = "hsic0"; hub@2 { - compatible = "usb0424,3503"; + compatible = "usb424,3503"; reg = <2>; #address-cells = <1>; #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: ethernet@1 { - compatible = "usb0424,ec00"; + compatible = "usb424,ec00"; reg = <1>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index c1715123bea0..d1cbc6b8a570 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -656,7 +656,7 @@ #size-cells = <0>; ethernet: ethernet@2 { - compatible = "usb0424,9730"; + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 749f051ffe70..e3154a1cae23 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -113,13 +113,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: ethernet@1 { - compatible = "usb0424,ec00"; + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 8cf3d644a4c1..a378d4937ff7 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -80,13 +80,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: ethernet@1 { - compatible = "usb0424,ec00"; + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; From c3d3727c8531ba78fc725995ce34cf948ebf1dae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:46:08 +0200 Subject: [PATCH 057/791] ARM: dts: exynos: remove deprecated unit address for LPDDR3 timings on Odroid Passing maximum frequency of LPDDR3 memory timings as unit address was deprecated in favor of 'max-freq' property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20220206135918.211990-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 2f65dcf6ba73..35818c4cd852 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -333,8 +333,6 @@ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; tRFC-min-tck = <17>; tRRD-min-tck = <2>; @@ -358,10 +356,9 @@ tCKESR-min-tck = <2>; tMRD-min-tck = <5>; - timings_samsung_K3QF2F20DB_800mhz: timings@800000000 { + timings_samsung_K3QF2F20DB_800mhz: timings { compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; + max-freq = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>; From aa8ea8cc95dec8bc7370773271e133c1b3cc864a Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:22 +0100 Subject: [PATCH 058/791] ARM: dts: bcm283x: fix ethernet node name It should be "ethernet@x" instead of "usbether@x" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi | 2 +- arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi index 967e081cb9c2..882b13807075 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi index dc7ae776db5f..4273b90b53cc 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi @@ -11,7 +11,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; From f4324583cd4d4979ff2e885a44b8335eb4c4bfa3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:47:40 +0200 Subject: [PATCH 059/791] arm64: dts: exynos: move aliases to board in Exynos850 The aliases for typical blocks which are disabled by default in DTSI (like I2C, UART and MMC) should be defined in the board DTS. The board should add aliases only for enabled blocks according to its specific order. On Exynos850, move aliases of enabled blocks to E850-96 board and remove unused ones. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220221075219.10827-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos850-e850-96.dts | 5 +++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 16 ---------------- 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index 7b5a61d22cc5..f52a55f644f7 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -20,6 +20,11 @@ model = "WinLink E850-96 board"; compatible = "winlink,e850-96", "samsung,exynos850"; + aliases { + mmc0 = &mmc_0; + serial0 = &serial_0; + }; + chosen { stdout-path = &serial_0; }; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d1700e96fee2..1c6d8fdf453c 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -29,22 +29,6 @@ pinctrl3 = &pinctrl_hsi; pinctrl4 = &pinctrl_core; pinctrl5 = &pinctrl_peri; - mmc0 = &mmc_0; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &hsi2c_0; - i2c8 = &hsi2c_1; - i2c9 = &hsi2c_2; - i2c10 = &hsi2c_3; - i2c11 = &hsi2c_4; }; arm-pmu { From cca50a59f60a6b2b5aa2c90d8c173da89f567ee3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:51:20 +0200 Subject: [PATCH 060/791] ARM: dts: exynos: add a specific compatible to MCT One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos3250 and all Exynos5 SoCs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-3-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos3250.dtsi | 3 ++- arch/arm/boot/dts/exynos5250.dtsi | 3 ++- arch/arm/boot/dts/exynos5260.dtsi | 3 ++- arch/arm/boot/dts/exynos54xx.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index ae644315855d..41bb421e67c2 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -269,7 +269,8 @@ }; timer@10050000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos3250-mct", + "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupts = , , diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 5baaa7eb71a4..63d1dcf2c55c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -245,7 +245,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5250-mct", + "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 56271e7c4587..ff1ee409eff3 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -333,7 +333,8 @@ }; mct: timer@100b0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5260-mct", + "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 2ddb7a5f12b3..3ec43761d8b9 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -74,7 +74,8 @@ }; mct: timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5420-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0xb00>; interrupts-extended = <&combiner 23 3>, <&combiner 23 4>, From 2616922241706ec5c2c5ae95d5ac1d3120575ded Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:52:55 +0200 Subject: [PATCH 061/791] arm64: dts: exynos: add a specific compatible to MCT One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos5433 and Exynos850. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-4-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 ++- arch/arm64/boot/dts/exynos/exynos850.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 661567d2dd7a..017ccc2f4650 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -806,7 +806,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; interrupts = , , diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 1c6d8fdf453c..9076afd4bb3e 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -165,7 +165,8 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; reg = <0x10040000 0x800>; interrupts = , , From 22cbcb8f4a17c194d208f686fc3ea37fc860bd71 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:53:08 +0200 Subject: [PATCH 062/791] arm64: dts: tesla: add a specific compatible to MCT on FSD One compatible is used for the Multi-Core Timer on Tesla FSD SoC, which is correct but not specific enough. The MCT blocks have different number of interrupts, so add a second specific compatible to Tesla FSD. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-5-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 9a652abcbcac..10c217a57a7d 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -727,7 +727,7 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; reg = <0x0 0x10040000 0x0 0x800>; interrupts = , , From 04398e04173f1be0b21d7cd50c54e8affcebe106 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:54:46 +0200 Subject: [PATCH 063/791] ARM: dts: exynos: drop deprecated SFR region from MIPI phy Commit e4b3d38088df ("phy: exynos-video-mipi: Fix regression by adding support for PMU regmap") deprecated the usage of unit address in MIPI phy node, in favor of a syscon phandle. Deprecating was a correct approach because that unit address was actually coming from Power Management Unit SFR range so its usage here caused overlapped memory mapping. In 2016 commit 26dbadba495f ("phy: exynos-mipi-video: Drop support for direct access to PMU") fully removed support for parsing that MIPI phy unit address (SFR range) but the address stayed in Exynos5250 DTSI for compatibility reasons. Remove that deprecated unit address from Exynos5250 MIPI phy, because it has been almost 6 years since it was deprecated and it causes now DT schema validation warnings: video-phy@10040710: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Any out-of-tree users of Exynos5250 DTSI, should update their code to use newer syscon property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220314184113.251013-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5250.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 63d1dcf2c55c..df80ddfada2d 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -818,15 +818,14 @@ status = "disabled"; }; - dp_phy: video-phy { + dp_phy: video-phy-0 { compatible = "samsung,exynos5250-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; - mipi_phy: video-phy@10040710 { + mipi_phy: video-phy-1 { compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10040710 0x100>; #phy-cells = <1>; syscon = <&pmu_system_controller>; }; From b412be7d3c0a248db0de4b7b53ee6ad44d49c71b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:55:19 +0200 Subject: [PATCH 064/791] ARM: dts: exynos: align EHCI/OHCI nodes with dtschema on Exynos4 The node names should be generic and USB DT schema expects "usb" names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220314181948.246434-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e81b3ee4e0f7..5fd17bc52321 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -373,7 +373,7 @@ status = "disabled"; }; - ehci: ehci@12580000 { + ehci: usb@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; interrupts = ; @@ -384,7 +384,7 @@ phy-names = "host", "hsic0", "hsic1"; }; - ohci: ohci@12590000 { + ohci: usb@12590000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; interrupts = ; From ab92681ca16194c966844ed4dd2c336705e0c727 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:55:46 +0200 Subject: [PATCH 065/791] ARM: dts: s5pv210: align EHCI/OHCI nodes with dtschema The node names should be generic and USB DT schema expects "usb" names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220314181948.246434-2-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/s5pv210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 353ba7b09a0c..a7aca54832d9 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -427,7 +427,7 @@ status = "disabled"; }; - ehci: ehci@ec200000 { + ehci: usb@ec200000 { compatible = "samsung,exynos4210-ehci"; reg = <0xec200000 0x100>; interrupts = <23>; @@ -444,7 +444,7 @@ }; }; - ohci: ohci@ec300000 { + ohci: usb@ec300000 { compatible = "samsung,exynos4210-ohci"; reg = <0xec300000 0x100>; interrupts = <23>; From 061d09499fd1fcf793291009d9a21899c4fb871f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:56:11 +0200 Subject: [PATCH 066/791] ARM: dts: s5pv210: Use standard arrays of generic PHYs for EHCI/OHCI device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move USB PHYs to a standard arrays for S5PV210 EHCI/OHCI devices. This resolves the conflict between S5PV210 EHCI/OHCI sub-nodes and generic USB device bindings. Suggested-by: Måns Rullgård Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220314181948.246434-3-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/s5pv210.dtsi | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index a7aca54832d9..4ea1e638432a 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -434,14 +434,9 @@ interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; ohci: usb@ec300000 { @@ -451,14 +446,9 @@ interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; mfc: codec@f1700000 { From a14a56a3dd6bb45aa7c0ef1a665839656f2bcce3 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 11 Mar 2022 14:11:14 +0530 Subject: [PATCH 067/791] ARM: dts: bcm-cygnus: Update spi clock properties PL022 binding require two clocks to be defined but broadcom cygnus platform doesn't comply with bindings and define only one clock. Update spi clocks and clocks-names property by adding appropriate clock reference to make it compliant with bindings. CC: Florian Fainelli Signed-off-by: Kuldeep Singh Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index ad65be871938..f9f79ed82518 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -397,8 +397,8 @@ #size-cells = <0>; interrupts = ; pinctrl-0 = <&spi_0>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -409,8 +409,8 @@ #size-cells = <0>; interrupts = ; pinctrl-0 = <&spi_1>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -421,8 +421,8 @@ #size-cells = <0>; interrupts = ; pinctrl-0 = <&spi_2>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; From 130b5e32ba9d2d2313e39cf3f6d0729bff02b76a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 30 Mar 2022 14:05:27 +0200 Subject: [PATCH 068/791] ARM: dts: BCM5301X: Update pin controller node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: cru-bus@100: 'pin-controller@1c0' does not match any of the regexes: '^clock-controller@[a-f0-9]+$', '^phy@[a-f0-9]+$', '^pinctrl@[a-f0-9]+$', '^syscon@[a-f0-9]+$', '^thermal@[a-f0-9]+$' From schema: Documentation/devicetree/bindings/mfd/brcm,cru.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pin-controller@1c0: $nodename:0: 'pin-controller@1c0' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' From schema: Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml Ref: e7391b021e3f ("dt-bindings: mfd: brcm,cru: Rename pinctrl node") Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 603c700c706f..65f8a759f1e3 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -455,7 +455,7 @@ reg = <0x180 0x4>; }; - pinctrl: pin-controller@1c0 { + pinctrl: pinctrl@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; reg-names = "cru_gpio_control"; From 90103611d573c5c238350f9b1d7cb682c62f5681 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:19:58 +0300 Subject: [PATCH 069/791] ARM: dts: BCM5301X: Fix DTC warning for NAND node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary #address-cells and #size-cells properties on the nand@0 node to fix the warning below. Warning (avoid_unnecessary_addr_size): /nand-controller@18028000/nand@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Arınç ÜNAL Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi index be9a00ff752d..bdf1b4a608e6 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -10,8 +10,6 @@ nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "brcm,bcm947xx-cfe-partitions"; From e5ff0a7aab3ef5dd8ec7636b936c95179aa5ddfa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:19:59 +0300 Subject: [PATCH 070/791] ARM: dts: BCM5301X: Remove cell properties from srab ports on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove #address-cells and #size-cells properties from the ports node of &srab. They are already defined on bcm5301x.dtsi, there's no need to define them again. Signed-off-by: Arınç ÜNAL Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 82f9629f0abb..cf793c558437 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright (C) 2021 Arınç ÜNAL + * Copyright (C) 2021-2022 Arınç ÜNAL */ /dts-v1/; @@ -177,9 +177,6 @@ dsa,member = <0 0>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; From 4b7a67420a34ebd8fbf0111221a8bfd8001d418d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:20:00 +0300 Subject: [PATCH 071/791] ARM: dts: BCM5301X: Add rgmii to port@5 of Broadcom switch on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define phy-mode of the Broadcom switch's port@5 as rgmii. This doesn't seem to matter but let's explicitly define it since phy-mode as rgmii is defined on the other side which is port@6 of the Realtek switch. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index cf793c558437..5696dd5fbaf4 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -205,6 +205,7 @@ sw0_p5: port@5 { reg = <5>; label = "extsw"; + phy-mode = "rgmii"; fixed-link { speed = <1000>; From 7f7f8c7b9f3cbae1355fb3b0ce4ea9d6f1552521 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 1 Apr 2022 13:20:01 +0300 Subject: [PATCH 072/791] ARM: dts: BCM5301X: Retrieve gmac1 MAC address from NVRAM on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The et1macaddr NVRAM variable contains a MAC address for gmac1 on Asus RT-AC88U. Add NVMEM cell for it and reference it in the gmac1 node. Signed-off-by: Arınç ÜNAL Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 5696dd5fbaf4..2f944d1c0330 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -25,6 +25,9 @@ nvram@1c080000 { compatible = "brcm,nvram"; reg = <0x1c080000 0x00180000>; + + et1macaddr: et1macaddr { + }; }; leds { @@ -239,6 +242,11 @@ }; }; +&gmac1 { + nvmem-cells = <&et1macaddr>; + nvmem-cell-names = "mac-address"; +}; + &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; From e403fff3b848107e2da92b9a567a926aa5943f7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:19 +0300 Subject: [PATCH 073/791] dt-bindings: arm: bcm: fix BCM53012 and BCM53016 SoC strings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix inaccurate SoC strings brcm,brcm53012 and brcm,brcm53016 to respectively brcm,bcm53012 and brcm,bcm53016. Fixes: 4cb5201fcb5d ("dt-bindings: arm: bcm: Convert BCM4708 to YAML") Fixes: a2e385f5374d ("dt-bindings: ARM: add bindings for the Meraki MR32") Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 434d3c6db61e..f0e2a20d22d5 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -84,8 +84,8 @@ properties: - brcm,bcm953012hr - brcm,bcm953012k - meraki,mr32 - - const: brcm,brcm53012 - - const: brcm,brcm53016 + - const: brcm,bcm53012 + - const: brcm,bcm53016 - const: brcm,bcm4708 additionalProperties: true From ca41a8b302601b2547ea8aac4306efd8356d85a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:20 +0300 Subject: [PATCH 074/791] dt-bindings: arm: bcm: create new description for BCM53016 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create a new description for BCM53016 and move Meraki MR32 under it. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- .../devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index f0e2a20d22d5..8a97ee048053 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -83,8 +83,13 @@ properties: - brcm,bcm953012er - brcm,bcm953012hr - brcm,bcm953012k - - meraki,mr32 - const: brcm,bcm53012 + - const: brcm,bcm4708 + + - description: BCM53016 based boards + items: + - enum: + - meraki,mr32 - const: brcm,bcm53016 - const: brcm,bcm4708 From 69bb5c6f3f41fe6baa86a775c8a3e69dd27f85d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:21 +0300 Subject: [PATCH 075/791] ARM: dts: BCM5301X: Fix compatible strings for BCM53012 and BCM53016 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix compatible strings for devicetrees using the BCM53012 and BCM53016 SoC. Signed-off-by: Arınç ÜNAL Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +- arch/arm/boot/dts/bcm953012er.dts | 2 +- arch/arm/boot/dts/bcm953012hr.dts | 2 +- arch/arm/boot/dts/bcm953012k.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 66c64a6ec414..daca63f25134 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -13,7 +13,7 @@ #include / { - compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; + compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708"; model = "Meraki MR32"; chosen { diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 52feca0fb906..dd63a148a16b 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -37,7 +37,7 @@ / { model = "NorthStar Enterprise Router (BCM953012ER)"; - compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708"; memory@0 { device_type = "memory"; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 9140be7ec053..b070b69466bd 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -37,7 +37,7 @@ / { model = "NorthStar HR (BCM953012HR)"; - compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index de40bd59a5fa..f1e6bcaa1edd 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -36,7 +36,7 @@ / { model = "NorthStar SVK (BCM953012K)"; - compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708"; aliases { serial0 = &uart0; From 0346e33d558c3372a5f8138ad8086f9414177a06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 2 Apr 2022 23:46:22 +0300 Subject: [PATCH 076/791] dt-bindings: arm: bcm: add bindings for Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Asus RT-AC88U under BCM47094 based boards. Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 8a97ee048053..8b7e87fb6c34 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -64,6 +64,7 @@ properties: - description: BCM47094 based boards items: - enum: + - asus,rt-ac88u - dlink,dir-885l - linksys,panamera - luxul,abr-4500-v1 From 4db7a4d7efe5cd249967e8867bf227ec5d9edb8e Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sat, 12 Mar 2022 17:08:53 +0530 Subject: [PATCH 077/791] ARM: dts: ste-dbx: Update spi clock-names property Now that spi pl022 binding only accept "sspclk" as clock name, ST ericsson platform with "SSPCLK" clock name start raising dtbs_check warnings. Make necessary changes to update this property in order to make it compliant with binding. clock-names:0: 'sspclk' was expected Signed-off-by: Kuldeep Singh Link: https://lore.kernel.org/r/20220312113853.63446-5-singh.kuldeep87k@gmail.com Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index dc0bcc7020f1..c28b32640254 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -755,7 +755,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -772,7 +772,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -790,7 +790,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ <&dma 0 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -807,7 +807,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ <&dma 35 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -824,7 +824,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ <&dma 33 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -841,7 +841,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; From 1034eb1a6ab812b5c20063a0002de0b3b7f1d9ce Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 23 Feb 2022 00:33:12 +0100 Subject: [PATCH 078/791] dt-bindings: arm: ux500: Document Codina-TMO This is a U8500-based phone named Samsung Galaxy Exhibit or Samsung SGH-T599, codenamed "Codina TMO" as it was made for T-Mobile. Cc: phone-devel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220222233313.1774416-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/ux500.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ux500.yaml b/Documentation/devicetree/bindings/arm/ux500.yaml index a46193ad94e0..17accb31bca0 100644 --- a/Documentation/devicetree/bindings/arm/ux500.yaml +++ b/Documentation/devicetree/bindings/arm/ux500.yaml @@ -40,6 +40,11 @@ properties: - const: samsung,codina - const: st-ericsson,u8500 + - description: Samsung Galaxy Exhibit (SGH-T599) + items: + - const: samsung,codina-tmo + - const: st-ericsson,u8500 + - description: Samsung Galaxy Beam (GT-I8530) items: - const: samsung,gavini From 8388234ec562d77128ab9dbc6d26dff0c7b13af0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 23 Feb 2022 00:33:13 +0100 Subject: [PATCH 079/791] ARM: dts: ux500: Add Codina TMO device tree This adds a device tree for "Codina TMO" also known as Samsung Galaxy Exhibit or Samsung SGH-T599. It is quite different from the vanilla Codina despite sharing the same board file in the vendor tree. Fix up some comments in the Codina DTS while we're at it. Cc: phone-devel@vger.kernel.org Cc: Markuss Broks Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20220222233313.1774416-2-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/ste-ux500-samsung-codina-tmo.dts | 781 ++++++++++++++++++ .../arm/boot/dts/ste-ux500-samsung-codina.dts | 8 +- 3 files changed, 788 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..fdec7b7bf26d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1382,6 +1382,7 @@ dtb-$(CONFIG_ARCH_U8500) += \ ste-ux500-samsung-janice.dtb \ ste-ux500-samsung-gavini.dtb \ ste-ux500-samsung-codina.dtb \ + ste-ux500-samsung-codina-tmo.dtb \ ste-ux500-samsung-skomer.dtb \ ste-ux500-samsung-kyle.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts new file mode 100644 index 000000000000..80ae6ad05985 --- /dev/null +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO, + * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively + * for T-Mobile in the United States. + * + * This phone is closely related to the Codina, but has: + * - No CPU speed cap, full ~1GHz rate + * - Different power management IC, AB8505 + * - As AB8505 has a micro USB phy, no TI TSU6111 + * - Different power routing such as the removal of the external LDO for the + * touchscreen in favor of using the AB8505 + * - Using a regulator for the key backlight LED + * - Using the Samsung S6D27A1 panel by default + * - The panel is using one of the ordinary AB8505 regulators for 1.8V + * - WiFi/Bluetooth combi chip upgraded to BCM4334 + * - GPIO for backlight control moved from 68 to 69 + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung Galaxy Exhibit (SGH-T599)"; + compatible = "samsung,codina-tmo", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb425161lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both the 3.0V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + vibrator { + compatible = "gpio-vibrator"; + /* GPIO195 "MOT_EN" */ + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = ; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = ; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = ; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + led-touchkeys { + compatible = "regulator-led"; + vled-supply = <&ab8500_ldo_aux4_reg>; // 3.3V + default-state = "on"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* GPIO69 is used on Codina R0.4 and Codina TMO */ + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&ktd253_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* TODO: this should also be used by the SM5103 Camera power management unit */ + }; + + /* Bit-banged I2C on GPIO151 and GPIO152 also called "COMP I2C" */ + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + clock-frequency = <400000>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + dvdd-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + }; + }; + + spi-gpio-0 { + compatible = "spi-gpio"; + /* Clock on GPIO220, pin SCL */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MOSI on GPIO224, pin SDI "slave data in" */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* MISO on GPIO225, pin SDO "slave data out" */ + miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO201 */ + cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6d27a1"; + spi-max-frequency = <1200000>; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&ab8500_ldo_aux6_reg>; + + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + backlight = <&ktd253>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator is using AUX3 at 2.9 V as well */ + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + /* + * GPIO130 will be set to input no pull-up resulting in a resistor + * pulling the reset high and taking the memory out of reset. + */ + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + /* FIXME: convert to interrupt */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + uart@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + /* CTS/RTS is not used, CTS is repurposed as GPIO */ + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + /* FIXME: add a device for the GPS here */ + }; + + /* Debugging console UART connected to AB8505 */ + uart@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + /* This is mostly identical to the Codina v0.4 regulators */ + regulator { + ab8500_ldo_aux1 { + regulator-name = "v-sensors-vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + regulator-name = "v-aux2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + regulator-name = "v-mmc-sd"; + }; + + ab8500_ldo_aux4 { + regulator-name = "v-aux4"; + /* + * Providing some span here makes the touchkey + * LEDs actually dimmable. + */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "v-aux5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux6 { + /* 1.8 V to the display */ + regulator-name = "v-aux6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + regulator-name = "v-sensors-vio"; + }; + }; + }; + }; + + /* I2C0 also known as "AGC I2C" */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@39 { + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; + clock-frequency = <400000>; + reg = <0x39>; + + /* IRQ on GPIO146 "PS_INT" */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tmd2672_codina_default>; + }; + }; + + /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + /* Bosch BMA254 accelerometer */ + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + vddio-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* TODO: write bindings and driver for this touchscreen */ + + /* Zinitix BT404 ISP part */ + isp@50 { + compatible = "zinitix,bt404-isp"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + + /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ + touchscreen@20 { + compatible = "zinitix,bt404"; + reg = <0x20>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + vcca-supply = <&ab8500_ldo_aux2_reg>; // 3.3V + vdd-supply = <&ab8500_ldo_aux5_reg>; // 1.8V + zinitix,mode = <2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + sdi2 { + /* + * GPIO130 should be set in GPIO mode and + * pulled down. (Not connected.) + */ + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + codina_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + codina_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIOs for panel control */ + panel { + panel_default_mode: panel_default { + codina_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + codina_cfg2 { + /* ESD IRQ line "LCD detect" */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + codina_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + codina_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Backlight GPIO */ + backlight { + ktd253_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + codina_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Zinitix BT404 touchscreen */ + tsp { + tsp_default: tsp_default { + codina_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for light/proximity sensor TMD2672 */ + tmd2672 { + tmd2672_codina_default: tmd2672_codina { + codina_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for subpmu */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + codina_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the NFC */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + codina_cfg1 { + pins = "GPIO151_D17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0_d { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + codina_cfg2 { + pins = "GPIO225_AG8"; + /* Needs pull down, no pull down resistor on board */ + ste,config = <&gpio_in_pd>; + }; + }; + spi_gpio_0_sleep: spi_gpio_0_s { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", + "GPIO224_AG9", "GPIO225_AG8"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + codina_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + codina_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + codina_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 1c1725d31c7c..8284560a7bab 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -9,9 +9,13 @@ * the boot loader. * * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China). - * The GT-I8160 plain is knonw as the "europe" variant. - * The GT-I8160P appears to not use the ST Microelectronics accelerometer. + * The GT-I8160 plain is known as the "europe" variant. + * The GT-I8160P is the CDMA version and it appears to not use the ST + * Microelectronics accelerometer and reportedly has NFC mounted. * The GT-I8160chn appears to be the same as the europe variant. + * + * There is also the Codina-TMO, Samsung SGH-T599, which has its own device + * tree. */ /dts-v1/; From 003cac14f543cc3475255f10cfd6fa150c5c0e3e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 16 Feb 2022 00:46:27 +0100 Subject: [PATCH 080/791] ARM: dts: ux500: Register Amstaos proximity sensor The proximity sensor on the Codina is actually an Amstaos TMD2672, not Mouser, so alter the DTS to reflect this. Tested successfully with the IIO driver. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-codina.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 8284560a7bab..e6ea63d23d26 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -519,10 +519,9 @@ pinctrl-0 = <&i2c0_a_1_default>; pinctrl-1 = <&i2c0_a_1_sleep>; - /* TODO: write bindings and driver for this proximity sensor */ proximity@39 { - /* Codina has the Mouser TMD2672 */ - compatible = "mouser,tmd2672"; + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; clock-frequency = <400000>; reg = <0x39>; From 5c7502397e0ccd5fa9dd762223ed29641355947b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 26 Feb 2022 02:29:48 +0100 Subject: [PATCH 081/791] ARM: dts: ux500: Add line impedance to fuel gauge The line impedance is used to improve battery capacity estimation. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-codina.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-gavini.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-kyle.dts | 4 ++++ arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 4 ++++ 7 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts index 80ae6ad05985..d6940e0afa86 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -410,6 +410,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + /* This is mostly identical to the Codina v0.4 regulators */ regulator { ab8500_ldo_aux1 { diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index e6ea63d23d26..acbe43269c38 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -487,6 +487,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index fd170974765f..53062d50e455 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -456,6 +456,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <43000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 290ab59e863d..b0dce91aff4b 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -304,6 +304,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { regulator-name = "sensor_3v"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index 42762bfcd878..16f61d8acf4c 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -504,6 +504,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <15000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index 2a5bf54137ce..c57676faf181 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -325,6 +325,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index dcb03ce7cbd4..dcdec867f24d 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -305,6 +305,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <16000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ From 330e01653ac13e2e51896e3843e4969017b6d28f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 5 Mar 2022 00:37:37 +0100 Subject: [PATCH 082/791] ARM: dts: ux500: Add GPS to Janice device tree This adds the CSR GSD4t GPS to the Janice device tree. Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-janice.dts | 40 ++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index 16f61d8acf4c..e6d4fd0eb5f4 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -485,7 +485,26 @@ /* CTS/RTS is not used, CTS is repurposed as GPIO */ pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ + + gnss { + /* + * The Low Noise Amplifier (LNA) power and enablement is controlled + * autonomously by the GSD4t. + * Janice has a SiRFstarIV-based GSD4t + * Golden has a SiRFstarV 5t-based CSRG05TA03-ICJE-R. + */ + compatible = "csr,gsd4t"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO96 */ + sirf,onoff-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gsd4t_janice_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ @@ -945,4 +964,23 @@ }; }; }; + gsd4t { + gsd4t_janice_default: gsd4t_janice { + /* Reset line, start out asserted */ + janice_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + janice_cfg2 { + pins = "GPIO96_D8"; + ste,config = <&gpio_out_lo>; + }; + /* Unused power enablement line, used in R0.0 and R0.1 boards */ + janice_cfg3 { + pins = "GPIO86_C6"; + ste,config = <&gpio_in_pd>; + }; + }; + }; }; From 973a9ba5fe489bcb323cc4f4e9ece3959dd50686 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 5 Mar 2022 00:36:03 +0100 Subject: [PATCH 083/791] ARM: dts: ux500: Add GPS to Skomer device tree Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-skomer.dts | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index dcdec867f24d..81b341a5ae45 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -281,12 +281,27 @@ }; }; - /* GPF UART */ + /* GPS UART */ uart@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_skomer_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to AB8505 USB */ @@ -653,6 +668,20 @@ }; }; }; + g05ta03 { + g05ta03_skomer_default: g05ta03 { + /* Reset line, start out de-asserted */ + skomer_cfg1 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + skomer_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; &ab8505_gpio { From 236b8cfac4e3f007b9c4f014b3d25e63cc376ef7 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Wed, 23 Mar 2022 10:56:01 -0300 Subject: [PATCH 084/791] arm64: dts: imx8mn-bsh-smm-s2pro: Add tlv320aic31xx audio card node BSH SystemMaster (SMM) S2 PRO board comes with an audio card based on tlv320aic31xx family codec. The audio card exposes two playback devices, one of them using the EASRC (Enhanced Asynchronous Sample Rate Converter) module. Note that this would require SDMA and EASRC firmware in order to work. Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mn-bsh-smm-s2pro.dts | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts index c6a8ed6745c1..fbbb3367037b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "imx8mn-bsh-smm-s2-common.dtsi" +#include / { model = "BSH SMM S2 PRO"; @@ -16,6 +17,65 @@ device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; + + sound-tlv320aic31xx { + compatible = "fsl,imx-audio-tlv320aic31xx"; + model = "tlv320aic31xx-hifi"; + audio-cpu = <&sai3>; + audio-codec = <&tlv320dac3101>; + audio-asrc = <&easrc>; + audio-routing = + "Ext Spk", "SPL", + "Ext Spk", "SPR"; + mclk-id = ; + }; + + vdd_input: vdd_input { + compatible = "regulator-fixed"; + regulator-name = "vdd_input"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + fsl,asrc-format = <10>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tlv320dac3101: audio-codec@18 { + compatible = "ti,tlv320dac3101"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dac_rst>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <&buck4_reg>; + SPRVDD-supply = <&vdd_input>; + SPLVDD-supply = <&vdd_input>; + AVDD-supply = <&buck4_reg>; + IOVDD-supply = <&buck4_reg>; + DVDD-supply = <&buck5_reg>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + ai31xx-micbias-vg = ; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; }; /* eMMC */ @@ -30,6 +90,36 @@ }; &iomuxc { + pinctrl_dac_rst: dacrstgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */ + >; + }; + + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 + MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 From 583f24ae42a0786dbb70fde03a3652059811a9c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Feb 2022 01:17:38 +0100 Subject: [PATCH 085/791] arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC Add support for Data Modul i.MX8M Mini eDM SBC board. This is an evaluation board for various custom display units. Currently supported are serial console, ethernet, eMMC, SD, PCIe, SPI NOR, USB host and USB OTG. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mm-data-modul-edm-sbc.dts | 996 ++++++++++++++++++ 2 files changed, 997 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7f51b537df40..52ce0f798657 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts new file mode 100644 index 000000000000..154116d01c94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -0,0 +1,996 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Marek Vasut + */ + +/dts-v1/; + +#include +#include +#include "imx8mm.dtsi" + +/ { + model = "Data Modul i.MX8M Mini eDM SBC"; + compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm"; + + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + /* There are 1/2/4 GiB options, adjusted by bootloader. */ + reg = <0x0 0x40000000 0 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_backlight>; + brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 5000000>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + panel: panel { + backlight = <&backlight>; + power-supply = <®_panel_vcc>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_panel_vcc: regulator-panel-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_vcc_reg>; + regulator-name = "PANEL_VCC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 6 0>; + enable-active-high; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 0>; + enable-active-high; + }; + + watchdog-gpio { + /* TPS3813 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_watchdog_gpio>; + compatible = "linux,wdt-gpio"; + always-enabled; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + hw_algo = "level"; + /* Reset triggers in 2..3 seconds */ + hw_margin_ms = <1500>; + /* Disabled by default */ + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { /* W25Q128FVSI */ + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&ecspi2 { /* Feature connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless feature board plugged in. */ + status = "disabled"; +}; + +&ecspi3 { /* Display connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&fec1_phy>; + phy-supply = <&buck4_reg>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8031 PHY */ + fec1_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + /* + * Dedicated ENET_WOL# signal is unused, the PHY + * can wake the SoC up via INT signal as well. + */ + interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + qca,keep-pll-enabled; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "ENET_RST#", "WDOG_B#", "PMIC_INT#", + "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#", + "WDOG_KICK#", "M2-B_PCIE_CLKREQ#", + "USB1_OTG_ID_3V3", "ENET_WOL#", + "", "", "", "ENET_INT#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#", + "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#", + "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#", + "MEMCFG0", "WDOG_EN", + "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#", + "", "", "", "", + "", "", "", "SD2_RESET#", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", + "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", + "CSI_PD_1V8", "CSI_RESET_1V8#", "", "", + "", "", "", "", + "", "", "", "M2-B_WAKE_WWAN_1V8#", + "M2-B_RESET_1V8#", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "NC0", "NC1", "BOOTCFG0", "BOOTCFG1", + "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5", + "BOOTCFG6", "BOOTCFG7", "NC10", "NC11", + "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11", + "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15", + "NC20", "", "", "", + "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27", + "DIS_USB_DN2", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03", + "GPIO5_IO04", "", "", "", + "", "SPI1_CS#", "", "", + "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", + "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", + "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "", + "", "SPI3_CS#", "", "", "", "", "", ""; +}; + +&i2c1 { + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + rohm,reset-snvs-powered; + + /* + * i.MX 8M Mini Data Sheet for Consumer Products + * 3.1.3 Operating ranges + * MIMX8MM4DVTLZAA + */ + regulators { + /* VDD_SOC */ + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <950000>; + }; + + /* VDD_DRAM, BUCK5 */ + buck3_reg: BUCK3 { + regulator-name = "buck3"; + /* 1.5 GHz DDR bus clock */ + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 3V3_VDD, BUCK6 */ + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_VDD, BUCK7 */ + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V1_NVCC_DRAM, BUCK8 */ + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_NVCC_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 0V8_VDD_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_VDDA */ + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 0V9_VDD_PHY */ + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V2_VDD_PHY */ + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + usb-hub@2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + compatible = "microchip,usb2514bi"; + reg = <0x2c>; + individual-port-switching; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + self-powered; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "st,m41t62"; + reg = <0x68>; + interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pcieclk: clk@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&i2c3 { /* Display connector I2C */ + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { /* Feature connector I2C */ + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, + <&pinctrl_panel_expansion>; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40 + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + /* ENET_RST# */ + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6 + /* ENET_WOL# */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090 + /* ENET_INT# */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090 + >; + }; + + pinctrl_hog_feature: hog-feature-grp { + fsl,pins = < + /* GPIO4_IO27 */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006 + /* GPIO5_IO03 */ + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006 + /* GPIO5_IO04 */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006 + + /* CAN_INT# */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090 + /* CAN_RST# */ + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26 + >; + }; + + pinctrl_hog_panel: hog-panel-grp { + fsl,pins = < + /* GRAPHICS_GPIO0_1V8 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26 + >; + }; + + pinctrl_hog_misc: hog-misc-grp { + fsl,pins = < + /* PG_V_IN_VAR# */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000 + /* CSI_PD_1V8 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0 + /* CSI_RESET_1V8# */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0 + + /* DIS_USB_DN1 */ + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0 + /* DIS_USB_DN2 */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0 + + /* EEPROM_WP_1V8# */ + MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100 + /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 + /* GRAPHICS_PRSNT_1V8# */ + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000 + + /* CLK_CCM_CLKO1_3V3 */ + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10 + >; + }; + + pinctrl_hog_sbc: hog-sbc-grp { + fsl,pins = < + /* MEMCFG[0..2] straps */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140 + MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140 + MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140 + + /* BOOT_CFG[0..15] straps */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000 + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000 + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000 + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000 + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000 + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000 + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000 + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000 + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000 + + /* Not connected pins */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0 + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0 + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0 + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84 + >; + }; + + pinctrl_panel_backlight: panel-backlight-grp { + fsl,pins = < + /* BL_ENABLE_1V8 */ + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104 + >; + }; + + pinctrl_panel_expansion: panel-expansion-grp { + fsl,pins = < + /* DSI_RESET_1V8# */ + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2 + /* DSI_IRQ_1V8# */ + MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090 + >; + }; + + pinctrl_panel_vcc_reg: panel-vcc-grp { + fsl,pins = < + /* TFT_ENABLE_1V8 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104 + >; + }; + + pinctrl_panel_pwm: panel-pwm-grp { + fsl,pins = < + /* BL_PWM_3V3 */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12 + >; + }; + + pinctrl_pcie0: pcie-grp { + fsl,pins = < + /* M2-B_RESET_1V8# */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102 + /* M2-B_PCIE_RST# */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2 + /* M2-B_FULL_CARD_PWROFF_1V8# */ + MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102 + /* M2-B_W_DISABLE1_WWAN_1V8# */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102 + /* M2-B_W_DISABLE2_GPS_1V8# */ + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102 + /* CLK_M2_32K768 */ + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14 + /* M2-B_WAKE_WWAN_1V8# */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140 + /* M2-B_PCIE_WAKE# */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140 + /* M2-B_PCIE_CLKREQ# */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140 + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + /* RTC_IRQ# */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090 + >; + }; + + pinctrl_sai5: sai5-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40 + >; + }; + + pinctrl_usb_hub: usb-hub-grp { + fsl,pins = < + /* USBHUB_RESET# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4 + >; + }; + + pinctrl_usb_otg1: usb-otg1-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000 + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090 + >; + }; + + pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_watchdog_gpio: watchdog-gpio-grp { + fsl,pins = < + /* WDOG_B# */ + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26 + /* WDOG_EN -- ungate WDT RESET# signal propagation */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6 + /* WDOG_KICK# / WDI */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26 + >; + }; +}; + +&pcie_phy { + fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */ + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + clocks = <&pcieclk 0>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcieclk 0>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_pwm>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + fsl,sai-mclk-direction-output; + /* Input into codec PLL */ + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22579200>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&uart3 { /* A53 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { /* M4 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + /* UART4 is reserved for CM and RDC blocks CA access to UART4. */ + status = "disabled"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { /* MicroSD */ + assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vcc>; + status = "okay"; +}; + +&usdhc3 { /* eMMC */ + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + vmmc-supply = <&buck4_reg>; + vqmmc-supply = <&buck5_reg>; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; From e931a6f79620c2cc0e9dde215e35f016a3be33f4 Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:05 +0100 Subject: [PATCH 086/791] ARM: dts: imx6qdl-vicut1/vicutgo: Set default backlight brightness to maximum Recover default behavior of the device and set maximal brightness Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 227c952543d4..e6134efbfabd 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -28,7 +28,7 @@ pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; - default-brightness-level = <1>; + default-brightness-level = <48>; power-supply = <®_3v3>; enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 1ac7e13249d2..c1d06bc28c67 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -23,7 +23,7 @@ pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; - default-brightness-level = <1>; + default-brightness-level = <48>; power-supply = <®_3v3>; enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; From 156a722b39315e95dd018dbc614e2becf4782237 Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:06 +0100 Subject: [PATCH 087/791] ARM: dts: imx6qdl-vicut1/vicutgo: Rename backlight to backlight_lcd We have two backlight sources on this boards. Use more specific name for the LCD backlight to see the difference. Signed-off-by: David Jander Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 4 ++-- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index e6134efbfabd..833340c30537 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -21,7 +21,7 @@ stdout-path = &uart4; }; - backlight: backlight { + backlight_lcd: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; @@ -100,7 +100,7 @@ panel { compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; + backlight = <&backlight_lcd>; power-supply = <®_3v3>; port { diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index c1d06bc28c67..a1fbbc9c26b6 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -16,7 +16,7 @@ stdout-path = &uart4; }; - backlight: backlight { + backlight_lcd: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; @@ -102,7 +102,7 @@ panel { compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; + backlight = <&backlight_lcd>; power-supply = <®_3v3>; port { From 98efa526a0c436efea4cdc834ab632f66f13ac0b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:07 +0100 Subject: [PATCH 088/791] ARM: dts: imx6qdl-vicut1/vicutgo: Add backlight_led node backlight_led is the dimmable backlight for the rubber border on the case. It is also used to highlight the power- and some other buttons. MX6QDL_PAD_SD4_DAT1__PWM3_OUT is also assigned as output for pwm3. Since we need pwm3 for the backlight, we're forced to disable user space hardware revision detection. The bootloader will have to supply this information (i.e. through device tree). Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 24 +++++++++---------- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 33 +++++++++++++++++---------- 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 833340c30537..d542ddad4e32 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -33,6 +33,15 @@ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -392,8 +401,8 @@ &gpio2 { gpio-line-names = "", "", "", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "LED_PWM", "", "", "", + "", "", "", "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", "POWER_LED", "", "", "", "", "", "", ""; }; @@ -778,17 +787,6 @@ /* ITU656_nPDN */ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 is shared with PWM3 */ - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - /* New in HW revision 1 */ /* ON1_FB */ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index a1fbbc9c26b6..2f6b263eea66 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -28,6 +28,15 @@ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -448,6 +457,12 @@ status = "okay"; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &ssi1 { #sound-dai-cells = <0>; fsl,mode = "ac97-slave"; @@ -669,18 +684,6 @@ /* ITU656_nPDN */ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - /* New in HW revision 1 */ /* ON1_FB */ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 @@ -738,6 +741,12 @@ >; }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + >; + }; + /* YaCO AUX Uart */ pinctrl_uart1: uart1grp { fsl,pins = < From cb15ebbc10b5d35af76f34f18b1592abc39c3f5b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:08 +0100 Subject: [PATCH 089/791] ARM: dts: imx6qdl-vicut1: update gpio-line-names for some GPIOs countedX lines have different board names (YACO_x). And REV_ and BOARD_ pins have multiple functions. So, use names exposed to the OS. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 2f6b263eea66..ec39008c0950 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -277,9 +277,9 @@ &gpio2 { gpio-line-names = - "count0", "count1", "count2", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", + "", "LED_PWM", "", "", "", + "", "", "", "", "", "", "", "", "", "", "ON_SWITCH", "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; }; @@ -298,8 +298,10 @@ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "", - "", "", "", "", "BL_EN", "BL_PWM", "", ""; + "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "ON1_CTRL", + "ON2_CTRL", "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; }; &gpio5 { From 05ed0bc09a5377825b37240c0212a894aa4dad49 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Mon, 21 Feb 2022 10:53:10 +0100 Subject: [PATCH 090/791] ARM: dts: imx6dl-victgo: Add interrupt-counter nodes Interrupt counter is mainlined, now we can add missing counter nodes. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 41 ++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index d542ddad4e32..3d6dc1b2c5e9 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -54,6 +54,27 @@ }; }; + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -400,7 +421,7 @@ &gpio2 { gpio-line-names = - "", "", "", "", "", "", "", "", + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", "", "LED_PWM", "", "", "", "", "", "", "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", @@ -708,6 +729,24 @@ >; }; + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 From e310ba3c0fd5d9d017831501e81dad7e5a9aa2d7 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Mon, 21 Feb 2022 10:53:11 +0100 Subject: [PATCH 091/791] ARM: dts: imx6dl-victgo: The TGO uses a lg,lb070wv8 compatible 7" display This series of devices is using lg,lb070wv8 instead of kyo,tcg121xglp. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 3d6dc1b2c5e9..7a29283da245 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -129,7 +129,7 @@ }; panel { - compatible = "kyo,tcg121xglp"; + compatible = "lg,lb070wv8"; backlight = <&backlight_lcd>; power-supply = <®_3v3>; From 7bb9b9e34b8742afc0cd8547103ef0106012947b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:12 +0100 Subject: [PATCH 092/791] ARM: dts: imx6qdl-victgo: add CAN termination support The gpio1 0 pin is controlling CAN termination, not USB H1 VBUS. So, remove wrong regulator and assign this gpio to new DT CAN termination property. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 7a29283da245..7dd7fb165432 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -160,15 +160,6 @@ regulator-max-microvolt = <3300000>; }; - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; regulator-name = "otg-vbus"; @@ -312,6 +303,8 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; status = "okay"; }; @@ -648,7 +641,6 @@ }; &usbh1 { - vbus-supply = <®_h1_vbus>; pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; From 1c6add99c2bf1b19175e80826534b025c967afdd Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:27 +0100 Subject: [PATCH 093/791] arm64: dts: imx8mm-kontron: fix ethernet node name The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Acked-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index d40caf14ac4a..23be1ec538ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -182,7 +182,7 @@ #address-cells = <1>; #size-cells = <0>; - usbnet: usbether@1 { + usbnet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; local-mac-address = [ 00 00 00 00 00 00 ]; From 7b8861d8e6279a27873b85e3786fba8706fde7c9 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:42 +0100 Subject: [PATCH 094/791] ARM: dts: imx6ul: add TQ-Systems MBa6ULx device trees Add device trees for the MBa6ULx mainboard with TQMa6ULx SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi | 211 +++++++ arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts | 55 ++ arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi | 37 ++ arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts | 15 + arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi | 71 +++ arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi | 43 ++ arch/arm/boot/dts/mba6ulx.dtsi | 571 ++++++++++++++++++ 8 files changed, 1005 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi create mode 100644 arch/arm/boot/dts/mba6ulx.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..c76742cfe5b1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -690,6 +690,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-kontron-n6310-s.dtb \ imx6ul-kontron-n6310-s-43.dtb \ imx6ul-liteboard.dtb \ + imx6ul-tqma6ul1-mba6ulx.dtb \ + imx6ul-tqma6ul2-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi new file mode 100644 index 000000000000..eca94ed6451b --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULxL + * - TQMa6ULLx + * - TQMa6ULLxL + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + reg_sw1a: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-ramp-delay = <6250>; + /* not used */ + }; + + reg_sw1b_core: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + reg_sw2: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sw3_ddr: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_swbst: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + /* not used */ + }; + + reg_snvs_3v0: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vccsd: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + + reg_v33_3v3: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vldo1_3v3: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo2: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vldo3: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo4: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + jc42_1a: eeprom-temperature-sensor@1a { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + m24c02_52: eeprom@52 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + read-only; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + /* + * PMIC & temperature sensor IRQ + * Both do currently not use IRQ + * potentially dangerous if used on baseboard + */ + pmic-int-hog { + gpio-hog; + gpios = <24 0>; + input; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <33000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz" , "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + + bus-width = <8>; + disable-wp; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_recovery: i2c4recoverygrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0 + >; + }; + + pinctrl_pmic: pmic { + fsl,pins = < + /* PMIC irq */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts new file mode 100644 index 000000000000..f2a5f17f312e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul1.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) + * and need to be disabled here again + */ +&can2 { + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&fec2 { + /delete-property/ phy-handle; + /delete-node/ mdio; +}; + +&iomuxc { + pinctrl_enet1_mdc: enet1mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi new file mode 100644 index 000000000000..24192d012ef7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul-tqma6ul2.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM"; + compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * There are no module specific differences compared to TQMa6UL2, + * only external interfaces differ + */ + +/* + * Devices not available on i.MX6ULG1 and should not be enabled on + * mainboard level (again) + */ +&can2 { + status = "disabled"; +}; + +&csi { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts new file mode 100644 index 000000000000..0757df2b8f48 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi new file mode 100644 index 000000000000..e2e95dd92263 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2 SoM"; + compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi new file mode 100644 index 000000000000..5afb9046c202 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULLx + */ + +&m24c64_50 { + vcc-supply = <®_sw2>; +}; + +&m24c02_52 { + vcc-supply = <®_sw2>; +}; + +®_sw2 { + regulator-boot-on; + regulator-always-on; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_sw2>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi new file mode 100644 index 000000000000..fc38e185a51e --- /dev/null +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + model = "TQ-Systems MBA6ULx Baseboard"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + rtc0 = &rtc0; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <®_mba6ul_3v3>; + enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + beeper: beeper { + compatible = "gpio-beeper"; + gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buttons>; + + button1 { + label = "s14"; + linux,code = ; + gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s6"; + linux,code = ; + gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s7"; + linux,code = ; + gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; + }; + + power-button { + label = "POWER"; + linux,code = ; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + led1 { + label = "led1"; + gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "lcd-pwr"; + gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_mba6ul_3v3: regulator-mba6ul-3v3 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_mba6ul_5v0: regulator-mba6ul-5v0 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_mpcie: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mpcie-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <500000>; + vin-supply = <®_mba6ul_3v3>; + }; + + reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { + compatible = "regulator-fixed"; + gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "otg2-vbus-supply-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_mpcie>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <768000000>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + reg = <0>; + max-speed = <100>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + reg = <1>; + max-speed = <100>; + }; + }; +}; + +&i2c4 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + ldoin-supply = <®_mba6ul_3v3>; + iov-supply = <®_mba6ul_3v3>; + }; + + jc42: temperature-sensor@19 { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander_out0: gpio-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + expander_in0: gpio-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander_in0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + enet1_int-hog { + gpio-hog; + gpios = <6 0>; + input; + }; + + enet2_int-hog { + gpio-hog; + gpios = <7 0>; + input; + }; + }; + + expander_out1: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + analog_touch: touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio4>; + interrupt-controller; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,ave-ctrl = <3>; /* 8 sample average control */ + st,fraction-z = <7>; /* 7 length fractional part in z */ + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + st,settling = <3>; /* 1 ms panel driver settling time */ + st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24000000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart6dte>; */ + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* otg-port */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + power-active-high; + over-current-active-low; + /* we implement only dual role but not a fully featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* 7-port usb hub */ +/* id, pwr, oc pins not connected */ +&usbotg2 { + disable-over-current; + vbus-supply = <®_otg2vbus_5v0>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_mba6ul_3v3>; + vqmmc-supply = <®_vccsd>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_buttons: buttonsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 + MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + >; + }; + + pinctrl_enet2_mdc: enet2mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_expander_in0: expanderin0grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6dte: uart6dte { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 + MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 + >; + }; +}; From a333f3e46d76ecbe1cb8337fade76ee0d8514a8a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:43 +0100 Subject: [PATCH 095/791] ARM: dts: imx6ul: add TQ-Systems MBa6ULxL device trees Add device trees for the MBa6ULx mainboard with TQMa6ULxL SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi | 71 +++++++++++++++++++ .../arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi | 48 +++++++++++++ 4 files changed, 135 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c76742cfe5b1..e991232ae943 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -692,6 +692,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-tqma6ul1-mba6ulx.dtb \ imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 000000000000..9d9b6b744a1c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi new file mode 100644 index 000000000000..caf2c5d03f7e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2L SoM"; + compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi new file mode 100644 index 000000000000..ba84a4f70ebd --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULxL + * - TQMa6ULLxL + */ + +/ { + reg_vin: reg-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&m24c64_50 { + vcc-supply = <®_vin>; +}; + +&m24c02_52 { + vcc-supply = <®_vin>; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_vin>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; From 05c44ed0b776170fdf031080463cb5abd62cbed8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:44 +0100 Subject: [PATCH 096/791] ARM: dts: imx6ull: add TQ-Systems MBa6ULLx device trees Add device trees for the MBa6ULx mainboard with TQMa6ULLx SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e991232ae943..df272d658031 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -713,6 +713,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 000000000000..e593b7036fc7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi new file mode 100644 index 000000000000..326e6da91ed4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM"; + compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; From cbff1ae6bf3b9ecf0f4bf6afc509ce4b9aa70191 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:45 +0100 Subject: [PATCH 097/791] ARM: dts: imx6ull: add TQ-Systems MBa6ULLxL device trees Add device trees for the MBa6ULx mainboard with TQMa6ULLxL SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index df272d658031..aec4196d56fc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -714,6 +714,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 000000000000..33437aae9822 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi new file mode 100644 index 000000000000..8e4d5cd18614 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM"; + compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; From 0b08af343ab0b2dc53f34e7b2c7b98562b60cc93 Mon Sep 17 00:00:00 2001 From: Alexander Bauer Date: Tue, 22 Feb 2022 10:16:05 +0100 Subject: [PATCH 098/791] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or NAND. Supported features: * eMMC/NAND * i2c RTC * i2c TEMP * PMIC * PWM * debug UART * CAN * SD card * 2x 1Gbit Ethernet * RS232/RS485 * USB 2.0 Host * TPM * SPI-NOR Signed-off-by: Alexander Bauer Signed-off-by: Jens Lang Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 588 ++++++++++++++++++ 4 files changed, 630 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index aec4196d56fc..252353fb4e3b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -713,6 +713,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ + imx6ull-phytec-tauri-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts new file mode 100644 index 000000000000..14adb87da911 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* EMMC-Version */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts new file mode 100644 index 000000000000..ae396ac63443 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* NAND-Version */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi new file mode 100644 index 000000000000..5464a52a1f94 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" + +/ { + + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key { + label = "KEY-A"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_s25fl064_hold: regulator-s25fl064-hold { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_s25fl064_hold>; + compatible = "regulator-fixed"; + regulator-name = "s25fl064_hold"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vbus: regulator-hub-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_hub_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>, + <&pinctrl_user_leds_snvs>; + + user-led1 { + label = "yellow"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + user-led2 { + label = "red"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, + <&pinctrl_ecspi1_cs>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, + <&gpio3 10 GPIO_ACTIVE_LOW>, + <&gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm_tis: tpm@1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + compatible = "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; + + s25fl064: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = " jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <40000000>; + m25p,fast-read; + status = "disabled"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + dmas = <&sdma 7 8 0>, + <&sdma 8 8 0>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp102: tmp@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "okay"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 * RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* UART5 * RS232 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_hub_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&iomuxc_snvs { + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 + >; + }; + + pinctrl_user_leds_snvs: user_ledsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; +}; + +&iomuxc { + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 + >; + }; + + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 + >; + }; + + princtrl_flexcan2_en: flexcan2engrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 + >; + }; + + pinctrl_s25fl064_hold: s25fl064holdgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 + >; + }; +}; From 8bcbcbba9109d6e26029c089826b708164a2cb12 Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 22 Feb 2022 10:16:06 +0100 Subject: [PATCH 099/791] ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm Instead of changing default pwm-cells property, use the default "#pwm-cells = <3>" and add the third option. Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index 7cda6944501d..6ce534a896ef 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -11,7 +11,7 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <5>; power-supply = <®_backlight_en>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; status = "disabled"; }; @@ -91,7 +91,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; From 1cfa1e68af8d40ab233d5d27bc8446e4c5107571 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 24 Feb 2022 11:30:29 +0100 Subject: [PATCH 100/791] arm64: dts: imx8mn-evk: use proper names for PMIC outputs Use the power signal names as given in the schematics of the reference board. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index b4225cfcb6d9..2b685c0c7eeb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -41,7 +41,7 @@ regulators { buck1: BUCK1{ - regulator-name = "BUCK1"; + regulator-name = "VDD_SOC"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; @@ -50,7 +50,7 @@ }; buck2: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "VDD_ARM_0V9"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; @@ -61,7 +61,7 @@ }; buck4: BUCK4{ - regulator-name = "BUCK4"; + regulator-name = "VDD_3V3"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -69,7 +69,7 @@ }; buck5: BUCK5{ - regulator-name = "BUCK5"; + regulator-name = "VDD_1V8"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -77,7 +77,7 @@ }; buck6: BUCK6 { - regulator-name = "BUCK6"; + regulator-name = "NVCC_DRAM_1V1"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -85,7 +85,7 @@ }; ldo1: LDO1 { - regulator-name = "LDO1"; + regulator-name = "NVCC_SNVS_1V8"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -93,7 +93,7 @@ }; ldo2: LDO2 { - regulator-name = "LDO2"; + regulator-name = "VDD_SNVS_0V8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1150000>; regulator-boot-on; @@ -101,7 +101,7 @@ }; ldo3: LDO3 { - regulator-name = "LDO3"; + regulator-name = "VDDA_1V8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -109,7 +109,7 @@ }; ldo4: LDO4 { - regulator-name = "LDO4"; + regulator-name = "VDD_PHY_1V2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -117,7 +117,7 @@ }; ldo5: LDO5 { - regulator-name = "LDO5"; + regulator-name = "NVCC_SD2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; From bc046b952a5494b0dc53be28779460cee1214a3f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 24 Feb 2022 11:30:30 +0100 Subject: [PATCH 101/791] arm64: dts: imx8mn-evk: fix the min/max voltages of the PMIC Use the proper voltages as supported by the board instead of the ones supported by the PMIC. The voltages were taken from both the schematic of the 8MNANOLPD4-EVK eval board and the datasheet of the IMX8MN SoC. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 34 ++++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 2b685c0c7eeb..4eb467df5ba7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -42,8 +42,8 @@ regulators { buck1: BUCK1{ regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -51,8 +51,8 @@ buck2: BUCK2 { regulator-name = "VDD_ARM_0V9"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -62,32 +62,32 @@ buck4: BUCK4{ regulator-name = "VDD_3V3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; buck5: BUCK5{ regulator-name = "VDD_1V8"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; buck6: BUCK6 { regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; ldo1: LDO1 { regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -95,23 +95,23 @@ ldo2: LDO2 { regulator-name = "VDD_SNVS_0V8"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <800000>; regulator-boot-on; regulator-always-on; }; ldo3: LDO3 { regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo4: LDO4 { regulator-name = "VDD_PHY_1V2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-boot-on; regulator-always-on; }; From 7ac853ba789d1d9fb22b05f4ebd3a37fd1bb11c1 Mon Sep 17 00:00:00 2001 From: Aniruddha Rao Date: Wed, 16 Mar 2022 15:14:45 +0530 Subject: [PATCH 102/791] arm64: tegra: Update SDMMC1/3 clock source for Tegra194 The default parent for SDMMC1/3 clock sources can provide maximum frequency of 136MHz for SDR104 mode. Update parent clock source for SDMMC1/SDMMC3 instances to increase the output clock frequency to 195MHz and improve the perf. Signed-off-by: Aniruddha Rao Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 751ebe5e9506..1d6be5774fac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -934,6 +934,11 @@ clocks = <&bpmp TEGRA194_CLK_SDMMC1>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, + <&bpmp TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4_MUXED>, + <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, @@ -968,6 +973,11 @@ clocks = <&bpmp TEGRA194_CLK_SDMMC3>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, + <&bpmp TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4_MUXED>, + <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, From 5472b7df7c795352f73e9dfa68c6e5eb5db7fac8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 25 Feb 2022 17:00:01 +0800 Subject: [PATCH 103/791] arm64: dts: imx8mq: add hdmi phy 27m clock The i.MX8MQ PLL support hdmi phy 27m as pll reference clock, so add a fixed clock for it. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5b3e849f554d..1eca2b431467 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -63,6 +63,13 @@ clock-output-names = "osc_27m"; }; + hdmi_phy_27m: clock-hdmi-phy-27m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "hdmi_phy_27m"; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; From 71f69ffa0129bf04205edf0e7dc73dc4777b2588 Mon Sep 17 00:00:00 2001 From: Ashish Singhal Date: Wed, 9 Mar 2022 00:00:26 +0530 Subject: [PATCH 104/791] arm64: tegra: Add QSPI controllers on Tegra234 This adds the QSPI controllers on the Tegra234 SoC and populates the SPI NOR flash device for the Jetson AGX Orin platform. Signed-off-by: Ashish Singhal Signed-off-by: Jon Hunter Signed-off-by: Krishna Yarlagadda Reviewed-by: Jon Hunter Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 12 ++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 28 +++++++++++++++++++ include/dt-bindings/clock/tegra234-clock.h | 8 ++++++ include/dt-bindings/reset/tegra234-reset.h | 2 ++ 4 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d95a542c0bca..798de9226ba5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -7,6 +7,18 @@ compatible = "nvidia,p3701-0000", "nvidia,tegra234"; bus@0 { + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + mmc@3460000 { status = "okay"; bus-width = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace605bdaa..448512af7dea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -654,6 +654,20 @@ reset-names = "i2c"; }; + spi@3270000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3270000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI0_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI0>; + reset-names = "qspi"; + status = "disabled"; + }; + pwm1: pwm@3280000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; @@ -666,6 +680,20 @@ #pwm-cells = <2>; }; + spi@3300000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3300000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI1_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI1>; + reset-names = "qspi"; + status = "disabled"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8cae969e8cba..bd4c3086a2da 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -140,6 +140,14 @@ #define TEGRA234_CLK_PEX2_C9_CORE 173U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ +#define TEGRA234_CLK_QSPI0_2X_PM 192U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ +#define TEGRA234_CLK_QSPI1_2X_PM 193U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ +#define TEGRA234_CLK_QSPI0_PM 194U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ +#define TEGRA234_CLK_QSPI1_PM 195U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 1362cd5e03f0..547ca3b60caa 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -40,6 +40,8 @@ #define TEGRA234_RESET_PWM6 73U #define TEGRA234_RESET_PWM7 74U #define TEGRA234_RESET_PWM8 75U +#define TEGRA234_RESET_QSPI0 76U +#define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U From 6d41e13041a306f85ad6cbeb3d532f35cc5cc90a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:38 +0000 Subject: [PATCH 105/791] dt-bindings: watchdog: sunxi: fix F1C100s compatible The F1C100 series actually features a newer generation watchdog IP, so the compatible string was wrong. Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-2-andre.przywara@arm.com --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 43afa24513b9..7a26cde0afdd 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -26,10 +26,8 @@ properties: - allwinner,sun50i-h616-wdt - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset + - allwinner,suniv-f1c100s-wdt - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,suniv-f1c100s-wdt - - const: allwinner,sun4i-a10-wdt - const: allwinner,sun20i-d1-wdt - items: - const: allwinner,sun20i-d1-wdt-reset From 42b91bb160815d82d36cc1cfe28f1edd9079d912 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:39 +0000 Subject: [PATCH 106/791] dt-bindings: watchdog: sunxi: clarify clock support Most Allwinner SoCs have just one input clock to drive the watchdog peripheral. So far this is the 24 MHz "HOSC" oscillator, divided down internally to 32 KHz. The F1C100 series watchdog however uses the unchanged 32 KHz "LOSC" as its only clock input, which has the same effect, but let's the binding description mismatch. Change the binding description to name the clocks more loosely, so both the LOSC and divided HOSC match the description. As the fixed clock names now make less sense, drop them from SoCs supporting just one clock input, they were not used by any DT anyway. For the newer SoCs, supporting a choice of two input clocks, we keep both the description and clock-names requirement. Signed-off-by: Andre Przywara Reviewed-by: Guenter Roeck Reviewed-by: Samuel Holland Reviewed-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-3-andre.przywara@arm.com --- .../watchdog/allwinner,sun4i-a10-wdt.yaml | 20 ++++++++----------- 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 7a26cde0afdd..cbcf19f51411 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -39,14 +39,8 @@ properties: clocks: minItems: 1 items: - - description: High-frequency oscillator input, divided internally - - description: Low-frequency oscillator input, only found on some variants - - clock-names: - minItems: 1 - items: - - const: hosc - - const: losc + - description: 32 KHz input clock + - description: secondary clock source interrupts: maxItems: 1 @@ -71,9 +65,14 @@ then: properties: clocks: minItems: 2 + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input clock-names: - minItems: 2 + items: + - const: hosc + - const: losc required: - clock-names @@ -83,9 +82,6 @@ else: clocks: maxItems: 1 - clock-names: - maxItems: 1 - unevaluatedProperties: false examples: From 01a850ee61cbf0ab77dcbf26bb133fec2dd640d6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:40 +0000 Subject: [PATCH 107/791] ARM: dts: suniv: F1C100: fix watchdog compatible The F1C100 series of SoCs actually have their watchdog IP being compatible with the newer Allwinner generation, not the older one. The currently described sun4i-a10-wdt actually does not work, neither the watchdog functionality (just never fires), nor the reset part (reboot hangs). Replace the compatible string with the one used by the newer generation. Verified to work with both the watchdog and reboot functionality on a LicheePi Nano. Also add the missing interrupt line and clock source, to make it binding compliant. Fixes: 4ba16d17efdd ("ARM: dts: suniv: add initial DTSI file for F1C100s") Signed-off-by: Andre Przywara Acked-by: Guenter Roeck Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-4-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 6100d3b75f61..def830101448 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -104,8 +104,10 @@ wdt: watchdog@1c20ca0 { compatible = "allwinner,suniv-f1c100s-wdt", - "allwinner,sun4i-a10-wdt"; + "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; + interrupts = <16>; + clocks = <&osc32k>; }; uart0: serial@1c25000 { From fb2dcdd7c44652add88ac518c67b208e5133a7a9 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:41 +0000 Subject: [PATCH 108/791] dt-bindings: arm: sunxi: document LicheePi Nano name The top level LicheePi Nano compatible name was never documented in the bindings, so add the currently used string. As for the manufacturer name, Samuel reports: ========== From what I can tell, "Lichee Pi Nano" [1][2] is the original board, and the "Sipeed Lichee Nano" [3] is a newer batch by some of the same people [4]. Other than the silkscreen and the addition of the resistive touchscreen IC, the boards look identical. And in fact I was able to find an intermediate version of the schematic [5] that uses the old styling but includes the touchscreen IC. ========== [1]: https://licheepizero.us/ [2]: http://nano.lichee.pro/ [3]: https://wiki.sipeed.com/hardware/en/lichee/Nano/Nano.html [4]: see e.g. http://bbs.lichee.pro/ [5]: https://github.com/hongxuyao/F1C100s_with_Keil_RTX4_emWin5/blob/spl-separated/doc/lichee-nano/lichee_nano-Schematic.pdf Signed-off-by: Andre Przywara Reviewed-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-5-andre.przywara@arm.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 086c68771d2b..95278a6a9a8e 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -391,6 +391,11 @@ properties: - const: libretech,all-h5-cc-h5 - const: allwinner,sun50i-h5 + - description: Lichee Pi Nano + items: + - const: licheepi,licheepi-nano + - const: allwinner,suniv-f1c100s + - description: Lichee Pi One items: - const: licheepi,licheepi-one From 1aba2af585fc594f08e2a90e37d7f943b6d68730 Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Thu, 17 Mar 2022 16:23:42 +0000 Subject: [PATCH 109/791] ARM: dts: suniv: F1C100: add clock and reset macros Include clock and reset macros and replace magic numbers. Signed-off-by: Jesse Taube Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-6-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index def830101448..922efd5e9457 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,6 +4,9 @@ * Copyright 2018 Mesih Kilinc */ +#include +#include + / { #address-cells = <1>; #size-cells = <1>; @@ -82,7 +85,7 @@ compatible = "allwinner,suniv-f1c100s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <38>, <39>, <40>; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -116,8 +119,8 @@ interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 38>; - resets = <&ccu 24>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -127,8 +130,8 @@ interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 39>; - resets = <&ccu 25>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -138,8 +141,8 @@ interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 26>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; }; From a6d9efb62a482c2da1078d9654b68a0777aa2fc6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:43 +0000 Subject: [PATCH 110/791] ARM: dts: suniv: F1C100: fix CPU node The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing the reg property, and the corresponding address and size cells properties. Add them to make the bindings check pass. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-7-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 922efd5e9457..0a7fa37bbd24 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -29,9 +29,13 @@ }; cpus { - cpu { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; }; }; From a26123f355f23d8ba980d7ecf4899d309d5cd708 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:44 +0000 Subject: [PATCH 111/791] ARM: dts: suniv: F1C100: fix timer node The Allwinner F1C100s has three timer instances, each with their own interrupt line. Add the missing two interrupts to the DT node, to match the DT binding. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-8-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0a7fa37bbd24..f455e276521e 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -105,7 +105,7 @@ timer@1c20c00 { compatible = "allwinner,suniv-f1c100s-timer"; reg = <0x01c20c00 0x90>; - interrupts = <13>; + interrupts = <13>, <14>, <15>; clocks = <&osc24M>; }; From a672a3f2f0221bc56e94d6508e3b3fc74442065b Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Thu, 17 Mar 2022 16:23:45 +0000 Subject: [PATCH 112/791] ARM: dts: suniv: F1C100: add MMC controllers The F1C100 series contains two MMC controllers, where the first one is typically connected to an (micro)SD card slot (as this is the one the BROM is able to boot from). Describe the two controllers in the SoC .dtsi. We also add the pinctrl description for MMC0, since this is the only pin set supporting that function anyway, and SD cards are very common across boards. Signed-off-by: Jesse Taube Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-9-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index f455e276521e..59e0bd952f50 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -69,6 +69,42 @@ }; }; + mmc0: mmc@1c0f000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <23>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <24>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; @@ -96,6 +132,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0"; From 30b6259f8bb8f17377d13c61e47b66d71ec3abfe Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Thu, 17 Mar 2022 16:23:46 +0000 Subject: [PATCH 113/791] ARM: dts: suniv: licheepi-nano: add microSD card Enable MMC0 and supply the board setting to enable the microSD card slot on the LicheePi Nano board. Apart from the always missing write protect switch on microSD slots, the card-detect pin is not connected to anything, so we use the broken-cd property. Signed-off-by: Jesse Taube [Andre: add alias and vmmc supply] Signed-off-by: Andre Przywara Acked-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-10-andre.przywara@arm.com --- .../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts index a1154e6c7cb5..8fa79a1d1d2d 100644 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -11,12 +11,28 @@ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; aliases { + mmc0 = &mmc0; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + status = "okay"; + vmmc-supply = <®_vcc3v3>; }; &uart0 { From 382e0d4f9ece6d1b282ac70c246bdc7be5edc053 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:47 +0000 Subject: [PATCH 114/791] dt-bindings: spi: sunxi: document F1C100 controllers The Allwinner F1C100 series contains two SPI controllers, which are compatible to the IP block used in the Allwinner H3 as well. The only difference in the integration is the missing mod clock in the F1C100, but that does not affect the SPI controller binding, as we can still supply the correct clock (AHB parent) easily. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-11-andre.przywara@arm.com --- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 908248260afa..ca4c95345a49 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -26,6 +26,7 @@ properties: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi - allwinner,sun50i-h616-spi + - allwinner,suniv-f1c100s-spi - const: allwinner,sun8i-h3-spi reg: From 335f57508a7a3220feb161400f0475e7f42be1b3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:48 +0000 Subject: [PATCH 115/791] ARM: dts: suniv: F1C100: add SPI support The F1C100 series contains two SPI controllers, and many boards use SPI0 for a SPI flash, as the BROM is able to boot from that. Describe the two controllers in the SoC .dtsi, and also add the PortC pins for SPI0, since this is where BROM looks at when trying to boot from the commonly used SPI flash. The SPI controller seems to be the same as in the H3 chips, but it lacks a separate mod clock. The manual says it's connected to AHB directly. We don't export that AHB clock directly, but can use the AHB *gate* clock as a clock source, since the SPI driver is not supposed to change the AHB frequency anyway. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-12-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 59e0bd952f50..0edc1724407b 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -69,6 +69,34 @@ }; }; + spi0: spi@1c05000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,suniv-f1c100s-mmc", "allwinner,sun7i-a20-mmc"; @@ -138,6 +166,11 @@ drive-strength = <30>; }; + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0"; From 37384b81bc255bca3412536c50598fa50d05c751 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 17 Mar 2022 16:23:49 +0000 Subject: [PATCH 116/791] ARM: dts: suniv: licheepi-nano: add SPI flash Most LicheePi Nano boards come with soldered SPI flash, so enable SPI0 in the .dts and describe the flash chip. There is evidence of different flash chips used, also of boards with no flash chip soldered, but the Winbond 16MiB model is the most common, so use that for the compatible string. The actual flash chip model will be auto-detected at runtime anyway. Signed-off-by: Andre Przywara Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220317162349.739636-13-andre.przywara@arm.com --- arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts index 8fa79a1d1d2d..04e59b8381cb 100644 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -13,6 +13,7 @@ aliases { mmc0 = &mmc0; serial0 = &uart0; + spi0 = &spi0; }; chosen { @@ -35,6 +36,20 @@ vmmc-supply = <®_vcc3v3>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pe_pins>; From 7828494f78e4596e24d3fcce5bb2872f42ab9632 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:56 +0100 Subject: [PATCH 117/791] ARM: dts: stm32: Add alternate pinmux for ethernet0 pins Add another mux option for ethernet0 pins, this is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and then fed back via PA1 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index f0d66d8c6e3b..4890e8d4353b 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -379,6 +379,40 @@ }; }; + ethernet0_rmii_pins_c: rmii-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ From f6f39403ce6120226308124b80af7f18731192e7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:57 +0100 Subject: [PATCH 118/791] ARM: dts: stm32: Add alternate pinmux for mco2 pins Add pinmux option for MCO2 pin. This is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 4890e8d4353b..3c44a04c13fb 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -923,6 +923,21 @@ }; }; + mco2_pins_a: mco2-0 { + pins { + pinmux = ; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = ; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ From 73ab99aad50cd05ed0bc230aea39c733ebb9711d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:58 +0100 Subject: [PATCH 119/791] ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Tested-by: Johann Neuhauser Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 22 ++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 83e2c87713f8..238a611192e7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -446,6 +445,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; From ae6a766f4fc1ff1e0174ff6f6ba1fe24986f6852 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:10 +0200 Subject: [PATCH 120/791] ARM: dts: broadcom: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts | 2 +- arch/arm/boot/dts/bcm958522er.dts | 2 +- arch/arm/boot/dts/bcm958525er.dts | 2 +- arch/arm/boot/dts/bcm958525xmc.dts | 2 +- arch/arm/boot/dts/bcm958622hr.dts | 2 +- arch/arm/boot/dts/bcm958623hr.dts | 2 +- arch/arm/boot/dts/bcm958625hr.dts | 2 +- arch/arm/boot/dts/bcm958625k.dts | 2 +- arch/arm/boot/dts/bcm988312hr.dts | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts index 2e7fda9b998c..975f854f652f 100644 --- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts +++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts @@ -34,7 +34,7 @@ status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { compatible = "m25p80"; reg = <0>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 60376b62cd5f..15f023656df0 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -136,7 +136,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index 8eeb319f5b54..9b9c225a1fb3 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -136,7 +136,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index dc86d5a91292..ca9311452739 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -152,7 +152,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index c457e53d886e..9db3c851451a 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -140,7 +140,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index c06871915a1c..32786e7c4e12 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -144,7 +144,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index b22fc6624ae4..74263d98de73 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -151,7 +151,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 0183f8965a74..69ebc7a913a7 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -155,7 +155,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index 007e34715956..e96bc3f2d5cf 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -140,7 +140,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; From ad2c6e3cdd6121bdabf0726355dbe04b987c92e0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:11 +0200 Subject: [PATCH 121/791] arm64: dts: broadcom: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts | 2 +- arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index 12a4b1c03390..e34172e3117e 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -203,7 +203,7 @@ &qspi { bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index f00c21e0767e..7bf26f3e36bf 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -146,7 +146,7 @@ }; &qspi { - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts index 77efa28c4dd5..dfac910a45d6 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts @@ -61,7 +61,7 @@ cs-gpios = <&gpio_hsls 34 0>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; @@ -76,7 +76,7 @@ cs-gpios = <&gpio_hsls 96 0>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; From fa04ccac619085332563fb433ffc4ecc8ba5489e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 21:29:38 +0200 Subject: [PATCH 122/791] ARM: dts: nspire: use lower case hex addresses in node unit addresses Convert all hex addresses in node unit addresses to lower case to fix dt_binding_check and dtc W=1 warnings. Conversion was done using sed: $ sed -e 's/@\([a-zA-Z0-9_-]*\) {/@\L\1 {/' -i arch/arm/boot/dts/nspire* $ sed -e 's/<0x\([a-zA-Z0-9_-]*\) /<0x\L\1 /g' -i arch/arm/boot/dts/nspire* Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220317115542.450032-2-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/nspire-classic.dtsi | 10 ++--- arch/arm/boot/dts/nspire-cx.dts | 4 +- arch/arm/boot/dts/nspire.dtsi | 60 +++++++++++++-------------- 3 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi index 41744cc2bc72..01e1bb7c3c6c 100644 --- a/arch/arm/boot/dts/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire-classic.dtsi @@ -17,7 +17,7 @@ &fast_timer { /* compatible = "lsi,zevio-timer"; */ - reg = <0x90010000 0x1000>, <0x900A0010 0x8>; + reg = <0x90010000 0x1000>, <0x900a0010 0x8>; }; &uart { @@ -30,12 +30,12 @@ &timer0 { /* compatible = "lsi,zevio-timer"; */ - reg = <0x900C0000 0x1000>, <0x900A0018 0x8>; + reg = <0x900c0000 0x1000>, <0x900a0018 0x8>; }; &timer1 { compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; + reg = <0x900d0000 0x1000>, <0x900a0020 0x8>; }; &keypad { @@ -66,10 +66,10 @@ #address-cells = <1>; #size-cells = <1>; - intc: interrupt-controller@DC000000 { + intc: interrupt-controller@dc000000 { compatible = "lsi,zevio-intc"; interrupt-controller; - reg = <0xDC000000 0x1000>; + reg = <0xdc000000 0x1000>; #interrupt-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts index 0c16b04e2744..590b7dff6ae5 100644 --- a/arch/arm/boot/dts/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -92,10 +92,10 @@ #address-cells = <1>; #size-cells = <1>; - intc: interrupt-controller@DC000000 { + intc: interrupt-controller@dc000000 { compatible = "arm,pl190-vic"; interrupt-controller; - reg = <0xDC000000 0x1000>; + reg = <0xdc000000 0x1000>; #interrupt-cells = <1>; }; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index 90e033d9141f..bb240e6a3a6f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -20,9 +20,9 @@ reg = <0x00000000 0x80000>; }; - sram: sram@A4000000 { + sram: sram@a4000000 { device = "memory"; - reg = <0xA4000000 0x20000>; + reg = <0xa4000000 0x20000>; }; timer_clk: timer_clk { @@ -33,12 +33,12 @@ base_clk: base_clk { #clock-cells = <0>; - reg = <0x900B0024 0x4>; + reg = <0x900b0024 0x4>; }; ahb_clk: ahb_clk { #clock-cells = <0>; - reg = <0x900B0024 0x4>; + reg = <0x900b0024 0x4>; clocks = <&base_clk>; }; @@ -71,28 +71,28 @@ #size-cells = <1>; ranges; - spi: spi@A9000000 { - reg = <0xA9000000 0x1000>; + spi: spi@a9000000 { + reg = <0xa9000000 0x1000>; }; - usb0: usb@B0000000 { + usb0: usb@b0000000 { compatible = "lsi,zevio-usb"; - reg = <0xB0000000 0x1000>; + reg = <0xb0000000 0x1000>; interrupts = <8>; usb-phy = <&usb_phy>; vbus-supply = <&vbus_reg>; }; - usb1: usb@B4000000 { - reg = <0xB4000000 0x1000>; + usb1: usb@b4000000 { + reg = <0xb4000000 0x1000>; interrupts = <9>; status = "disabled"; }; - lcd: lcd@C0000000 { + lcd: lcd@c0000000 { compatible = "arm,pl111", "arm,primecell"; - reg = <0xC0000000 0x1000>; + reg = <0xc0000000 0x1000>; interrupts = <21>; /* @@ -105,17 +105,17 @@ clock-names = "clcdclk", "apb_pclk"; }; - adc: adc@C4000000 { - reg = <0xC4000000 0x1000>; + adc: adc@c4000000 { + reg = <0xc4000000 0x1000>; interrupts = <11>; }; - tdes: crypto@C8010000 { - reg = <0xC8010000 0x1000>; + tdes: crypto@c8010000 { + reg = <0xc8010000 0x1000>; }; - sha256: crypto@CC000000 { - reg = <0xCC000000 0x1000>; + sha256: crypto@cc000000 { + reg = <0xcc000000 0x1000>; }; apb@90000000 { @@ -143,16 +143,16 @@ interrupts = <1>; }; - timer0: timer@900C0000 { - reg = <0x900C0000 0x1000>; + timer0: timer@900c0000 { + reg = <0x900c0000 0x1000>; clocks = <&timer_clk>, <&timer_clk>, <&timer_clk>; clock-names = "timer0clk", "timer1clk", "apb_pclk"; }; - timer1: timer@900D0000 { - reg = <0x900D0000 0x1000>; + timer1: timer@900d0000 { + reg = <0x900d0000 0x1000>; interrupts = <19>; clocks = <&timer_clk>, <&timer_clk>, <&timer_clk>; @@ -171,18 +171,18 @@ interrupts = <4>; }; - misc: misc@900A0000 { - reg = <0x900A0000 0x1000>; + misc: misc@900a0000 { + reg = <0x900a0000 0x1000>; }; - pwr: pwr@900B0000 { - reg = <0x900B0000 0x1000>; + pwr: pwr@900b0000 { + reg = <0x900b0000 0x1000>; interrupts = <15>; }; - keypad: input@900E0000 { + keypad: input@900e0000 { compatible = "ti,nspire-keypad"; - reg = <0x900E0000 0x1000>; + reg = <0x900e0000 0x1000>; interrupts = <16>; scan-interval = <1000>; @@ -191,8 +191,8 @@ clocks = <&apb_pclk>; }; - contrast: contrast@900F0000 { - reg = <0x900F0000 0x1000>; + contrast: contrast@900f0000 { + reg = <0x900f0000 0x1000>; }; led: led@90110000 { From fbcd5ad7a419ad40644a0bb8b4152bc660172d8a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 21:29:59 +0200 Subject: [PATCH 123/791] ARM: dts: ox820: align interrupt controller node name with dtschema Fixes dtbs_check warnings like: gic@1000: $nodename:0: 'gic@1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Acked-by: Neil Armstrong Link: https://lore.kernel.org/r/20220317115705.450427-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/ox820.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi index 90846a7655b4..dde4364892bf 100644 --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -287,7 +287,7 @@ clocks = <&armclk>; }; - gic: gic@1000 { + gic: interrupt-controller@1000 { compatible = "arm,arm11mp-gic"; interrupt-controller; #interrupt-cells = <3>; From c9bdd50d2019f78bf4c1f6a79254c27771901023 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 21:30:22 +0200 Subject: [PATCH 124/791] ARM: dts: socfpga: align interrupt controller node name with dtschema Fixes dtbs_check warnings like: $nodename:0: 'intc@fffed000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski Acked-by: Dinh Nguyen Link: https://lore.kernel.org/r/20220317115705.450427-2-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7c1d6423d7f8..b8c5dd7860cb 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -46,7 +46,7 @@ <0xff113000 0x1000>; }; - intc: intc@fffed000 { + intc: interrupt-controller@fffed000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 3ba431dfa8c9..f1e50d2e623a 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -38,7 +38,7 @@ <0xff113000 0x1000>; }; - intc: intc@ffffd000 { + intc: interrupt-controller@ffffd000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; From 8771ce5eadb5b73daab190c2451172e43e16ae41 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:21:59 +0200 Subject: [PATCH 125/791] arm64: dts: meson: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220407142159.293836-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index 2d7032f41e4b..bcdf55f48a83 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -416,7 +416,7 @@ pinctrl-names = "default"; status = "okay"; - gd25lq128: spi-flash@0 { + gd25lq128: flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index 2d769203f671..213a0705ebdc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -298,7 +298,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 93d8f8aff70d..874f91c348ec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -284,7 +284,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - nor_4u1: spi-flash@0 { + nor_4u1: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 86bdc0baf032..f43c45daf7eb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -374,7 +374,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q16", "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 3cf4ecb6d52e..c9705941e4ab 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -458,7 +458,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q128: spi-flash@0 { + w25q128: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q128fw", "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index f3f953225bf5..e3486f60645a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -121,7 +121,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; From e8662d0832431a069f0138da72c638cb6a377bdd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:21:58 +0200 Subject: [PATCH 126/791] ARM: dts: meson: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220407142159.293836-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/meson8-minix-neo-x8.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 61ec929ab86e..56ea875c418c 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -65,7 +65,7 @@ pinctrl-0 = <&spi_nor_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25l1606e"; #address-cells = <1>; #size-cells = <1>; From a3b2fc4f76de7d307a5ed865b88fb35c69ebd172 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 28 Feb 2022 14:12:18 +0100 Subject: [PATCH 127/791] arm64: dts: imx8mq-librem5: make the volume buttons a wakeup source They turn on the display currently so to be consistent, let's make them wake the system from suspend as well. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 05c16376b4d8..0d391468bf21 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -42,6 +42,7 @@ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; + wakeup-source; }; vol-up { @@ -49,6 +50,7 @@ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; + wakeup-source; }; }; From b019694c8be088bef1011fb21ea6fc4180727c6e Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 28 Feb 2022 14:12:19 +0100 Subject: [PATCH 128/791] arm64: dts: imx8mq-librem5: remove description of CHG_STATUS_B That pin is not connected on the board so no need to describe it. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 0d391468bf21..b7d9edc1358b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -389,8 +389,6 @@ fsl,pins = < /* CHRG_INT */ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 - /* CHG_STATUS_B */ - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 >; }; From 2bf475ce12e6a67b971045f3ed53494bbcbf0b65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 28 Feb 2022 14:12:20 +0100 Subject: [PATCH 129/791] arm64: dts: imx8mq-librem5: higher boost regulation current MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1,5A is what's used by the type-c controller on the Librem 5 board so increase ti,boost-max-current to 1,5A too. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index b7d9edc1358b..a0c8191bd33c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1098,7 +1098,7 @@ ti,precharge-current = <130000>; /* uA */ ti,minimum-sys-voltage = <3700000>; /* uV */ ti,boost-voltage = <5000000>; /* uV */ - ti,boost-max-current = <500000>; /* uA */ + ti,boost-max-current = <1500000>; /* uA */ ti,use-vinmin-threshold = <1>; /* enable VINDPM */ ti,vinmin-threshold = <3900000>; /* uV */ monitored-battery = <&bat>; From c3e9d4547a9e15b56c2ceefa54ec04057b3276eb Mon Sep 17 00:00:00 2001 From: Angus Ainslie Date: Mon, 28 Feb 2022 14:12:21 +0100 Subject: [PATCH 130/791] arm64: dts: imx8mq-librem5: add a RO firmware partition This partition will hold a squashfs firmware jail. Only one read-only partition is needed. Signed-off-by: Angus Ainslie Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index a0c8191bd33c..587e55aaa57b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -325,15 +325,10 @@ }; partition@30000 { - label = "protected1"; - reg = <0x30000 0x10000>; + label = "firmware"; + reg = <0x30000 0x1d0000>; read-only; }; - - partition@40000 { - label = "rw"; - reg = <0x40000 0x1C0000>; - }; }; }; From 9694ed9bcf3b761c05d7787739eb4e77bd86c367 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 28 Feb 2022 14:12:22 +0100 Subject: [PATCH 131/791] arm64: dts: imx8mq-librem5-r4: add the correct panel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The r4 ("Evergreen") hardware revision of the Librem 5 phone includes a slightly different panel than the revisions before it. Since its' description is available, describe it properly for the board. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts index 30d65bef6939..1056b7981bdb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts @@ -18,6 +18,10 @@ led-max-microamp = <25000>; }; +&lcd_panel { + compatible = "ys,ys57pss36bh5gq"; +}; + &proximity { proximity-near-level = <10>; }; From 579df4288896f22c5e8c38aee771edc5f25bf461 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 14:25:23 +0100 Subject: [PATCH 132/791] arm64: dts: imx8mn-evk: add QSPI flash There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board. Add a device tree node for it. Tested on a 8MNANOD3L-EVK. Signed-off-by: Michael Walle Tested-by: Heiko Thiery Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index c3f15192b76c..dc75d6d13bb3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -110,6 +110,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <166000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -267,6 +283,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 From fc0f051246212675de77c352ce955a5738e1419d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 30 Mar 2022 12:46:19 +0200 Subject: [PATCH 133/791] arm64: dts: imx8mp: add GPC node with GPU power domains Add the power domains for the GPUs, which do not require any interaction with a blk-ctrl, but are simply two PU domains nested inside a MIX domain. Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Tested-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 41 +++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 794d75173cf5..c6bfaacaeb7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -475,6 +476,46 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_gpu2d: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + power-domains = <&pgc_gpumix>; + }; + + pgc_gpumix: power-domain@7 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <400000000>; + }; + + pgc_gpu3d: power-domain@9 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + power-domains = <&pgc_gpumix>; + }; + }; + }; }; aips2: bus@30400000 { From 4bdb11926e486757ae01312228df60d7a215b3e5 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 30 Mar 2022 12:46:20 +0200 Subject: [PATCH 134/791] arm64: dts: imx8mp: add GPU nodes Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP. etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0 Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Tested-by: Alexander Stein Tested-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c6bfaacaeb7f..afd36374dccb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -933,6 +933,37 @@ }; }; + gpu3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; + power-domains = <&pgc_gpu3d>; + }; + + gpu2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>; + power-domains = <&pgc_gpu2d>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, From 1ceaccf2b267165fcff39e374f8596dfccd2321b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 22:41:15 +0200 Subject: [PATCH 135/791] arm64: dts: synaptics: remove unused DTSI for AS370 The as370.dtsi for Synaptics AS370 SoC does not have a user (DTS board file), is uncompilable and untestable. It was added back in 2018. No user appeared since that time, so assume it won't be added. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/arm/syna.txt | 4 - arch/arm64/boot/dts/synaptics/as370.dtsi | 173 ------------------ 2 files changed, 177 deletions(-) delete mode 100644 arch/arm64/boot/dts/synaptics/as370.dtsi diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt index d8b48f2edf1b..851f48ead927 100644 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ b/Documentation/devicetree/bindings/arm/syna.txt @@ -18,10 +18,6 @@ stable binding/ABI. --------------------------------------------------------------- -Boards with the Synaptics AS370 SoC shall have the following properties: - Required root node property: - compatible: "syna,as370" - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi deleted file mode 100644 index 4bb5d650df9c..000000000000 --- a/arch/arm64/boot/dts/synaptics/as370.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Synaptics Incorporated - * - * Author: Jisheng Zhang - */ - -#include - -/ { - compatible = "syna,as370"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible = "cache"; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <75>; - exit-latency-us = <155>; - min-residency-us = <1000>; - }; - }; - }; - - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts = ; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe80000 0x10000>; - - uart0: serial@c00 { - compatible = "snps,dw-apb-uart"; - reg = <0xc00 0x100>; - interrupts = ; - clocks = <&osc>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio0: gpio@1800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio1: gpio@2000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x2000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; - }; -}; From 397ad94668c14b558d8dcf2bf29bce4bf78222ba Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 27 Feb 2022 00:10:27 +0530 Subject: [PATCH 136/791] arm64: dts: qcom: sm8150: Add pdc interrupt controller node Add pdc interrupt controller for sm8150. Cc: Maulik Shah Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226184028.111566-4-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 15f3bf2e7ea0..a57b898ce5be 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3381,6 +3381,16 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8150-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x400>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; From fe75b0c4a6911243fe239fd0c2b2bda4fd398f6e Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 24 Mar 2022 02:00:52 +0530 Subject: [PATCH 137/791] arm64: dts: qcom: sm8150: Add ufs power-domain entries Add power-domain entries for UFS phy node in sm8150 dts. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma [bjorn: Dropped power-domain-names] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220323203052.1124683-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a57b898ce5be..f4f639f3dc47 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1807,6 +1807,8 @@ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; status = "disabled"; From a1c86c6805336503ad2460426736456cc324d4a3 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 26 Mar 2022 11:27:53 +0530 Subject: [PATCH 138/791] arm64: dts: qcom: sm8150: Add PCIe nodes Add nodes for the two PCIe controllers found on the SM8150 SoC. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220326055754.1796146-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f4f639f3dc47..13547c15f321 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1746,6 +1746,203 @@ interrupts = ; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + iommus = <&apps_smmu 0x1d80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: phy@1c06200 { + reg = <0 0x1c06200 0 0x170>, /* tx */ + <0 0x1c06400 0 0x200>, /* rx */ + <0 0x1c06800 0 0x1f0>, /* pcs */ + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1e00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: phy@1c0e200 { + reg = <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ + <0 0x1c0e600 0 0x170>, /* tx1 */ + <0 0x1c0e800 0 0x200>, /* rx1 */ + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -2450,6 +2647,52 @@ drive-strength = <6>; bias-disable; }; + + pcie0_default_state: pcie0-default { + perst { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio36"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + perst { + pins = "gpio102"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio103"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio104"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; remoteproc_mpss: remoteproc@4080000 { From 03d470ce2b70f269cecf2aeacee41e228cafde44 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 26 Mar 2022 11:27:54 +0530 Subject: [PATCH 139/791] arm64: dts: qcom: sa8155: Enable PCIe nodes SA8155p ADP board supports the PCIe0 controller in the RC mode (only). So add the support for the same. Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220326055754.1796146-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 8756c2b25c7e..676e4fe3f848 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -387,6 +387,21 @@ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; }; +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l18c_0p88>; + vdda-pll-supply = <&vreg_l8c_1p2>; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l18c_0p88>; + vdda-pll-supply = <&vreg_l8c_1p2>; +}; + &tlmm { gpio-reserved-ranges = <0 4>; From 90f38145e6dd25ff0d9ebe48d28b8ae3a814d52d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 3 Mar 2022 16:06:53 +0100 Subject: [PATCH 140/791] ARM: dts: imx7s: fix iomuxc_lpsr node name Schema requires the node being named 'pinctrl'. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 5af6d58666f4..008e3da460f1 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -446,7 +446,7 @@ status = "disabled"; }; - iomuxc_lpsr: iomuxc-lpsr@302c0000 { + iomuxc_lpsr: pinctrl@302c0000 { compatible = "fsl,imx7d-iomuxc-lpsr"; reg = <0x302c0000 0x10000>; fsl,input-sel = <&iomuxc>; From 096f58507374e1293a9e9cff8a1ccd5f37780a20 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Sun, 27 Mar 2022 11:08:50 -0700 Subject: [PATCH 141/791] ARM: dts: s5pv210: Remove spi-cs-high on panel in Aries Since commit 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors"), the panel has been blank due to an inverted CS GPIO. In order to correct this, drop the spi-cs-high from the panel SPI device. Fixes: 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors") Cc: Signed-off-by: Jonathan Bakker Link: https://lore.kernel.org/r/CY4PR04MB05670C771062570E911AF3B4CB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index c8f1c324a6c2..dba186d57924 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -564,7 +564,6 @@ reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; vdd3-supply = <&ldo7_reg>; vci-supply = <&ldo17_reg>; - spi-cs-high; spi-max-frequency = <1200000>; pinctrl-names = "default"; From 3f5e3d3a8b895c8a11da8b0063ba2022dd9e2045 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Sun, 27 Mar 2022 11:08:51 -0700 Subject: [PATCH 142/791] ARM: dts: s5pv210: Correct interrupt name for bluetooth in Aries Correct the name of the bluetooth interrupt from host-wake to host-wakeup. Fixes: 1c65b6184441b ("ARM: dts: s5pv210: Correct BCM4329 bluetooth node") Cc: Signed-off-by: Jonathan Bakker Link: https://lore.kernel.org/r/CY4PR04MB0567495CFCBDC8D408D44199CB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index dba186d57924..9ae4c4a0fab8 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -894,7 +894,7 @@ device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gph2>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; + interrupt-names = "host-wakeup"; }; }; From 9576ec12261c4b639cd802fd9c13e3c9605165da Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Sun, 27 Mar 2022 11:08:52 -0700 Subject: [PATCH 143/791] ARM: dts: s5pv210: Adjust memory reg entries to match spec The reg property of memory nodes should have pairs of offset, size; not all memory banks lumped in as one. Signed-off-by: Jonathan Bakker Link: https://lore.kernel.org/r/CY4PR04MB05677849A13F41BF603906DFCB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aquila.dts | 3 +-- arch/arm/boot/dts/s5pv210-aries.dtsi | 6 +++--- arch/arm/boot/dts/s5pv210-goni.dts | 6 +++--- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 54de3bc77c30..bc0b7354b6c0 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -29,8 +29,7 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x18000000>; + reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>; }; pmic_ap_clk: clock-0 { diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 9ae4c4a0fab8..32216aa542b2 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -24,9 +24,9 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; }; reserved-memory { diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index c6f39147cb96..d32f42dd1bf5 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -30,9 +30,9 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; }; pmic_ap_clk: clock-0 { From 21e4b7d151af9a3191fb251e2b4044e361a56102 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Sun, 27 Mar 2022 11:08:53 -0700 Subject: [PATCH 144/791] ARM: dts: s5pv210: Adjust DMA node names to match spec DMA node names should be dma-controller according to the DT spec, so rename them from pdma/mdma. Prevents warnings when running make dtbs_check Signed-off-by: Jonathan Bakker Link: https://lore.kernel.org/r/CY4PR04MB0567F52ABAE0A3CCD3C7CE59CB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 4ea1e638432a..7c133c331896 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -117,7 +117,7 @@ }; }; - pdma0: dma@e0900000 { + pdma0: dma-controller@e0900000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xe0900000 0x1000>; interrupt-parent = <&vic0>; @@ -129,7 +129,7 @@ #dma-requests = <32>; }; - pdma1: dma@e0a00000 { + pdma1: dma-controller@e0a00000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xe0a00000 0x1000>; interrupt-parent = <&vic0>; @@ -518,7 +518,7 @@ clock-names = "sclk_fimg2d", "fimg2d"; }; - mdma1: mdma@fa200000 { + mdma1: dma-controller@fa200000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xfa200000 0x1000>; interrupt-parent = <&vic0>; From 9e916fb9bc3d16066286f19fc9c51d26a6aec6bd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 27 Mar 2022 11:08:54 -0700 Subject: [PATCH 145/791] ARM: dts: s5pv210: align DMA channels with dtschema dtschema expects DMA channels in specific order (tx, rx and tx-sec). The order actually should not matter because dma-names is used however let's make it aligned with dtschema to suppress warnings like: i2s@eee30000: dma-names: ['rx', 'tx', 'tx-sec'] is not valid under any of the given schemas Signed-off-by: Krzysztof Kozlowski Co-developed-by: Jonathan Bakker Signed-off-by: Jonathan Bakker Link: https://lore.kernel.org/r/CY4PR04MB056779A9C50DC95987C5272ACB1C9@CY4PR04MB0567.namprd04.prod.outlook.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 2 +- arch/arm/boot/dts/s5pv210.dtsi | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 32216aa542b2..daa1067055c8 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -635,7 +635,7 @@ }; &i2s0 { - dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>; + dmas = <&pdma0 10>, <&pdma0 9>, <&pdma0 11>; status = "okay"; }; diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 7c133c331896..ac281f42e8f5 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -239,8 +239,8 @@ reg = <0xeee30000 0x1000>; interrupt-parent = <&vic2>; interrupts = <16>; - dma-names = "rx", "tx", "tx-sec"; - dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; + dma-names = "tx", "rx", "tx-sec"; + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 11>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; @@ -259,8 +259,8 @@ reg = <0xe2100000 0x1000>; interrupt-parent = <&vic2>; interrupts = <17>; - dma-names = "rx", "tx"; - dmas = <&pdma1 12>, <&pdma1 13>; + dma-names = "tx", "rx"; + dmas = <&pdma1 13>, <&pdma1 12>; clock-names = "iis", "i2s_opclk0"; clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; pinctrl-names = "default"; @@ -274,8 +274,8 @@ reg = <0xe2a00000 0x1000>; interrupt-parent = <&vic2>; interrupts = <18>; - dma-names = "rx", "tx"; - dmas = <&pdma1 14>, <&pdma1 15>; + dma-names = "tx", "rx"; + dmas = <&pdma1 15>, <&pdma1 14>; clock-names = "iis", "i2s_opclk0"; clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; pinctrl-names = "default"; From c043dee9cb6bc332746cd60ec42d5f8220d90332 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:52:11 +0200 Subject: [PATCH 146/791] arm64: dts: rockchip: correct interrupt flags on rk3399 boards GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_HIGH => IRQ_TYPE_LEVEL_HIGH Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200917185211.5483-2-krzk@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 3 ++- 8 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index c654b6b02f3f..b340c9e246c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include #include #include "rk3399.dtsi" @@ -786,7 +787,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts index bee45c17e2ca..7af27e8216f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts @@ -2,6 +2,7 @@ /dts-v1/; #include #include +#include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -629,7 +630,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index 7ba3ed24084b..46c4581deb8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -682,7 +683,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts index 5bbe74bed0ea..a21ac319f809 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -509,7 +510,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 9d3a718f66f6..ed856bfcfc33 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -7,6 +7,7 @@ #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/input/input.h" +#include #include "dt-bindings/usb/pd.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -735,7 +736,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts index cf48746a3ad8..0806545922f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -23,7 +23,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 793d84833921..4053ba72618c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -31,7 +31,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index 25dc61c26a94..94e39ed63397 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -7,6 +7,7 @@ #include "rk3399.dtsi" #include "rk3399-opp.dtsi" +#include / { aliases { @@ -528,7 +529,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; From ef5814e75b2bd9714dbfd60bfc360f940092ba62 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 4 Apr 2022 10:49:42 +0200 Subject: [PATCH 147/791] arm64: dts: rockchip: fix Makefile sorting for BananaPi R2 Pro Banana before evb of course. Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro") Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 4ae9f35434b8..a8893d1d0b9e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -59,5 +59,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb From 6648d167fbd16eaa4ef4972b4904adde2717f722 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Thu, 10 Mar 2022 22:03:50 +0100 Subject: [PATCH 148/791] dt-bindings: arm: rockchip: add radxa rock3 model a Add entry for the Radxa ROCK3 Model A board (with the Rockchip RK3568 SoC). Signed-off-by: Michael Riesch Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220310210352.451136-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index eece92f83a2d..efb0a9c4347b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -545,6 +545,11 @@ properties: - const: radxa,rock2-square - const: rockchip,rk3288 + - description: Radxa ROCK3 Model A + items: + - const: radxa,rock3a + - const: rockchip,rk3568 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 From 22a442e6586c898a6da1fbc57fab1b31dfc3e4b5 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Thu, 10 Mar 2022 22:03:51 +0100 Subject: [PATCH 149/791] arm64: dts: rockchip: add basic dts for the radxa rock3 model a Add basic device tree for the Radxa ROCK3 Model A board (with the Rockchip RK3568 SoC) including Ethernet, USB2 and headphone connector. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220310210352.451136-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-rock-3a.dts | 502 ++++++++++++++++++ 2 files changed, 503 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a8893d1d0b9e..99941e9dbba1 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -61,3 +61,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts new file mode 100644 index 000000000000..53cf444ecb04 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Radxa ROCK3 Model A"; + compatible = "radxa,rock3a", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + mic-in-differential; + }; + }; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth_phy_rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; From 9f4c480f24e2ce1d464ff9d5f8a249a485acdc7f Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 8 Apr 2022 11:12:35 -0400 Subject: [PATCH 150/791] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes Add the dwc3 device nodes to the rk356x device trees. The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable dwc3 host controller. The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable dwc3 host controller. Signed-off-by: Peter Geis Tested-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220408151237.3165046-4-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++- 3 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi index 3839eef5e4f7..0b957068ff89 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi @@ -6,6 +6,10 @@ compatible = "rockchip,rk3566"; }; +&pipegrf { + compatible = "rockchip,rk3566-pipe-grf", "syscon"; +}; + &power { power-domain@RK3568_PD_PIPE { reg = ; @@ -18,3 +22,10 @@ #power-domain-cells = <0>; }; }; + +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 3e07d9f6a2d1..5eafddf62edc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -113,6 +113,10 @@ }; }; +&pipegrf { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; +}; + &power { power-domain@RK3568_PD_PIPE { reg = ; @@ -128,3 +132,8 @@ #power-domain-cells = <0>; }; }; + +&usb_host0_xhci { + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 264dd030e703..55e6dcb948cc 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -258,6 +258,40 @@ status = "disabled"; }; + usb_host0_xhci: usb@fcc00000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "host"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + + usb_host1_xhci: usb@fd000000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "host"; + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG1>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + gic: interrupt-controller@fd400000 { compatible = "arm,gic-v3"; reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ @@ -325,7 +359,6 @@ }; pipegrf: syscon@fdc50000 { - compatible = "rockchip,rk3568-pipe-grf", "syscon"; reg = <0x0 0xfdc50000 0x0 0x1000>; }; From e432309ff8bf2a148bbdd4946ca1580c6b5b610c Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 8 Apr 2022 11:12:36 -0400 Subject: [PATCH 151/791] arm64: dts: rockchip: enable dwc3 on quartz64-a The quartz64 model a has support for both the dwc3 otg port and the dwc3 host port. Add the otg power supply and dwc3 nodes to the device tree to enable support for these. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220408151237.3165046-5-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index dd7f4b9b686b..141a433429b5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -151,6 +151,16 @@ vin-supply = <&vcc5v0_usb>; }; + vcc5v0_usb20_otg: vcc5v0_usb20_otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb20_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dcdc_boost>; + }; + vcc3v3_sd: vcc3v3_sd { compatible = "regulator-fixed"; enable-active-low; @@ -187,6 +197,10 @@ }; }; +&combphy1 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -672,6 +686,29 @@ status = "okay"; }; +&usb_host0_xhci { + status = "okay"; +}; + +/* usb3 controller is muxed with sata1 */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb20_otg>; + status = "okay"; +}; + &usb2phy1 { status = "okay"; }; From d6cfb110b0fdfb4e61ef4e3c3ab89a8f21b4d1b8 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 8 Apr 2022 11:12:37 -0400 Subject: [PATCH 152/791] arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10 The Rockchip RK3568 EVB1 features one USB 3.0 device-only (USB 2.0 OTG) port and one USB 3.0 host-only port. Activate the USB 3.0 controller nodes and phy nodes in the device tree. Signed-off-by: Sascha Hauer Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220408151237.3165046-6-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-evb1-v10.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index a794a0ea5c70..622be8be9813 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -103,6 +103,18 @@ vin-supply = <&vcc5v0_usb>; }; + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + vcc3v3_lcd0_n: vcc3v3-lcd0-n { compatible = "regulator-fixed"; regulator-name = "vcc3v3_lcd0_n"; @@ -136,6 +148,14 @@ }; }; +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -507,6 +527,9 @@ vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; @@ -568,6 +591,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; @@ -576,6 +604,24 @@ status = "okay"; }; +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + vbus-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + &usb2phy1 { status = "okay"; }; From f29ffce32b4e1204b67f82fd80584ec4173cca54 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sat, 9 Apr 2022 13:21:35 +0200 Subject: [PATCH 153/791] arm64: dts: rockchip: Add USB nodes for BPI-R2-Pro Add usb2 nodes to Bananapi R2 Pro board Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220409112136.164481-2-linux@fw-web.de Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index a01886b467ed..e96622c4c413 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -72,6 +72,50 @@ regulator-max-microvolt = <5000000>; vin-supply = <&dc_12v>; }; + + vcc5v0_usb: vcc5v0_usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0 { + /* used for USB3 */ + status = "okay"; +}; + +&combphy1 { + /* used for USB3 */ + status = "okay"; }; &gmac0 { @@ -338,6 +382,16 @@ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { @@ -455,3 +509,42 @@ pinctrl-0 = <&uart9m1_xfer>; status = "disabled"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; From 551e645fed5dd2ed4c81c9e3d3b4827862f51dc6 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sat, 9 Apr 2022 13:21:36 +0200 Subject: [PATCH 154/791] arm64: dts: rockchip: Add SATA support to BPI-R2-Pro Enable the Combphy and Sata nodes in Bananapi R2 Pro Board. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220409112136.164481-3-linux@fw-web.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index e96622c4c413..a4aba63c7a1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -118,6 +118,11 @@ status = "okay"; }; +&combphy2 { + /* used for SATA */ + status = "okay"; +}; + &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; @@ -454,6 +459,10 @@ status = "okay"; }; +&sata2 { + status = "okay"; +}; + &sdhci { bus-width = <8>; max-frequency = <200000000>; From e03774ff21493f4f82ec7853b33fb3ccc35e4363 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 29 Mar 2022 17:07:41 +0200 Subject: [PATCH 155/791] arm64: dts: rockchip: use generic node name for pmucru on rk3399 The node names should be generic, so fix this for the rk3399 pmucru node and rename it to "clock-controller". Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20220329150742.22093-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 88f26d89eea1..01c08a2aaf73 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1413,7 +1413,7 @@ clock-names = "apb_pclk"; }; - pmucru: pmu-clock-controller@ff750000 { + pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; rockchip,grf = <&pmugrf>; From 14fc86b9aa5435bf7dd75839c9a73d9a85a98396 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 29 Mar 2022 17:07:42 +0200 Subject: [PATCH 156/791] arm64: dts: rockchip: add clocks property to cru nodes rk3399 Add clocks property to rk3399 cru nodes to fix warnings like: 'clocks' is a dependency of 'assigned-clocks'. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20220329150742.22093-6-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 01c08a2aaf73..56af1a1d65ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1416,6 +1416,8 @@ pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; @@ -1426,6 +1428,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; From 1b3f36854ab74839693582bc957930f4416ce8ff Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Tue, 8 Mar 2022 11:08:57 -0800 Subject: [PATCH 157/791] arm64: dts: rockchip: Add dfi and dmc nodes to rk3399 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are required to support DDR DVFS on RK3399 platforms. Change since Daniel's posting: reordered by unit address, per existing style Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris Link: https://lore.kernel.org/r/20220308110825.v4.11.Ie97993621975c5463d7928a8646f3737c9f2921d@changeid Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 56af1a1d65ef..a90beec50f6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -178,6 +178,15 @@ ports = <&vopl_out>, <&vopb_out>; }; + dmc: memory-controller { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + status = "disabled"; + }; + pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -1295,6 +1304,16 @@ status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = ; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + vpu: video-codec@ff650000 { compatible = "rockchip,rk3399-vpu"; reg = <0x0 0xff650000 0x0 0x800>; From 80bc6f34c559c97069b75d6eb453d4218c3ed017 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Tue, 8 Mar 2022 11:08:58 -0800 Subject: [PATCH 158/791] arm64: dts: rockchip: Enable dmc and dfi nodes on gru MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY Interface) nodes on gru boards so we can support DDR DVFS. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris Link: https://lore.kernel.org/r/20220308110825.v4.12.I3a5c7f21ecd8221b42c2dbcd618386bce7b3e9a6@changeid Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-gru-chromebook.dtsi | 7 +++++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 12 ++++++++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 28 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 25 +++++++++++++++++ 4 files changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3355fb90fa54..50d459ee4831 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -234,6 +234,13 @@ extcon = <&usbc_extcon0>, <&usbc_extcon1>; }; +&dmc { + center-supply = <&ppvar_centerlogic>; + rockchip,pd-idle-dis-freq-hz = <800000000>; + rockchip,sr-idle-dis-freq-hz = <800000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz = <800000000>; +}; + &edp { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index a9817b3d7edc..913d845eb51a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -391,6 +391,18 @@ camera: &i2c7 { <400000000>; }; +/* The center supply is fixed to .9V on scarlet */ +&dmc { + center-supply = <&pp900_s0>; +}; + +/* We don't need .925 V for 928 MHz on scarlet */ +&dmc_opp_table { + opp03 { + opp-microvolt = <900000>; + }; +}; + &gpio0 { gpio-line-names = /* GPIO0 A 0-7 */ "CLK_32K_AP", diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..23bfba86daab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -373,6 +373,34 @@ <200000000>; }; +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + + rockchip,pd-idle-ns = <160>; + rockchip,sr-idle-ns = <10240>; + rockchip,sr-mc-gate-idle-ns = <40960>; + rockchip,srpd-lite-idle-ns = <61440>; + rockchip,standby-idle-ns = <81920>; + + rockchip,ddr3_odt_dis_freq = <666000000>; + rockchip,lpddr3_odt_dis_freq = <666000000>; + rockchip,lpddr4_odt_dis_freq = <666000000>; + + rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz = <0>; + rockchip,standby-idle-dis-freq-hz = <928000000>; +}; + +&dmc_opp_table { + opp03 { + opp-suspend; + }; +}; + &emmc_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi index 2180e0f75003..6e29e74f6fc6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -110,6 +110,27 @@ opp-microvolt = <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <925000>; + }; + }; }; &cpu_l0 { @@ -136,6 +157,10 @@ operating-points-v2 = <&cluster1_opp>; }; +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; + &gpu { operating-points-v2 = <&gpu_opp_table>; }; From f9814e2ef9056fd919e774e95f721e12420648e6 Mon Sep 17 00:00:00 2001 From: Philip Rinn Date: Thu, 7 Apr 2022 17:51:45 +0200 Subject: [PATCH 159/791] arm64: dts: allwinner: a64: olinuxino: Enable audio Enable the audio hardware on the Olimex A64-OLinuXino board family. Tested on the A64-OLinuXino-2Ge8G-IND variant. Signed-off-by: Philip Rinn Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220407155145.10891-1-rinni@inventati.org --- .../dts/allwinner/sun50i-a64-olinuxino.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index ec7e2c0e82c1..bfb806cf6d7a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -58,6 +58,15 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; @@ -74,6 +83,10 @@ cpu-supply = <®_dcdc2>; }; +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -328,6 +341,23 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack Left", + "Microphone", "Microphone Jack Right", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Left DAC", "DACL", + "Right DAC", "DACR", + "Headphone Jack", "HP", + "ADCL", "Left ADC", + "ADCR", "Right ADC", + "Microphone Jack Left", "MBIAS", + "MIC1", "Microphone Jack Left", + "Microphone Jack Right", "MBIAS", + "MIC2", "Microphone Jack Right"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From 53070cfa8228bdc64148d1e8c76c9f97ed0dfd62 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 30 Mar 2022 15:39:52 +0200 Subject: [PATCH 160/791] ARM: dts: rockchip: rename pcfg_pull_default node name on rk3036 Rename pcfg_pull_default node name so that it fits the regex. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20220330133952.1949-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 477a8d0030c2..242ce42fbd87 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -614,7 +614,7 @@ #interrupt-cells = <2>; }; - pcfg_pull_default: pcfg_pull_default { + pcfg_pull_default: pcfg-pull-default { bias-pull-pin-default; }; From 94382f08702efdd6b6bb3e875726942954a723d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 25 Mar 2022 18:19:55 +0100 Subject: [PATCH 161/791] ARM: dts: imx6qdl-tx6: Drop some duplicated properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit clocks and clock-names are already present in imx6qdl.dtsi since commit f3e7dae323ab ("ARM: dts: imx6qdl: add enet_out clk support"). The change to imx6qdl.dtsi was explicitly done to avoid this construct in this file, so benefit from the change and drop these properties. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index bcc5bbcce769..f41f86a76ea9 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -264,11 +264,6 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; phy-reset-post-delay = <10>; From 9ad9773e89f8e06148b2a0e77fcdcd716f8f3b18 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 11 Mar 2022 18:23:51 +0100 Subject: [PATCH 162/791] arm64: dts: imx8mp: Add missing speed grade phandle And missing speed grade phandle to cpu@0 node. Signed-off-by: Marek Vasut Cc: Anson Huang Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index afd36374dccb..68e6c9099f65 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -59,6 +59,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; #cooling-cells = <2>; }; From 21a14c68f3a34e1ad06d05c153446644fefa748b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 11 Mar 2022 18:23:52 +0100 Subject: [PATCH 163/791] arm64: dts: imx8mp: Add cpu-freq support Add A53 OPP table and cpu regulator to support cpu-freq driver. Signed-off-by: Marek Vasut Cc: Anson Huang Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 68e6c9099f65..e910dc22bf43 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -61,6 +61,7 @@ next-level-cache = <&A53_L2>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -78,6 +79,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -95,6 +97,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -112,6 +115,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -124,6 +128,35 @@ }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x8a0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0xa0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x20>, <0x3>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; From 68b7cf5d91d4c7e8a690693a53738e66d60113f1 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 21 Mar 2022 15:51:31 +0800 Subject: [PATCH 164/791] arm64: dts: imx8mp: add ddr controller node to support EDAC on imx8mp i.MX8MP use synopsys V3.70a ddr controller IP, so add edac support for i.MX8MP based on "snps,ddrc-3.80a" synopsys edac driver. Signed-off-by: Sherry Sun Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e910dc22bf43..2c207bc27d70 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1009,6 +1009,12 @@ interrupt-parent = <&gic>; }; + edacmc: memory-controller@3d400000 { + compatible = "snps,ddrc-3.80a"; + reg = <0x3d400000 0x400000>; + interrupts = ; + }; + ddr-pmu@3d800000 { compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; From 97a07703cf9674823f4432facc0fbcbaed683eeb Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:40 +0100 Subject: [PATCH 165/791] arm64: dts: imx8mm-verdin: update regulator names Annotate regulators which are on-module. Rename usb_otg{1/2}_vbus to USB_{1/2}_EN more in-line with Verdin spec. Annotate PMIC regulators with information on which BUCK/LDO they are on. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 0d84d29e70f1..f70782d2a23d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -86,7 +86,7 @@ regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_ETH"; + regulator-name = "On-module +V3.3_ETH"; startup-delay-us = <200000>; }; @@ -99,7 +99,7 @@ pinctrl-0 = <&pinctrl_reg_usb1_en>; regulator-max-microvolt = <5000000>; regulator-min-microvolt = <5000000>; - regulator-name = "usb_otg1_vbus"; + regulator-name = "USB_1_EN"; }; reg_usb_otg2_vbus: regulator-usb-otg2 { @@ -111,7 +111,7 @@ pinctrl-0 = <&pinctrl_reg_usb2_en>; regulator-max-microvolt = <5000000>; regulator-min-microvolt = <5000000>; - regulator-name = "usb_otg2_vbus"; + regulator-name = "USB_2_EN"; }; reg_usdhc2_vmmc: regulator-usdhc2 { @@ -345,7 +345,7 @@ regulator-boot-on; regulator-max-microvolt = <850000>; regulator-min-microvolt = <800000>; - regulator-name = "+VDD_SOC"; + regulator-name = "On-module +VDD_SOC (BUCK1)"; regulator-ramp-delay = <3125>; }; @@ -356,7 +356,7 @@ regulator-boot-on; regulator-max-microvolt = <950000>; regulator-min-microvolt = <850000>; - regulator-name = "+VDD_ARM"; + regulator-name = "On-module +VDD_ARM (BUCK2)"; regulator-ramp-delay = <3125>; }; @@ -365,7 +365,7 @@ regulator-boot-on; regulator-max-microvolt = <950000>; regulator-min-microvolt = <850000>; - regulator-name = "+VDD_GPU_VPU_DDR"; + regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; }; reg_vdd_3v3: BUCK4 { @@ -373,7 +373,7 @@ regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3"; + regulator-name = "On-module +V3.3 (BUCK4)"; }; reg_vdd_1v8: BUCK5 { @@ -381,7 +381,7 @@ regulator-boot-on; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; - regulator-name = "PWR_1V8_MOCI"; + regulator-name = "PWR_1V8_MOCI (BUCK5)"; }; reg_nvcc_dram: BUCK6 { @@ -389,7 +389,7 @@ regulator-boot-on; regulator-max-microvolt = <1100000>; regulator-min-microvolt = <1100000>; - regulator-name = "+VDD_DDR"; + regulator-name = "On-module +VDD_DDR (BUCK6)"; }; reg_nvcc_snvs: LDO1 { @@ -397,7 +397,7 @@ regulator-boot-on; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_SNVS"; + regulator-name = "On-module +V1.8_SNVS (LDO1)"; }; reg_vdd_snvs: LDO2 { @@ -405,7 +405,7 @@ regulator-boot-on; regulator-max-microvolt = <900000>; regulator-min-microvolt = <800000>; - regulator-name = "+V0.8_SNVS"; + regulator-name = "On-module +V0.8_SNVS (LDO2)"; }; reg_vdda: LDO3 { @@ -413,7 +413,7 @@ regulator-boot-on; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8A"; + regulator-name = "On-module +V1.8A (LDO3)"; }; reg_vdd_phy: LDO4 { @@ -421,13 +421,13 @@ regulator-boot-on; regulator-max-microvolt = <900000>; regulator-min-microvolt = <900000>; - regulator-name = "+V0.9_MIPI"; + regulator-name = "On-module +V0.9_MIPI (LDO4)"; }; reg_nvcc_sd: LDO5 { regulator-max-microvolt = <3300000>; regulator-min-microvolt = <1800000>; - regulator-name = "+V3.3_1.8_SD"; + regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; }; }; }; From 98e4f1930ef1561042a1be3b3b4fef7c3c271729 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:41 +0100 Subject: [PATCH 166/791] arm64: dts: imx8mm-verdin: multi-line comment style Fix multi-line comment style. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index f70782d2a23d..de811be435d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -580,8 +580,10 @@ atmel_mxt_ts: touch@4a { compatible = "atmel,maxtouch"; - /* Verdin GPIO_9_DSI */ - /* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */ + /* + * Verdin GPIO_9_DSI + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + */ interrupt-parent = <&gpio3>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -695,8 +697,8 @@ uart-has-rtscts; }; -/* Verdin UART_4 */ /* + * Verdin UART_4 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS */ &uart4 { @@ -1205,8 +1207,10 @@ ; }; - /* On-module Wi-Fi/BT or type specific SDHC interface */ - /* (e.g. on X52 extension slot of Verdin Development Board) */ + /* + * On-module Wi-Fi/BT or type specific SDHC interface + * (e.g. on X52 extension slot of Verdin Development Board) + */ pinctrl_usdhc3: usdhc3grp { fsl,pins = , From 344acf05d89ff9a5d3e3d047d36d328efc799fee Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:42 +0100 Subject: [PATCH 167/791] arm64: dts: imx8mm-verdin: alphabetically re-order nodes Alphabetically re-order nodes. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-verdin-wifi.dtsi | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi index 3e06a6ce3406..017db9eab256 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi @@ -17,19 +17,6 @@ }; }; -/* On-module Wi-Fi */ -&usdhc3 { - bus-width = <4>; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; - &gpio3 { gpio-line-names = "SODIMM_52", "SODIMM_54", @@ -92,3 +79,16 @@ "SODIMM_135", "SODIMM_129"; }; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; From 9847725e3a775832376646907159ce644d90bb18 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:43 +0100 Subject: [PATCH 168/791] arm64: dts: imx8mm-verdin: only dashes in node names Make sure we only have dashes rather than underscores in node names by renaming ctrl_sleep_moci-hog to ctrl-sleep-moci-hog. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index de811be435d0..599b620ae04d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -306,7 +306,7 @@ "SODIMM_151", "SODIMM_153"; - ctrl_sleep_moci-hog { + ctrl-sleep-moci-hog { gpio-hog; /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ gpios = <1 GPIO_ACTIVE_HIGH>; From 79c1c8509cbc3ce586fa7903cb1f9905b9f8326d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:44 +0100 Subject: [PATCH 169/791] arm64: dts: imx8mm-verdin: comment about i2c level shifter Add a note about the bootloader being expected to switch on the I2C level shifter for the TLA2024 ADC behind this PMIC. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 599b620ae04d..4542c99ce906 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -337,6 +337,11 @@ reg = <0x25>; sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /* + * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC + * behind this PMIC. + */ + regulators { reg_vdd_soc: BUCK1 { nxp,dvs-run-voltage = <850000>; From 60f01b5b5c7df32360329aea9b455d13b76d2a5f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:45 +0100 Subject: [PATCH 170/791] arm64: dts: imx8mm-verdin: update iomux configuration Update IOMUX configuration as required by the hardware design team. Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 304 +++++++++--------- 1 file changed, 152 insertions(+), 152 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 4542c99ce906..7976d055f17b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -781,34 +781,34 @@ pinctrl_can1_int: can1intgrp { fsl,pins = - ; /* CAN_1_SPI_INT#_1.8V */ + ; /* CAN_1_SPI_INT#_1.8V */ }; pinctrl_can2_int: can2intgrp { fsl,pins = - ; /* CAN_2_SPI_INT#_1.8V */ + ; /* CAN_2_SPI_INT#_1.8V, unused */ }; pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { fsl,pins = - ; /* SODIMM 256 */ + ; /* SODIMM 256 */ }; pinctrl_ecspi2: ecspi2grp { fsl,pins = - , /* SODIMM 196 */ - , /* SODIMM 200 */ - , /* SODIMM 198 */ - ; /* SODIMM 202 */ + , /* SODIMM 196 */ + , /* SODIMM 200 */ + , /* SODIMM 198 */ + ; /* SODIMM 202 */ }; pinctrl_ecspi3: ecspi3grp { fsl,pins = - , /* CAN_SPI_SCK_1.8V */ - , /* CAN_SPI_MOSI_1.8V */ - , /* CAN_SPI_MISO_1.8V */ - , /* CAN_1_SPI_CS_1.8V# */ - ; /* CAN_2_SPI_CS#_1.8V */ + , /* CAN_SPI_SCK_1.8V */ + , /* CAN_SPI_MOSI_1.8V */ + , /* CAN_SPI_MISO_1.8V */ + , /* CAN_1_SPI_CS_1.8V# */ + ; /* CAN_2_SPI_CS#_1.8V */ }; pinctrl_fec1: fec1grp { @@ -827,7 +827,7 @@ , , , - ; + ; }; pinctrl_fec1_sleep: fec1-sleepgrp { @@ -846,170 +846,170 @@ , , , - ; + ; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = - , /* SODIMM 52 */ - , /* SODIMM 54 */ - , /* SODIMM 64 */ - , /* SODIMM 66 */ - , /* SODIMM 56 */ - , /* SODIMM 58 */ - , /* SODIMM 60 */ - ; /* SODIMM 62 */ + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 64 */ + , /* SODIMM 66 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + ; /* SODIMM 62 */ }; pinctrl_gpio1: gpio1grp { fsl,pins = - ; /* SODIMM 206 */ + ; /* SODIMM 206 */ }; pinctrl_gpio2: gpio2grp { fsl,pins = - ; /* SODIMM 208 */ + ; /* SODIMM 208 */ }; pinctrl_gpio3: gpio3grp { fsl,pins = - ; /* SODIMM 210 */ + ; /* SODIMM 210 */ }; pinctrl_gpio4: gpio4grp { fsl,pins = - ; /* SODIMM 212 */ + ; /* SODIMM 212 */ }; pinctrl_gpio5: gpio5grp { fsl,pins = - ; /* SODIMM 216 */ + ; /* SODIMM 216 */ }; pinctrl_gpio6: gpio6grp { fsl,pins = - ; /* SODIMM 218 */ + ; /* SODIMM 218 */ }; pinctrl_gpio7: gpio7grp { fsl,pins = - ; /* SODIMM 220 */ + ; /* SODIMM 220 */ }; pinctrl_gpio8: gpio8grp { fsl,pins = - ; /* SODIMM 222 */ + ; /* SODIMM 222 */ }; /* Verdin GPIO_9_DSI (pulled-up as active-low) */ pinctrl_gpio_9_dsi: gpio9dsigrp { fsl,pins = - ; /* SODIMM 17 */ + ; /* SODIMM 17 */ }; - /* Verdin GPIO_10_DSI */ + /* Verdin GPIO_10_DSI (pulled-up as active-low) */ pinctrl_gpio_10_dsi: gpio10dsigrp { fsl,pins = - ; /* SODIMM 21 */ + ; /* SODIMM 21 */ }; pinctrl_gpio_hog1: gpiohog1grp { fsl,pins = - , /* SODIMM 88 */ - , /* SODIMM 90 */ - , /* SODIMM 92 */ - , /* SODIMM 94 */ - , /* SODIMM 96 */ - , /* SODIMM 100 */ - , /* SODIMM 102 */ - , /* SODIMM 104 */ - , /* SODIMM 106 */ - , /* SODIMM 108 */ - , /* SODIMM 112 */ - , /* SODIMM 114 */ - , /* SODIMM 116 */ - , /* SODIMM 118 */ - ; /* SODIMM 120 */ + , /* SODIMM 88 */ + , /* SODIMM 90 */ + , /* SODIMM 92 */ + , /* SODIMM 94 */ + , /* SODIMM 96 */ + , /* SODIMM 100 */ + , /* SODIMM 102 */ + , /* SODIMM 104 */ + , /* SODIMM 106 */ + , /* SODIMM 108 */ + , /* SODIMM 112 */ + , /* SODIMM 114 */ + , /* SODIMM 116 */ + , /* SODIMM 118 */ + ; /* SODIMM 120 */ }; pinctrl_gpio_hog2: gpiohog2grp { fsl,pins = - ; /* SODIMM 91 */ + ; /* SODIMM 91 */ }; pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = - , /* SODIMM 157 */ - ; /* SODIMM 187 */ + , /* SODIMM 157 */ + ; /* SODIMM 187 */ }; pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = - ; /* SODIMM 252 */ + ; /* SODIMM 252 */ }; /* On-module I2C */ pinctrl_i2c1: i2c1grp { fsl,pins = - , /* PMIC_I2C_SCL */ - ; /* PMIC_I2C_SDA */ + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = - , /* PMIC_I2C_SCL */ - ; /* PMIC_I2C_SDA */ + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ }; /* Verdin I2C_4_CSI */ pinctrl_i2c2: i2c2grp { fsl,pins = - , /* SODIMM 55 */ - ; /* SODIMM 53 */ + , /* SODIMM 55 */ + ; /* SODIMM 53 */ }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = - , /* SODIMM 55 */ - ; /* SODIMM 53 */ + , /* SODIMM 55 */ + ; /* SODIMM 53 */ }; /* Verdin I2C_2_DSI */ pinctrl_i2c3: i2c3grp { fsl,pins = - , /* SODIMM 95 */ - ; /* SODIMM 93 */ + , /* SODIMM 95 */ + ; /* SODIMM 93 */ }; pinctrl_i2c3_gpio: i2c3gpiogrp { fsl,pins = - , /* SODIMM 95 */ - ; /* SODIMM 93 */ + , /* SODIMM 95 */ + ; /* SODIMM 93 */ }; /* Verdin I2C_1 */ pinctrl_i2c4: i2c4grp { fsl,pins = - , /* SODIMM 14 */ - ; /* SODIMM 12 */ + , /* SODIMM 14 */ + ; /* SODIMM 12 */ }; pinctrl_i2c4_gpio: i2c4gpiogrp { fsl,pins = - , /* SODIMM 14 */ - ; /* SODIMM 12 */ + , /* SODIMM 14 */ + ; /* SODIMM 12 */ }; /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { fsl,pins = - ; /* SODIMM 42 */ + ; /* SODIMM 42 */ }; /* Verdin I2S_2_D_OUT shared with SAI5 */ pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { fsl,pins = - ; /* SODIMM 46 */ + ; /* SODIMM 46 */ }; pinctrl_pcie0: pcie0grp { @@ -1021,7 +1021,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = - ; /* PMIC_INT# */ + ; /* PMIC_INT# */ }; /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ @@ -1043,82 +1043,82 @@ /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { fsl,pins = - ; /* SODIMM 19 */ + ; /* SODIMM 19 */ }; pinctrl_reg_eth: regethgrp { fsl,pins = - ; /* PMIC_EN_ETH */ + ; /* PMIC_EN_ETH */ }; pinctrl_reg_usb1_en: regusb1engrp { fsl,pins = - ; /* SODIMM 155 */ + ; /* SODIMM 155 */ }; pinctrl_reg_usb2_en: regusb2engrp { fsl,pins = - ; /* SODIMM 185 */ + ; /* SODIMM 185 */ }; pinctrl_sai2: sai2grp { fsl,pins = - , /* SODIMM 32 */ - , /* SODIMM 30 */ - , /* SODIMM 38 */ - , /* SODIMM 36 */ - ; /* SODIMM 34 */ + , /* SODIMM 32 */ + , /* SODIMM 30 */ + , /* SODIMM 38 */ + , /* SODIMM 36 */ + ; /* SODIMM 34 */ }; pinctrl_sai5: sai5grp { fsl,pins = - , /* SODIMM 48 */ - , /* SODIMM 44 */ - , /* SODIMM 42 */ - ; /* SODIMM 46 */ + , /* SODIMM 48 */ + , /* SODIMM 44 */ + , /* SODIMM 42 */ + ; /* SODIMM 46 */ }; /* control signal for optional ATTPM20P or SE050 */ pinctrl_pmic_tpm_ena: pmictpmenagrp { fsl,pins = - ; /* PMIC_TPM_ENA */ + ; /* PMIC_TPM_ENA */ }; pinctrl_tsp: tspgrp { fsl,pins = - , /* SODIMM 148 */ - , /* SODIMM 152 */ - , /* SODIMM 154 */ - , /* SODIMM 174 */ - ; /* SODIMM 150 */ + , /* SODIMM 148 */ + , /* SODIMM 152 */ + , /* SODIMM 154 */ + , /* SODIMM 174 */ + ; /* SODIMM 150 */ }; pinctrl_uart1: uart1grp { fsl,pins = - , /* SODIMM 149 */ - ; /* SODIMM 147 */ + , /* SODIMM 149 */ + ; /* SODIMM 147 */ }; pinctrl_uart2: uart2grp { fsl,pins = - , /* SODIMM 129 */ - , /* SODIMM 131 */ - , /* SODIMM 133 */ - ; /* SODIMM 135 */ + , /* SODIMM 129 */ + , /* SODIMM 131 */ + , /* SODIMM 133 */ + ; /* SODIMM 135 */ }; pinctrl_uart3: uart3grp { fsl,pins = - , /* SODIMM 137 */ - , /* SODIMM 139 */ - , /* SODIMM 141 */ - ; /* SODIMM 143 */ + , /* SODIMM 137 */ + , /* SODIMM 139 */ + , /* SODIMM 141 */ + ; /* SODIMM 143 */ }; pinctrl_uart4: uart4grp { fsl,pins = - , /* SODIMM 151 */ - ; /* SODIMM 153 */ + , /* SODIMM 151 */ + ; /* SODIMM 153 */ }; pinctrl_usdhc1: usdhc1grp { @@ -1171,45 +1171,45 @@ pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = - ; /* SODIMM 84 */ + ; /* SODIMM 84 */ }; pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = - ; /* SODIMM 76 */ + ; /* SODIMM 76 */ }; pinctrl_usdhc2: usdhc2grp { fsl,pins = - , /* SODIMM 78 */ - , /* SODIMM 74 */ - , /* SODIMM 80 */ - , /* SODIMM 82 */ - , /* SODIMM 70 */ - , /* SODIMM 72 */ - ; + , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + , /* SODIMM 72 */ + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; }; /* @@ -1218,56 +1218,56 @@ */ pinctrl_usdhc3: usdhc3grp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_wdog: wdoggrp { fsl,pins = - ; /* PMIC_WDI */ + ; /* PMIC_WDI */ }; pinctrl_wifi_ctrl: wifictrlgrp { fsl,pins = - , /* WIFI_WKUP_BT */ - , /* WIFI_W_WKUP_HOST */ - ; /* WIFI_WKUP_WLAN */ + , /* WIFI_WKUP_BT */ + , /* WIFI_W_WKUP_HOST */ + ; /* WIFI_WKUP_WLAN */ }; pinctrl_wifi_i2s: bti2sgrp { fsl,pins = - , /* WIFI_TX_BCLK */ - , /* WIFI_TX_DATA0 */ - , /* WIFI_TX_SYNC */ - ; /* WIFI_RX_DATA0 */ + , /* WIFI_TX_BCLK */ + , /* WIFI_TX_DATA0 */ + , /* WIFI_TX_SYNC */ + ; /* WIFI_RX_DATA0 */ }; pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = - ; /* PMIC_EN_WIFI */ + ; /* PMIC_EN_WIFI */ }; }; From 593c535b0ddcc48325c1199549afcae74ccbfb96 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:46 +0100 Subject: [PATCH 171/791] arm64: dts: imx8mm-verdin: re-order pinctrl groups Alphabetically re-order pinctrl groups. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 92 +++++++++---------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 7976d055f17b..f188ac187c37 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -796,36 +796,36 @@ pinctrl_ecspi2: ecspi2grp { fsl,pins = - , /* SODIMM 196 */ - , /* SODIMM 200 */ , /* SODIMM 198 */ + , /* SODIMM 200 */ + , /* SODIMM 196 */ ; /* SODIMM 202 */ }; pinctrl_ecspi3: ecspi3grp { fsl,pins = + , /* CAN_2_SPI_CS#_1.8V */ , /* CAN_SPI_SCK_1.8V */ , /* CAN_SPI_MOSI_1.8V */ , /* CAN_SPI_MISO_1.8V */ - , /* CAN_1_SPI_CS_1.8V# */ - ; /* CAN_2_SPI_CS#_1.8V */ + ; /* CAN_1_SPI_CS_1.8V# */ }; pinctrl_fec1: fec1grp { fsl,pins = , , - , - , - , - , - , - , - , , - , + , + , + , , , + , + , + , + , + , , ; }; @@ -834,17 +834,17 @@ fsl,pins = , , - , - , - , - , - , - , - , , - , + , + , + , , , + , + , + , + , + , , ; }; @@ -854,11 +854,11 @@ , /* SODIMM 52 */ , /* SODIMM 54 */ , /* SODIMM 64 */ - , /* SODIMM 66 */ , /* SODIMM 56 */ , /* SODIMM 58 */ , /* SODIMM 60 */ - ; /* SODIMM 62 */ + , /* SODIMM 62 */ + ; /* SODIMM 66 */ }; pinctrl_gpio1: gpio1grp { @@ -1063,9 +1063,9 @@ pinctrl_sai2: sai2grp { fsl,pins = - , /* SODIMM 32 */ - , /* SODIMM 30 */ , /* SODIMM 38 */ + , /* SODIMM 30 */ + , /* SODIMM 32 */ , /* SODIMM 36 */ ; /* SODIMM 34 */ }; @@ -1095,23 +1095,23 @@ pinctrl_uart1: uart1grp { fsl,pins = - , /* SODIMM 149 */ - ; /* SODIMM 147 */ + , /* SODIMM 147 */ + ; /* SODIMM 149 */ }; pinctrl_uart2: uart2grp { fsl,pins = - , /* SODIMM 129 */ - , /* SODIMM 131 */ , /* SODIMM 133 */ - ; /* SODIMM 135 */ + , /* SODIMM 135 */ + , /* SODIMM 131 */ + ; /* SODIMM 129 */ }; pinctrl_uart3: uart3grp { fsl,pins = - , /* SODIMM 137 */ - , /* SODIMM 139 */ , /* SODIMM 141 */ + , /* SODIMM 139 */ + , /* SODIMM 137 */ ; /* SODIMM 143 */ }; @@ -1181,35 +1181,35 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = + , , /* SODIMM 78 */ , /* SODIMM 74 */ , /* SODIMM 80 */ , /* SODIMM 82 */ , /* SODIMM 70 */ - , /* SODIMM 72 */ - ; + ; /* SODIMM 72 */ }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = + , , , , , , - , - ; + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = + , , , , , , - , - ; + ; }; /* @@ -1218,32 +1218,32 @@ */ pinctrl_usdhc3: usdhc3grp { fsl,pins = - , - , , , , - ; + , + , + ; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = - , - , , , , - ; + , + , + ; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = - , - , , , , - ; + , + , + ; }; pinctrl_wdog: wdoggrp { From 473b34b8ce38f02b7b0c0272b90e30c99d8d4fdd Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:47 +0100 Subject: [PATCH 172/791] arm64: dts: imx8mm-verdin: capitalisation of verdin comments Fix capitalisation of Verdin in comments. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi index aca5ae0d307d..c2a5c2f7b204 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -114,7 +114,7 @@ status = "okay"; }; -/* VERDIN I2S_1 */ +/* Verdin I2S_1 */ &sai2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index f188ac187c37..6e1c762fd2e7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -668,7 +668,7 @@ #pwm-cells = <3>; }; -/* VERDIN I2S_1 */ +/* Verdin I2S_1 */ &sai2 { #sound-dai-cells = <0>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; From f84ccff6d8f34b7b1513411bcb172e8c903fc14e Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:48 +0100 Subject: [PATCH 173/791] arm64: dts: imx8mm-verdin: note about disabled sd1 pull-ups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a note about us using discrete external on-module resistors pulling-up to the on-module +V3.3_1.8_SD (LDO5) rail and explicitly disabling the internal pull-ups due to ERR050080 [1]: IO: Degradation of internal IO pullup/pulldown current capability for IO’s continuously driven in a 3.3V operating mode [1] https://www.nxp.com/webapp/Download?colCode=IMX8MM_0N87W Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 6e1c762fd2e7..97dd7a00d63b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -1179,6 +1179,10 @@ ; /* SODIMM 76 */ }; + /* + * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the + * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. + */ pinctrl_usdhc2: usdhc2grp { fsl,pins = , From 4f6b5de98560d27638dea2b43d9a97fa88b79e4b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:49 +0100 Subject: [PATCH 174/791] arm64: dts: imx8mm-verdin: add sd1 sleep pinctrl Add SD1 sleep pinctrl to avoid backfeeding during sleep. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 97dd7a00d63b..eafa88d980b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -757,10 +757,11 @@ bus-width = <4>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; }; @@ -1174,6 +1175,11 @@ ; /* SODIMM 84 */ }; + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = ; /* SODIMM 76 */ @@ -1216,6 +1222,18 @@ ; }; + /* Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + /* * On-module Wi-Fi/BT or type specific SDHC interface * (e.g. on X52 extension slot of Verdin Development Board) From be0b178c50c37a666d54f435da71cf9f008362a0 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 30 Mar 2022 13:33:29 +0200 Subject: [PATCH 175/791] arm64: dts: ls1028a: sl28: use ocelot-8021q tagging by default Enable the ocelot-8021q tagger by default which supports ethernet flow control. The new default is set in the common board dtsi. The actual switch node is enabled on a per board variant basis. Because of this we set the new tagger default for both internal ports and a particular variant is free to choose among the two port. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index c03f4e183389..0825c090ca95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -311,6 +311,14 @@ status = "okay"; }; +&mscc_felix_port4 { + dsa-tag-protocol = "ocelot-8021q"; +}; + +&mscc_felix_port5 { + dsa-tag-protocol = "ocelot-8021q"; +}; + &usb0 { status = "okay"; }; From 73d901d6dc6158e3a7474b184f319260a2ebc921 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 30 Mar 2022 13:34:42 +0200 Subject: [PATCH 176/791] arm64: dts: ls1028a: default to OTG mode for USB At the moment, the dtsi will force the dr_mode to host. This is problematic because it will always turn on the Vbus voltage regardless if the port is host or device. This might lead to a "shortcut" between the two USB endpoints because both might have their Vbus supplies enabled. Therefore, the default should be "otg" for any ports which aren't host only (from a SoC point of view) and have a user of the dtsi file overwrite that explicitly. Move the 'dr_mode = "host";' into the board dts. Now that the dtsi doesn't set the dr_mode anymore, we can also drop the 'dr_mode = "otg";' in the board dts because that is the default value if dr_mode is not set. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 1 + arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 -- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 0825c090ca95..4ab17b984b03 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -324,5 +324,6 @@ }; &usb1 { + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 19d3952dbffe..5baf060acf93 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -382,9 +382,11 @@ }; &usb0 { + dr_mode = "host"; status = "okay"; }; &usb1 { + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 68c31cb8eead..e0cd1516d05b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -299,10 +299,10 @@ }; &usb0 { + dr_mode = "host"; status = "okay"; }; &usb1 { - dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 088271d49139..92465f777603 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -599,7 +599,6 @@ compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; - dr_mode = "host"; snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; @@ -610,7 +609,6 @@ compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; - dr_mode = "host"; snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; From 7cbeeb0553615d4c8beaab36170f26b138f718ee Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 3 Apr 2022 00:38:55 +0530 Subject: [PATCH 177/791] arm64: dts: lx2160a: Update can node property fsl,clk-source property is of type uint8 and need to be defined as "/bits/ 8 <0>". Simply setting value to 0 raise warning: can@2180000: fsl,clk-source:0: [0, 0, 0, 0] is too long Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index c5daa15b020d..82bd8c0f318b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -909,7 +909,7 @@ QORIQ_CLK_PLL_DIV(8)>, <&clockgen QORIQ_CLK_SYSCLK 0>; clock-names = "ipg", "per"; - fsl,clk-source = <0>; + fsl,clk-source = /bits/ 8 <0>; status = "disabled"; }; @@ -921,7 +921,7 @@ QORIQ_CLK_PLL_DIV(8)>, <&clockgen QORIQ_CLK_SYSCLK 0>; clock-names = "ipg", "per"; - fsl,clk-source = <0>; + fsl,clk-source = /bits/ 8 <0>; status = "disabled"; }; From aba3a3fb8ebc8672288f287176286d39abcd7515 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:55 +0200 Subject: [PATCH 178/791] arm64: dts: freescale: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi | 2 +- .../boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index 10d2fe091965..6fab73d484b6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -104,21 +104,21 @@ &dspi { status = "okay"; - dflash0: n25q128a@0 { + dflash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; spi-max-frequency = <3000000>; reg = <0>; }; - dflash1: sst25wf040b@1 { + dflash1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; spi-max-frequency = <3000000>; reg = <1>; }; - dflash2: en25s64@2 { + dflash2: flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; @@ -129,7 +129,7 @@ &qspi { status = "okay"; - flash0: s25fl256s1@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; @@ -138,7 +138,7 @@ spi-tx-bus-width = <4>; reg = <0>; }; - flash2: s25fl256s1@2 { + flash2: flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi index 4b71c4fcb35f..f8135c5c252d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi @@ -100,7 +100,7 @@ &dspi { status = "okay"; - dflash0: n25q512a@0 { + dflash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi index 7c4af71baab9..0dbdc9ec3fe5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi @@ -98,7 +98,7 @@ pinctrl-1 = <&pinctrl_flexspi1>; status = "okay"; - flash0: spi-flash@0 { + flash0: flash@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 22a5ef771d4e..8f90eb02550d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -66,7 +66,7 @@ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; spi-max-frequency = <80000000>; reg = <0>; From a00f1fa615803cfe5eeb834fc411ab6c560b1952 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 8 Apr 2022 16:57:23 +0200 Subject: [PATCH 179/791] arm64: dts: imx8mp: add uart2 dma Add DMA properties to uart2 node. Signed-off-by: Marcel Ziswiler Reviewed-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 2c207bc27d70..c42d25bd16ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -693,6 +693,8 @@ clocks = <&clk IMX8MP_CLK_UART2_ROOT>, <&clk IMX8MP_CLK_UART2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; From a39ed23bdf6ec7eb0f093b6ef0391e1f3d152f71 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 8 Apr 2022 16:57:25 +0200 Subject: [PATCH 180/791] arm64: dts: freescale: add initial support for verdin imx8m plus This patch adds the device tree to support Toradex Verdin iMX8M Plus [1] a computer on module which can be used on different carrier boards. The module consists of an NXP i.MX 8M Plus family SoC (either i.MX 8M Plus Quad or 8M Plus QuadLite), a PCA9450C PMIC, a Gigabit Ethernet PHY, 1, 2, 4 or 8 GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, an optional I2C temperature sensor plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. The device tree for the Dahlia includes the module's device tree and enables the supported peripherals of the carrier board. The device tree for the Verdin Development Board includes the module's device tree as well as the Dahlia one as it is a superset and supports almost all peripherals available. So far there is no display functionality supported at all but basic console UART, USB host, eMMC and Ethernet functionality work fine. [1] https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus Signed-off-by: Marcel Ziswiler Reviewed-by: Laurent Pinchart Tested-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../dts/freescale/imx8mp-verdin-dahlia.dtsi | 129 ++ .../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 46 + .../imx8mp-verdin-nonwifi-dahlia.dts | 18 + .../freescale/imx8mp-verdin-nonwifi-dev.dts | 18 + .../dts/freescale/imx8mp-verdin-nonwifi.dtsi | 54 + .../freescale/imx8mp-verdin-wifi-dahlia.dts | 18 + .../dts/freescale/imx8mp-verdin-wifi-dev.dts | 18 + .../dts/freescale/imx8mp-verdin-wifi.dtsi | 82 + .../boot/dts/freescale/imx8mp-verdin.dtsi | 1380 +++++++++++++++++ 10 files changed, 1767 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 52ce0f798657..85c2c9ba5110 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -79,6 +79,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi new file mode 100644 index 000000000000..4b8f86f63081 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/* TODO: Audio Codec */ + +&backlight { + power-supply = <®_3p3v>; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + status = "okay"; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&eqos { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&hwmon_temp { + vs-supply = <®_1p8v>; + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; + + /* TODO: Audio Codec */ +}; + +/* TODO: Verdin PCIE_1 */ + +/* Verdin PWM_1 */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm3 { + status = "okay"; +}; + +®_usdhc2_vmmc { + vin-supply = <®_3p3v>; +}; + +/* TODO: Verdin I2S_1 */ + +/* Verdin UART_1 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux Console */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3_1 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi new file mode 100644 index 000000000000..cefabe65b252 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8mp-verdin-dahlia.dtsi" + +/ { + /* TODO: Audio Codec */ + + reg_eth2phy: regulator-eth2phy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */ + off-on-delay = <500000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + startup-delay-us = <200000>; + vin-supply = <®_3p3v>; + }; +}; + +&fec { + phy-supply = <®_eth2phy>; + status = "okay"; +}; + +&gpio_expander_21 { + status = "okay"; + vcc-supply = <®_1p8v>; +}; + +/* TODO: Verdin I2C_1 with Audio Codec */ + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&uart1 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +}; + +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..68147b0c1b35 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-nonwifi.dtsi" +#include "imx8mp-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus on Dahlia Board"; + compatible = "toradex,verdin-imx8mp-nonwifi-dahlia", + "toradex,verdin-imx8mp-nonwifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..879ff687cf2b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-nonwifi.dtsi" +#include "imx8mp-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus on Verdin Development Board"; + compatible = "toradex,verdin-imx8mp-nonwifi-dev", + "toradex,verdin-imx8mp-nonwifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..91d597391b7c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +&gpio5 { + gpio-line-names = "SODIMM_42", + "SODIMM_46", + "SODIMM_187", + "SODIMM_20", + "SODIMM_22", + "SODIMM_15", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "SODIMM_164", + "SODIMM_152", + "SODIMM_116", + "SODIMM_128", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "SODIMM_129", + "SODIMM_131", + "SODIMM_137", + "SODIMM_139", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, + <&pinctrl_hdmi_hog>; +}; + +/* + * Verdin UART_4 + * Often used by the M7 and then should not be enabled here. + */ +&uart4 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..804567f6ccee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-wifi.dtsi" +#include "imx8mp-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus WB on Dahlia Board"; + compatible = "toradex,verdin-imx8mp-wifi-dahlia", + "toradex,verdin-imx8mp-wifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts new file mode 100644 index 000000000000..c1713c28cdce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-wifi.dtsi" +#include "imx8mp-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus WB on Verdin Development Board"; + compatible = "toradex,verdin-imx8mp-wifi-dev", + "toradex,verdin-imx8mp-wifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi new file mode 100644 index 000000000000..34d9bc48c899 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_AW-CM276NF"; + startup-delay-us = <2000>; + }; +}; + +&gpio5 { + gpio-line-names = "SODIMM_42", + "SODIMM_46", + "SODIMM_187", + "SODIMM_20", + "SODIMM_22", + "SODIMM_15", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "", + "", + "", + "", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "SODIMM_129", + "SODIMM_131", + "SODIMM_137", + "SODIMM_139", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>, + <&pinctrl_hdmi_hog>; +}; + +/* On-module Bluetooth */ +&uart4 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + status = "okay"; +}; + +/* On-module Wi-Fi */ +&usdhc1 { + bus-width = <4>; + keep-power-in-suspend; + max-frequency = <100000000>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi new file mode 100644 index 000000000000..aa6442be130e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -0,0 +1,1380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "imx8mp.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + aliases { + /* Ethernet aliases to ensure correct MAC addresses */ + ethernet0 = &eqos; + ethernet1 = &fec; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ + pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + backlight_mezzanine: backlight-mezzanine { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin GPIO 4 (SODIMM 212) */ + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + /* Verdin PWM_2 (SODIMM 16) */ + pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + /* Carrier Board Supplies */ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "+V5_SW"; + }; + + /* Non PMIC On-module Supplies */ + reg_module_eth1phy: regulator-module-eth1phy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ + off-on-delay = <500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3_ETH"; + startup-delay-us = <200000>; + vin-supply = <®_vdd_3v3>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_1_EN (SODIMM 155) */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_2_EN (SODIMM 185) */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_2_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + off-on-delay = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Use the kernel configuration settings instead */ + /delete-node/ linux,cma; + }; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + phy-supply = <®_module_eth1phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + eee-broken-100tx; + eee-broken-1000t; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; +}; + +/* Verdin ETH_2_RGMII */ +&fec { + fsl,magic-packet; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + + +/* Verdin CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; +}; + +&gpio1 { + gpio-line-names = "SODIMM_206", + "SODIMM_208", + "", + "", + "", + "SODIMM_210", + "SODIMM_212", + "SODIMM_216", + "SODIMM_218", + "", + "", + "SODIMM_16", + "SODIMM_155", + "SODIMM_157", + "SODIMM_185", + "SODIMM_91"; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "SODIMM_143", + "SODIMM_141", + "", + "", + "SODIMM_161", + "", + "SODIMM_84", + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72"; + + ctrl-sleep-moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + }; +}; + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "", + "", + "", + "", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", + "SODIMM_66", + "", + "SODIMM_64", + "", + "", + "SODIMM_34", + "SODIMM_19", + "", + "SODIMM_32", + "", + "", + "SODIMM_30", + "SODIMM_59", + "SODIMM_57", + "SODIMM_63", + "SODIMM_61"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_252", + "SODIMM_222", + "SODIMM_36", + "SODIMM_220", + "SODIMM_193", + "SODIMM_191", + "SODIMM_201", + "SODIMM_203", + "SODIMM_205", + "SODIMM_207", + "SODIMM_199", + "SODIMM_197", + "SODIMM_221", + "SODIMM_219", + "SODIMM_217", + "SODIMM_215", + "SODIMM_211", + "SODIMM_213", + "SODIMM_189", + "SODIMM_244", + "SODIMM_38", + "", + "SODIMM_76", + "SODIMM_135", + "SODIMM_133", + "SODIMM_17", + "SODIMM_24", + "SODIMM_26", + "SODIMM_21", + "SODIMM_256", + "SODIMM_48", + "SODIMM_44"; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + interrupt-parent = <&gpio1>; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x25>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + /* + * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the + * I2C level shifter for the TLA2024 ADC behind this PMIC. + */ + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <720000>; + regulator-name = "On-module +VDD_SOC (BUCK1)"; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1025000>; + regulator-min-microvolt = <720000>; + regulator-name = "On-module +VDD_ARM (BUCK2)"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3 (BUCK4)"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PWR_1V8_MOCI (BUCK5)"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "On-module +VDD_DDR (BUCK6)"; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "On-module +V1.8_SNVS (LDO1)"; + }; + + LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + regulator-name = "On-module +V0.8_SNVS (LDO2)"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8A (LDO3)"; + }; + + LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3_ADC (LDO4)"; + }; + + LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + /* On-module temperature sensor */ + hwmon_temp_module: sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + vs-supply = <®_vdd_1v8>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin I2C_1 (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ + clock-frequency = <10000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + atmel_mxt_ts_mezzanine: touch-mezzanine@4a { + compatible = "atmel,maxtouch"; + /* Verdin GPIO_3 (SODIMM 210) */ + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reg = <0x4a>; + /* Verdin GPIO_2 (SODIMM 208) */ + reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +/* TODO: Verdin I2C_3_HDMI */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + vcc-supply = <®_3p3v>; + status = "disabled"; + }; + + lvds_ti_sn65dsi83: bridge@2c { + compatible = "ti,sn65dsi83"; + /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + reg = <0x2c>; + status = "disabled"; + }; + + /* Current measurement into module VCC */ + hwmon: hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "disabled"; + }; + + hdmi_lontium_lt8912: hdmi@48 { + compatible = "lontium,lt8912b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; + reg = <0x48>; + /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + atmel_mxt_ts: touch@4a { + compatible = "atmel,maxtouch"; + /* + * Verdin GPIO_9_DSI + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + */ + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + reg = <0x4a>; + /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ + reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + /* Temperature sensor on carrier board */ + hwmon_temp: sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + status = "disabled"; + }; + + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + status = "disabled"; + }; + + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + status = "disabled"; + }; +}; + +/* TODO: Verdin PCIE_1 */ + +/* Verdin PWM_1 */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_1>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_2 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_3_DSI */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; +}; + +/* TODO: Verdin I2S_1 */ + +/* TODO: Verdin I2S_2 */ + +&snvs_pwrkey { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_3, used as the Linux Console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +/* Verdin USB_1 */ +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; +}; + +&usb_dwc3_0 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + maximum-speed = "high-speed"; + over-current-active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_id>; + srp-disable; +}; + +/* Verdin USB_2 */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; +}; + +&usb_dwc3_1 { + disable-over-current; + dr_mode = "host"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; + vmmc-supply = <®_usdhc2_vmmc>; +}; + +/* On-module eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + status = "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt_uart: btuartgrp { + fsl,pins = + , + , + , + ; + }; + + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = + ; /* SODIMM 256 */ + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = + , /* SODIMM 198 */ + , /* SODIMM 200 */ + , /* SODIMM 196 */ + ; /* SODIMM 202 */ + }; + + /* Connection On Board PHY */ + pinctrl_eqos: eqosgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + /* ETH_INT# shared with TPM_INT# (usually N/A) */ + pinctrl_eth_tpm_int: ethtpmintgrp { + fsl,pins = + ; + }; + + /* Connection Carrier Board PHY ETH_2 */ + pinctrl_fec: fecgrp { + fsl,pins = + , /* SODIMM 193 */ + , /* SODIMM 191 */ + , /* SODIMM 201 */ + , /* SODIMM 203 */ + , /* SODIMM 205 */ + , /* SODIMM 207 */ + , /* SODIMM 197 */ + , /* SODIMM 199 */ + , /* SODIMM 221 */ + , /* SODIMM 219 */ + , /* SODIMM 217 */ + , /* SODIMM 215 */ + , /* SODIMM 211 */ + , /* SODIMM 213 */ + ; /* SODIMM 189 */ + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = + , /* SODIMM 193 */ + , /* SODIMM 191 */ + , /* SODIMM 201 */ + , /* SODIMM 203 */ + , /* SODIMM 205 */ + , /* SODIMM 207 */ + , /* SODIMM 197 */ + , /* SODIMM 199 */ + , /* SODIMM 221 */ + , /* SODIMM 219 */ + , /* SODIMM 217 */ + , /* SODIMM 215 */ + , /* SODIMM 211 */ + , /* SODIMM 213 */ + ; /* SODIMM 189 */ + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = + , /* SODIMM 22 */ + ; /* SODIMM 20 */ + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = + , /* SODIMM 26 */ + ; /* SODIMM 24 */ + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 66 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + , /* SODIMM 62 */ + ; /* SODIMM 64 */ + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = + ; /* SODIMM 206 */ + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = + ; /* SODIMM 208 */ + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = + ; /* SODIMM 210 */ + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = + ; /* SODIMM 212 */ + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = + ; /* SODIMM 216 */ + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = + ; /* SODIMM 218 */ + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = + ; /* SODIMM 220 */ + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = + ; /* SODIMM 222 */ + }; + + /* Verdin GPIO_9_DSI (pulled-up as active-low) */ + pinctrl_gpio_9_dsi: gpio9dsigrp { + fsl,pins = + ; /* SODIMM 17 */ + }; + + /* Verdin GPIO_10_DSI */ + pinctrl_gpio_10_dsi: gpio10dsigrp { + fsl,pins = + ; /* SODIMM 21 */ + }; + + /* Non-wifi MSP usage only */ + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = + , /* SODIMM 116 */ + , /* SODIMM 152 */ + , /* SODIMM 164 */ + ; /* SODIMM 128 */ + }; + + /* USB_2_OC# */ + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = + ; /* SODIMM 187 */ + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = + , /* SODIMM 157 */ + /* CSI_1_MCLK */ + ; /* SODIMM 91 */ + }; + + /* Wifi usage only */ + pinctrl_gpio_hog4: gpiohog4grp { + fsl,pins = + , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = + ; /* SODIMM 252 */ + }; + + pinctrl_hdmi_hog: hdmihoggrp { + fsl,pins = + , /* SODIMM 63 */ + , /* SODIMM 59 */ + , /* SODIMM 57 */ + ; /* SODIMM 61 */ + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ + pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { + fsl,pins = + ; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_OUT shared with SAI3 */ + pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { + fsl,pins = + ; /* SODIMM 46 */ + }; + + pinctrl_pcie: pciegrp { + fsl,pins = + , /* SODIMM 244 */ + ; /* PMIC_EN_PCIe_CLK, unused */ + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = + ; /* PMIC_INT# */ + }; + + pinctrl_pwm_1: pwm1grp { + fsl,pins = + ; /* SODIMM 15 */ + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = + ; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ + pinctrl_pwm_3: pwm3grp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ + pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = + ; /* PMIC_EN_ETH */ + }; + + pinctrl_sai1: sai1grp { + fsl,pins = + , /* SODIMM 38 */ + , /* SODIMM 36 */ + , /* SODIMM 30 */ + , /* SODIMM 32 */ + ; /* SODIMM 34 */ + }; + + pinctrl_sai3: sai3grp { + fsl,pins = + , /* SODIMM 48 */ + , /* SODIMM 42 */ + , /* SODIMM 46 */ + ; /* SODIMM 44 */ + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , /* SODIMM 135 */ + , /* SODIMM 133 */ + , /* SODIMM 129 */ + ; /* SODIMM 131 */ + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + , /* SODIMM 143 */ + , /* SODIMM 141 */ + , /* SODIMM 137 */ + ; /* SODIMM 139 */ + }; + + pinctrl_uart3: uart3grp { + fsl,pins = + , /* SODIMM 147 */ + ; /* SODIMM 149 */ + }; + + /* Non-wifi usage only */ + pinctrl_uart4: uart4grp { + fsl,pins = + , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + pinctrl_usb1_vbus: usb1vbusgrp { + fsl,pins = + ; /* SODIMM 155 */ + }; + + /* USB_1_ID */ + pinctrl_usb_1_id: usb1idgrp { + fsl,pins = + ; /* SODIMM 161 */ + }; + + pinctrl_usb2_vbus: usb2vbusgrp { + fsl,pins = + ; /* SODIMM 185 */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = + ; /* SODIMM 76 */ + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , /* PMIC_USDHC_VSELECT */ + , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + /* Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = + ; /* PMIC_WDI */ + }; + + pinctrl_bluetooth_ctrl: bluetoothctrlgrp { + fsl,pins = + ; /* WIFI_WKUP_BT */ + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = + ; /* WIFI_WKUP_WLAN */ + }; + + pinctrl_wifi_i2s: wifii2sgrp { + fsl,pins = + , /* WIFI_TX_SYNC */ + , /* WIFI_RX_DATA0 */ + , /* WIFI_TX_BCLK */ + ; /* WIFI_TX_DATA0 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = + ; /* PMIC_EN_WIFI */ + }; +}; From 3d397a1277853498e8b7b305f2610881357c033f Mon Sep 17 00:00:00 2001 From: Thorsten Scherer Date: Wed, 6 Apr 2022 06:39:45 +0200 Subject: [PATCH 181/791] ARM: dts: ci4x10: Adapt to changes in imx6qdl.dtsi regarding fec clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit f3e7dae323ab ("ARM: dts: imx6qdl: add enet_out clk support") added another item to the list of clocks for the fec device. As imx6dl-eckelmann-ci4x10.dts only overwrites clocks, but not clock-names this resulted in an inconsistency with clocks having one item more than clock-names. Also overwrite clock-names with the same value as in imx6qdl.dtsi. This is a no-op today, but prevents similar inconsistencies if the soc file will be changed in a similar way in the future. Signed-off-by: Thorsten Scherer Reviewed-by: Uwe Kleine-König Fixes: f3e7dae323ab ("ARM: dts: imx6qdl: add enet_out clk support") Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts index b4a9523e325b..864dc5018451 100644 --- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -297,7 +297,11 @@ phy-mode = "rmii"; phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; phy-handle = <&phy>; - clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&rmii_clk>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; status = "okay"; mdio { From ba9fe460dc2cfe90dc115b22af14dd3f13cffa0f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:54 +0200 Subject: [PATCH 182/791] ARM: dts: imx: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 2 +- arch/arm/boot/dts/imx28-m28evk.dts | 2 +- arch/arm/boot/dts/imx28-sps1.dts | 2 +- arch/arm/boot/dts/imx6dl-rex-basic.dts | 2 +- arch/arm/boot/dts/imx6q-ba16.dtsi | 2 +- arch/arm/boot/dts/imx6q-bx50v3.dtsi | 2 +- arch/arm/boot/dts/imx6q-cm-fx6.dts | 2 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-dms-ba16.dts | 2 +- arch/arm/boot/dts/imx6q-gw5400-a.dts | 2 +- arch/arm/boot/dts/imx6q-marsboard.dts | 2 +- arch/arm/boot/dts/imx6q-rex-pro.dts | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 +- arch/arm/boot/dts/imx6sl-evk.dts | 2 +- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 2 +- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 4 ++-- arch/arm/boot/dts/imx6sx-sdb.dts | 4 ++-- arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi | 2 +- arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi | 2 +- 32 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 7e2b0f198dfa..1053b7c584d8 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -129,7 +129,7 @@ pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index f3bddc5ada4b..13acdc7916b9 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -33,7 +33,7 @@ pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 43be7a6a769b..90928db0df70 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -51,7 +51,7 @@ pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "everspin,mr25h256", "mr25h256"; diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts index 0f1616bfa9a8..b72f8ea1e6f6 100644 --- a/arch/arm/boot/dts/imx6dl-rex-basic.dts +++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts @@ -19,7 +19,7 @@ }; &ecspi3 { - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index 6330d75f8f39..f266f1b7e0cf 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -142,7 +142,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: n25q032@0 { + flash: flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 10922375c51e..ead83091e193 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -160,7 +160,7 @@ pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: m25p80@0 { + m25_eeprom: flash@0 { compatible = "atmel,at25"; spi-max-frequency = <10000000>; size = <0x8000>; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index bfb530f29d9d..1ad41c944b4b 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -260,7 +260,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index c713ac03b3b9..9591848cbd37 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -102,7 +102,7 @@ cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "m25p80", "jedec,spi-nor"; spi-max-frequency = <40000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts index 48fb47e715f6..137db38f0d27 100644 --- a/arch/arm/boot/dts/imx6q-dms-ba16.dts +++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts @@ -47,7 +47,7 @@ pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: m25p80@0 { + m25_eeprom: flash@0 { compatible = "atmel,at25256B", "atmel,at25"; spi-max-frequency = <20000000>; size = <0x8000>; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 4cde45d5c90c..e894faba571f 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -137,7 +137,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,w25q256", "jedec,spi-nor"; spi-max-frequency = <30000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts index 05ee28388229..cc1801002394 100644 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -100,7 +100,7 @@ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts index 1767e1a3cd53..271f4b2d9b9f 100644 --- a/arch/arm/boot/dts/imx6q-rex-pro.dts +++ b/arch/arm/boot/dts/imx6q-rex-pro.dts @@ -19,7 +19,7 @@ }; &ecspi3 { - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf032b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index e21f6ac864e5..baa197c90060 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -96,7 +96,7 @@ pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index 563bf9d44fe0..2ba577e602e7 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -131,7 +131,7 @@ pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; - flash: m25p80@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index 648f5fcb72e6..2c1d6f28e695 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -35,7 +35,7 @@ pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf040b", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index b167b33bd108..095c9143d99a 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -258,7 +258,7 @@ status = "okay"; /* default boot source: workaround #1 for errata ERR006282 */ - smarc_flash: spi-flash@0 { + smarc_flash: flash@0 { compatible = "winbond,w25q16dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index ac34709e9741..0ad4cb4f1e82 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -179,7 +179,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index c96f4d7e1e0d..beaa2dcd436c 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -321,7 +321,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 92d09a3ebe0e..ee7e2371f94b 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -252,7 +252,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 49da30d7510c..904d5d051d63 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -237,7 +237,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 5e58740d40c5..1368a4762037 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -272,7 +272,7 @@ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "disabled"; /* pin conflict with WEIM NOR */ - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index eb9a0b104f1c..901b9a761b66 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -313,7 +313,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0c0105468a2f..37482a9023fc 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -197,7 +197,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 25f6f2fb1555..f16c830f1e91 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -137,7 +137,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 66af78e83b70..a2c79bcf9a11 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -107,7 +107,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index dce5dcf96c25..7dda42553f4b 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -123,7 +123,7 @@ pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; - flash0: s25fl128s@0 { + flash0: flash@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; @@ -133,7 +133,7 @@ spi-tx-bus-width = <4>; }; - flash1: s25fl128s@2 { + flash1: flash@2 { reg = <2>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 99f4cf777a38..969cfe920d25 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -108,7 +108,7 @@ pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; - flash0: n25q256a@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; @@ -118,7 +118,7 @@ reg = <0>; }; - flash1: n25q256a@2 { + flash1: flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index a3fde3316c73..1a18c41ce385 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -286,7 +286,7 @@ pinctrl-0 = <&pinctrl_qspi>; status = "okay"; - flash0: n25q256a@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi index 47d3ce5d255f..acd936540d89 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi @@ -19,7 +19,7 @@ }; &qspi { - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-nand"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi index a095a7654ac6..29ed38dce580 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi @@ -18,7 +18,7 @@ }; &qspi { - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-nand"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi index 2a449a3c1ae2..09a83dbdf651 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -19,7 +19,7 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi index b7e984284e1a..d000606c0704 100644 --- a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi +++ b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi @@ -18,7 +18,7 @@ }; &qspi { - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-nand"; From bd04437341962d4bff32a8410d69c4ab974c86d1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Feb 2022 16:26:47 +0100 Subject: [PATCH 183/791] arm64: dts: renesas: r8a779f0: Add I2C nodes Add device nodes for the I2C Bus Interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/e1c7fb17801bc82a74aa5364212d02ba51535dd2.1643898884.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 102 ++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index f4e549867371..ab0856b7a2bd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -96,6 +96,108 @@ #power-domain-cells = <1>; }; + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac0 0x91>, <&dmac0 0x90>, + <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac0 0x93>, <&dmac0 0x92>, + <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac0 0x95>, <&dmac0 0x94>, + <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>, + <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>, + <&dmac1 0x99>, <&dmac1 0x98>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, + <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; From b74d5d65afce4332b2c781c4b252ff9af4885b1f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Feb 2022 16:26:48 +0100 Subject: [PATCH 184/791] arm64: dts: renesas: spider-cpu: Add I2C4 and EEPROMs Enable the I2C4 bus on the Falcon CPU board, and describe the I2C EEPROMs present on the Spider CPU and BreakOut boards. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/6d8917e49f83b6a932970ca169100eb086d11f16.1643898884.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 20 +++++++++++++++++++ .../boot/dts/renesas/r8a779f0-spider.dts | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 6e07c54148e7..41aa8591b3b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -31,10 +31,30 @@ clock-frequency = <32768>; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + scif3_pins: scif3 { groups = "scif3_data", "scif3_ctrl"; function = "scif3"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index f286254b41d8..78c4730538fd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -20,3 +20,12 @@ stdout-path = "serial0:115200n8"; }; }; + +&i2c4 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; From 599fdfddc8fcdde92b41444613549ff99cff7adb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Feb 2022 16:26:49 +0100 Subject: [PATCH 185/791] arm64: dts: renesas: spider: Add Ethernet sub-board Add a DTS file for the Spider Ether TSN sub-board (RTP8A779F0ASKB0ST0S), and include it from the main r8a779f0-spider.dts. For now its contents are limited to the Board ID EEPROM. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/5aa58816182b34d9e5795bc1e22784f4e4879d13.1643898884.git.geert+renesas@glider.be --- .../dts/renesas/r8a779f0-spider-ethernet.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider.dts | 1 + 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi new file mode 100644 index 000000000000..15e8d1ebf575 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Spider Ethernet sub-board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +&i2c4 { + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board"; + reg = <0x52>; + pagesize = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index 78c4730538fd..2e3b719cc749 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r8a779f0-spider-cpu.dtsi" +#include "r8a779f0-spider-ethernet.dtsi" / { model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; From 456733feb0da2dbb1288b9e8f5765df163620c2c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 9 Apr 2022 06:42:57 +0000 Subject: [PATCH 186/791] arm64: dts: meson: alpa sort the board Makefile Let's alpha-sort the board Makefile to keep things organised. Signed-off-by: Christian Hewitt Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220409064257.24453-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/Makefile | 40 ++++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 0eec18678311..8773211df50e 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,17 +1,18 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb @@ -19,29 +20,29 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb @@ -52,15 +53,14 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb From 26ad4834da921ffcadad3ba177dbb137d36c9248 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 13:23:35 +0200 Subject: [PATCH 187/791] dt-bindings: omap: Add clock-output-names and #clock-cells This allows us to use clock-output-names for the clock manager instance name instead of relying on non-standard node names. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Acked-by: Rob Herring Message-Id: <20220203112337.19821-1-tony@atomide.com> --- Documentation/devicetree/bindings/arm/omap/prcm.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 3eb6d7afff14..431ef8c56a13 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -31,12 +31,17 @@ Required properties: (base address and length) - clocks: clocks for this module - clockdomains: clockdomains for this module +- #clock-cells: From common clock binding +- clock-output-names: From common clock binding + Example: -cm: cm@48004000 { +cm: clock@48004000 { compatible = "ti,omap3-cm"; reg = <0x48004000 0x4000>; + #clock-cells = <0>; + clock-output-names = "cm"; cm_clocks: clocks { #address-cells = <1>; From 8ab423081a263cc84f4377d518d98330d4f78072 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 13:23:36 +0200 Subject: [PATCH 188/791] dt-bindings: clock: ti: Add clock-output-names for clockctrl This allows us to use clock-output-names for the clockctrl instance name instead of relying on a custom compatible or non-standard node names. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Acked-by: Rob Herring Message-Id: <20220203112337.19821-2-tony@atomide.com> --- Documentation/devicetree/bindings/clock/ti-clkctrl.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt index 18af6b9409e3..d20db7974a38 100644 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt @@ -21,6 +21,7 @@ Required properties : "ti,clkctrl-l4-per" "ti,clkctrl-l4-secure" "ti,clkctrl-l4-wkup" +- clock-output-names : from common clock binding - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index @@ -32,7 +33,8 @@ Example: Clock controller node on omap 4430: l4per: cm@1400 { cm_l4per@0 { cm_l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; From fc3d39d5758dc001662df5aac825b2b6bcb6476f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 13:23:37 +0200 Subject: [PATCH 189/791] dt-bindings: clock: ti: Add clock-output-names for TI composite clocks For the TI composite clocks, we currently have only the divider clock list clock-output-names as an optional devicetree property. Let's add clock-output-names for all the TI composite clock bindings. This allows us to use clock-output-names for the clockctrl instance name instead of relying on a custom compatible or non-standard node names. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Acked-by: Rob Herring Message-Id: <20220203112337.19821-3-tony@atomide.com> --- Documentation/devicetree/bindings/clock/ti/clockdomain.txt | 3 +++ Documentation/devicetree/bindings/clock/ti/composite.txt | 3 +++ .../devicetree/bindings/clock/ti/fixed-factor-clock.txt | 1 + Documentation/devicetree/bindings/clock/ti/gate.txt | 1 + Documentation/devicetree/bindings/clock/ti/interface.txt | 1 + Documentation/devicetree/bindings/clock/ti/mux.txt | 1 + 6 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt index cb76b3f2b341..9c6199249ce5 100644 --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt @@ -17,6 +17,9 @@ Required properties: - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of clocks within this domain +Optional properties: +- clock-output-names : from common clock binding. + Examples: dss_clkdm: dss_clkdm { compatible = "ti,clockdomain"; diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt index 5f43c4706b09..33ac7c9ad053 100644 --- a/Documentation/devicetree/bindings/clock/ti/composite.txt +++ b/Documentation/devicetree/bindings/clock/ti/composite.txt @@ -27,6 +27,9 @@ Required properties: - clocks : link phandles of component clocks - #clock-cells : from common clock binding; shall be set to 0. +Optional properties: +- clock-output-names : from common clock binding. + Examples: usb_l4_gate_ick: usb_l4_gate_ick { diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt index 662b36d53bf0..518e3c142276 100644 --- a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt +++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt @@ -16,6 +16,7 @@ Required properties: - clocks: parent clock. Optional properties: +- clock-output-names : from common clock binding. - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock, see [2] - reg: offset for the autoidle register of this clock, see [2] diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt index 56d603c1f716..b4820b1de4f0 100644 --- a/Documentation/devicetree/bindings/clock/ti/gate.txt +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt @@ -36,6 +36,7 @@ Required properties: ti,clkdm-gate-clock type Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for programming the clock gate, invalid for ti,clkdm-gate-clock type - ti,set-bit-to-disable : inverts default gate programming. Setting the bit diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt index 3f4704040140..94ec77dc3c59 100644 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt @@ -28,6 +28,7 @@ Required properties: - reg : base address for the control register Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) Examples: diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt index eec8994b9be8..e17425a58621 100644 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ b/Documentation/devicetree/bindings/clock/ti/mux.txt @@ -42,6 +42,7 @@ Required properties: - reg : register offset for register controlling adjustable mux Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : number of bits to shift the bit-mask, defaults to 0 if not present - ti,index-starts-at-one : valid input select programming starts at 1, not From c2f2646057bcf3f86a75f6a8aa9fbd159a1d4784 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:33:30 +0200 Subject: [PATCH 190/791] ARM: dts: Add clksel node for am3 ehrpwm Let's add a clksel node for the component clocks to avoid devicetree unique_unit_address warnings. The component clocks can now get IO address from the parent clksel node. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204073333.18175-2-tony@atomide.com> --- arch/arm/boot/dts/am33xx-clocks.dtsi | 47 ++++++++++++++++------------ 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index b7b7106f2dee..e90f148c323c 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -93,28 +93,35 @@ clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; + clock@664 { + compatible = "ti,clksel"; + reg = <0x664>; + #clock-cells = <2>; + #address-cells = <0>; - ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; + ehrpwm0_tbclk: clock-ehrpwm0-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <0>; + }; - ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; + ehrpwm1_tbclk: clock-ehrpwm1-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <1>; + }; + + ehrpwm2_tbclk: clock-ehrpwm2-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <2>; + }; }; }; &prcm_clocks { From 00950028d0796f2f130a6bb04903fe91b988b4e7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:33:31 +0200 Subject: [PATCH 191/791] ARM: dts: Add clksel node for am3 gfx Let's add a clksel node for the component clocks to avoid devicetree unique_unit_address warnings. The component clocks can now get IO address from the parent clksel node. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204073333.18175-3-tony@atomide.com> --- arch/arm/boot/dts/am33xx-clocks.dtsi | 33 +++++++++++++++++----------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index e90f148c323c..a70ce9f3fb27 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -501,20 +501,27 @@ clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x052c>; - }; + clock@52c { + compatible = "ti,clksel"; + reg = <0x52c>; + #clock-cells = <2>; + #address-cells = <0>; - gfx_fck_div_ck: gfx_fck_div_ck@52c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x052c>; - ti,max-div = <2>; + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + }; + + gfx_fck_div_ck: clock-gfx-fck-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; + clocks = <&gfx_fclk_clksel_ck>; + ti,max-div = <2>; + }; }; sysclkout_pre_ck: sysclkout_pre_ck@700 { From 9bc059f71c0ad5a1a9a94556a2e77fde6416fcec Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:33:32 +0200 Subject: [PATCH 192/791] ARM: dts: Add clksel node for am3 clkout Let's add a clksel node for the component clocks to avoid devicetree unique_unit_address warnings. The component clocks can now get IO address from the parent clksel node. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204073333.18175-4-tony@atomide.com> --- arch/arm/boot/dts/am33xx-clocks.dtsi | 47 ++++++++++++++++------------ 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index a70ce9f3fb27..632147b16244 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -524,28 +524,35 @@ }; }; - sysclkout_pre_ck: sysclkout_pre_ck@700 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; - reg = <0x0700>; - }; + clock@700 { + compatible = "ti,clksel"; + reg = <0x700>; + #clock-cells = <2>; + #address-cells = <0>; - clkout2_div_ck: clkout2_div_ck@700 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x0700>; - }; + sysclkout_pre_ck: clock-sysclkout-pre { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sysclkout_pre_ck"; + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; + }; - clkout2_ck: clkout2_ck@700 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; - reg = <0x0700>; + clkout2_div_ck: clock-clkout2-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "clkout2_div_ck"; + clocks = <&sysclkout_pre_ck>; + ti,bit-shift = <3>; + ti,max-div = <8>; + }; + + clkout2_ck: clock-clkout2 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "clkout2_ck"; + clocks = <&clkout2_div_ck>; + ti,bit-shift = <7>; + }; }; }; From ec7aa25fa4839e05f73b17a838e46dc591df75f0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:33:33 +0200 Subject: [PATCH 193/791] ARM: dts: Use clock-output-names for am3 With the TI clocks supporting the use of clock-output-names devicetree property, we no longer need to use non-standard node names for clocks. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204073333.18175-5-tony@atomide.com> --- arch/arm/boot/dts/am33xx-clocks.dtsi | 246 ++++++++++++++++++--------- 1 file changed, 164 insertions(+), 82 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 632147b16244..d34483ae1778 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -5,89 +5,100 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { + sys_clkin_ck: clock-sys-clkin-22@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; }; - adc_tsc_fck: adc_tsc_fck { + adc_tsc_fck: clock-adc-tsc-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan0_fck: dcan0_fck { + dcan0_fck: clock-dcan0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan1_fck: dcan1_fck { + dcan1_fck: clock-dcan1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp0_fck: mcasp0_fck { + mcasp0_fck: clock-mcasp0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp1_fck: mcasp1_fck { + mcasp1_fck: clock-mcasp1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex0_fck: smartreflex0_fck { + smartreflex0_fck: clock-smartreflex0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex1_fck: smartreflex1_fck { + smartreflex1_fck: clock-smartreflex1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - sha0_fck: sha0_fck { + sha0_fck: clock-sha0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - aes0_fck: aes0_fck { + aes0_fck: clock-aes0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - rng_fck: rng_fck { + rng_fck: clock-rng-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; @@ -125,138 +136,157 @@ }; }; &prcm_clocks { - clk_32768_ck: clk_32768_ck { + clk_32768_ck: clock-clk-32768 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; clock-frequency = <32768>; }; - clk_rc32k_ck: clk_rc32k_ck { + clk_rc32k_ck: clock-clk-rc32k { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; clock-frequency = <32000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_24000000_ck: virt_24000000_ck { + virt_24000000_ck: clock-virt-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; clock-frequency = <24000000>; }; - virt_25000000_ck: virt_25000000_ck { + virt_25000000_ck: clock-virt-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; clock-frequency = <25000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - tclkin_ck: tclkin_ck { + tclkin_ck: clock-tclkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; clock-frequency = <12000000>; }; - dpll_core_ck: dpll_core_ck@490 { + dpll_core_ck: clock@490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck@480 { + dpll_core_m4_ck: clock-dpll-core-m4@480 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0480>; ti,index-starts-at-one; }; - dpll_core_m5_ck: dpll_core_m5_ck@484 { + dpll_core_m5_ck: clock-dpll-core-m5@484 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0484>; ti,index-starts-at-one; }; - dpll_core_m6_ck: dpll_core_m6_ck@4d8 { + dpll_core_m6_ck: clock-dpll-core-m6@4d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x04d8>; ti,index-starts-at-one; }; - dpll_mpu_ck: dpll_mpu_ck@488 { + dpll_mpu_ck: clock@488 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; reg = <0x04a8>; ti,index-starts-at-one; }; - dpll_ddr_ck: dpll_ddr_ck@494 { + dpll_ddr_ck: clock@494 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; reg = <0x04a0>; ti,index-starts-at-one; }; - dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { + dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_ddr_m2_div2_ck"; clocks = <&dpll_ddr_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - dpll_disp_ck: dpll_disp_ck@498 { + dpll_disp_ck: clock@498 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_disp_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { + dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; clocks = <&dpll_disp_ck>; ti,max-div = <31>; reg = <0x04a4>; @@ -264,238 +294,269 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck@48c { + dpll_per_ck: clock@48c { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; - dpll_per_m2_ck: dpll_per_m2_ck@4ac { + dpll_per_m2_ck: clock-dpll-per-m2@4ac { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x04ac>; ti,index-starts-at-one; }; - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - clk_24mhz: clk_24mhz { + clk_24mhz: clock-clk-24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <8>; }; - clkdiv32k_ck: clkdiv32k_ck { + clkdiv32k_ck: clock-clkdiv32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; clocks = <&clk_24mhz>; clock-mult = <1>; clock-div = <732>; }; - l3_gclk: l3_gclk { + l3_gclk: clock-l3-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk@530 { + pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; reg = <0x0530>; }; - mmu_fck: mmu_fck@914 { + mmu_fck: clock-mmu-fck-1@914 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "mmu_fck"; clocks = <&dpll_core_m4_ck>; ti,bit-shift = <1>; reg = <0x0914>; }; - timer1_fck: timer1_fck@528 { + timer1_fck: clock-timer1-fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; - timer2_fck: timer2_fck@508 { + timer2_fck: clock-timer2-fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0508>; }; - timer3_fck: timer3_fck@50c { + timer3_fck: clock-timer3-fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x050c>; }; - timer4_fck: timer4_fck@510 { + timer4_fck: clock-timer4-fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0510>; }; - timer5_fck: timer5_fck@518 { + timer5_fck: clock-timer5-fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0518>; }; - timer6_fck: timer6_fck@51c { + timer6_fck: clock-timer6-fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x051c>; }; - timer7_fck: timer7_fck@504 { + timer7_fck: clock-timer7-fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0504>; }; - usbotg_fck: usbotg_fck@47c { + usbotg_fck: clock-usbotg-fck-8@47c { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usbotg_fck"; clocks = <&dpll_per_ck>; ti,bit-shift = <8>; reg = <0x047c>; }; - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <2>; }; - ieee5000_fck: ieee5000_fck@e4 { + ieee5000_fck: clock-ieee5000-fck-1@e4 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ieee5000_fck"; clocks = <&dpll_core_m4_div2_ck>; ti,bit-shift = <1>; reg = <0x00e4>; }; - wdt1_fck: wdt1_fck@538 { + wdt1_fck: clock-wdt1-fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0538>; }; - l4_rtc_gclk: l4_rtc_gclk { + l4_rtc_gclk: clock-l4-rtc-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4_rtc_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <2>; }; - l4hs_gclk: l4hs_gclk { + l4hs_gclk: clock-l4hs-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - l3s_gclk: l3s_gclk { + l3s_gclk: clock-l3s-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4fw_gclk: l4fw_gclk { + l4fw_gclk: clock-l4fw-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4fw_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4ls_gclk: l4ls_gclk { + l4ls_gclk: clock-l4ls-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - sysclk_div_ck: sysclk_div_ck { + sysclk_div_ck: clock-sysclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div_ck"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; reg = <0x0520>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x053c>; }; - lcd_gclk: lcd_gclk@534 { + lcd_gclk: clock-lcd-gclk@534 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "lcd_gclk"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x0534>; ti,set-rate-parent; }; - mmc_clk: mmc_clk { + mmc_clk: clock-mmc { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <2>; @@ -557,139 +618,160 @@ }; &prcm { - per_cm: per-cm@0 { + per_cm: clock@0 { compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; reg = <0x0 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x400>; - l4ls_clkctrl: l4ls-clkctrl@38 { + l4ls_clkctrl: clock@38 { compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; #clock-cells = <2>; }; - l3s_clkctrl: l3s-clkctrl@1c { + l3s_clkctrl: clock@1c { compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; #clock-cells = <2>; }; - l3_clkctrl: l3-clkctrl@24 { + l3_clkctrl: clock@24 { compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; #clock-cells = <2>; }; - l4hs_clkctrl: l4hs-clkctrl@120 { + l4hs_clkctrl: clock@120 { compatible = "ti,clkctrl"; + clock-output-names = "l4hs_clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; - pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { + pruss_ocp_clkctrl: clock@e8 { compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; reg = <0xe8 0x4>; #clock-cells = <2>; }; - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { + cpsw_125mhz_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; reg = <0x0 0x18>; #clock-cells = <2>; }; - lcdc_clkctrl: lcdc-clkctrl@18 { + lcdc_clkctrl: clock@18 { compatible = "ti,clkctrl"; + clock-output-names = "lcdc_clkctrl"; reg = <0x18 0x4>; #clock-cells = <2>; }; - clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { + clk_24mhz_clkctrl: clock@14c { compatible = "ti,clkctrl"; + clock-output-names = "clk_24mhz_clkctrl"; reg = <0x14c 0x4>; #clock-cells = <2>; }; }; - wkup_cm: wkup-cm@400 { + wkup_cm: clock@400 { compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - l4_wkup_clkctrl: l4-wkup-clkctrl@0 { + l4_wkup_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x0 0x10>, <0xb4 0x24>; #clock-cells = <2>; }; - l3_aon_clkctrl: l3-aon-clkctrl@14 { + l3_aon_clkctrl: clock@14 { compatible = "ti,clkctrl"; + clock-output-names = "l3_aon_clkctrl"; reg = <0x14 0x4>; #clock-cells = <2>; }; - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { + l4_wkup_aon_clkctrl: clock@b0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; reg = <0xb0 0x4>; #clock-cells = <2>; }; }; - mpu_cm: mpu-cm@600 { + mpu_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - mpu_clkctrl: mpu-clkctrl@0 { + mpu_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4-rtc-cm@800 { + l4_rtc_cm: clock@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x100>; - l4_rtc_clkctrl: l4-rtc-clkctrl@0 { + l4_rtc_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx-l3-cm@900 { + gfx_l3_cm: clock@900 { compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - gfx_l3_clkctrl: gfx-l3-clkctrl@0 { + gfx_l3_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_cefuse_cm: l4-cefuse-cm@a00 { + l4_cefuse_cm: clock@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_cefuse_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { + l4_cefuse_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_cefuse_clkctrl"; reg = <0x0 0x24>; #clock-cells = <2>; }; From e4920169e7a2a839836d3a0d8cda1bae8caa3056 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 10:08:42 +0200 Subject: [PATCH 194/791] ARM: dts: Use clock-output-names for dra7 With the TI clocks supporting the use of clock-output-names devicetree property, we no longer need to use non-standard node names for clocks. Depends-on: 31aa7056bbec ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl") Depends-on: 9206a3af4fc0 ("clk: ti: Move dra7 clock devices out of the legacy section") Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204080842.40673-1-tony@atomide.com> --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 693 ++++++++++++++++++--------- 1 file changed, 462 insertions(+), 231 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 2365554eef3c..04a7a6d1d529 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -5,210 +5,244 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_core_aon_clocks { - atl_clkin0_ck: atl_clkin0_ck { + atl_clkin0_ck: clock-atl-clkin0 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin0_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin1_ck: atl_clkin1_ck { + atl_clkin1_ck: clock-atl-clkin1 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin1_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin2_ck: atl_clkin2_ck { + atl_clkin2_ck: clock-atl-clkin2 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin2_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin3_ck: atl_clkin3_ck { + atl_clkin3_ck: clock-atl-clkin3 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin3_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - hdmi_clkin_ck: hdmi_clkin_ck { + hdmi_clkin_ck: clock-hdmi-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "hdmi_clkin_ck"; clock-frequency = <0>; }; - mlb_clkin_ck: mlb_clkin_ck { + mlb_clkin_ck: clock-mlb-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "mlb_clkin_ck"; clock-frequency = <0>; }; - mlbp_clkin_ck: mlbp_clkin_ck { + mlbp_clkin_ck: clock-mlbp-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "mlbp_clkin_ck"; clock-frequency = <0>; }; - pciesref_acs_clk_ck: pciesref_acs_clk_ck { + pciesref_acs_clk_ck: clock-pciesref-acs { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pciesref_acs_clk_ck"; clock-frequency = <100000000>; }; - ref_clkin0_ck: ref_clkin0_ck { + ref_clkin0_ck: clock-ref-clkin0 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin0_ck"; clock-frequency = <0>; }; - ref_clkin1_ck: ref_clkin1_ck { + ref_clkin1_ck: clock-ref-clkin1 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin1_ck"; clock-frequency = <0>; }; - ref_clkin2_ck: ref_clkin2_ck { + ref_clkin2_ck: clock-ref-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin2_ck"; clock-frequency = <0>; }; - ref_clkin3_ck: ref_clkin3_ck { + ref_clkin3_ck: clock-ref-clkin3 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin3_ck"; clock-frequency = <0>; }; - rmii_clk_ck: rmii_clk_ck { + rmii_clk_ck: clock-rmii { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "rmii_clk_ck"; clock-frequency = <0>; }; - sdvenc_clkin_ck: sdvenc_clkin_ck { + sdvenc_clkin_ck: clock-sdvenc-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sdvenc_clkin_ck"; clock-frequency = <0>; }; - secure_32k_clk_src_ck: secure_32k_clk_src_ck { + secure_32k_clk_src_ck: clock-secure-32k-clk-src { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; - sys_clk32_crystal_ck: sys_clk32_crystal_ck { + sys_clk32_crystal_ck: clock-sys-clk32-crystal { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_clk32_crystal_ck"; clock-frequency = <32768>; }; - sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { + sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sys_clk32_pseudo_ck"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <610>; }; - virt_12000000_ck: virt_12000000_ck { + virt_12000000_ck: clock-virt-12000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; - virt_13000000_ck: virt_13000000_ck { + virt_13000000_ck: clock-virt-13000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; - virt_16800000_ck: virt_16800000_ck { + virt_16800000_ck: clock-virt-16800000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_20000000_ck: virt_20000000_ck { + virt_20000000_ck: clock-virt-20000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_20000000_ck"; clock-frequency = <20000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - virt_27000000_ck: virt_27000000_ck { + virt_27000000_ck: clock-virt-27000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; - virt_38400000_ck: virt_38400000_ck { + virt_38400000_ck: clock-virt-38400000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; - sys_clkin2: sys_clkin2 { + sys_clkin2: clock-sys-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_clkin2"; clock-frequency = <22579200>; }; - usb_otg_clkin_ck: usb_otg_clkin_ck { + usb_otg_clkin_ck: clock-usb-otg-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "usb_otg_clkin_ck"; clock-frequency = <0>; }; - video1_clkin_ck: video1_clkin_ck { + video1_clkin_ck: clock-video1-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video1_clkin_ck"; clock-frequency = <0>; }; - video1_m2_clkin_ck: video1_m2_clkin_ck { + video1_m2_clkin_ck: clock-video1-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video1_m2_clkin_ck"; clock-frequency = <0>; }; - video2_clkin_ck: video2_clkin_ck { + video2_clkin_ck: clock-video2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video2_clkin_ck"; clock-frequency = <0>; }; - video2_m2_clkin_ck: video2_m2_clkin_ck { + video2_m2_clkin_ck: clock-video2-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video2_m2_clkin_ck"; clock-frequency = <0>; }; - dpll_abe_ck: dpll_abe_ck@1e0 { + dpll_abe_ck: clock@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; - dpll_abe_x2_ck: dpll_abe_x2_ck { + dpll_abe_x2_ck: clock-dpll-abe-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { + dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -217,18 +251,20 @@ ti,invert-autoidle-bit; }; - abe_clk: abe_clk@108 { + abe_clk: clock-abe@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; ti,index-power-of-two; }; - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { + dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -237,9 +273,10 @@ ti,invert-autoidle-bit; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { + dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -248,30 +285,34 @@ ti,invert-autoidle-bit; }; - dpll_core_byp_mux: dpll_core_byp_mux@12c { + dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck@120 { + dpll_core_ck: clock@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { + dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -280,24 +321,27 @@ ti,invert-autoidle-bit; }; - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { + mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck@160 { + dpll_mpu_ck: clock@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -306,42 +350,47 @@ ti,invert-autoidle-bit; }; - mpu_dclk_div: mpu_dclk_div { + mpu_dclk_div: clock-mpu-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dclk_div"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { + dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dsp_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { + dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_dsp_byp_mux"; clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0240>; }; - dpll_dsp_ck: dpll_dsp_ck@234 { + dpll_dsp_ck: clock@234 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_dsp_ck"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; assigned-clocks = <&dpll_dsp_ck>; assigned-clock-rates = <600000000>; }; - dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { + dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m2_ck"; clocks = <&dpll_dsp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -352,34 +401,38 @@ assigned-clock-rates = <600000000>; }; - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { + iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { + dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck@1a0 { + dpll_iva_ck: clock@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; assigned-clock-rates = <1165000000>; }; - dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { + dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m2_ck"; clocks = <&dpll_iva_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -390,34 +443,38 @@ assigned-clock-rates = <388333334>; }; - iva_dclk: iva_dclk { + iva_dclk: clock-iva-dclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dclk"; clocks = <&dpll_iva_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { + dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_gpu_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02e4>; }; - dpll_gpu_ck: dpll_gpu_ck@2d8 { + dpll_gpu_ck: clock@2d8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gpu_ck"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; assigned-clocks = <&dpll_gpu_ck>; assigned-clock-rates = <1277000000>; }; - dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { + dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gpu_m2_ck"; clocks = <&dpll_gpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -428,9 +485,10 @@ assigned-clock-rates = <425666667>; }; - dpll_core_m2_ck: dpll_core_m2_ck@130 { + dpll_core_m2_ck: clock-dpll-core-m2-8@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -439,32 +497,36 @@ ti,invert-autoidle-bit; }; - core_dpll_out_dclk_div: core_dpll_out_dclk_div { + core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "core_dpll_out_dclk_div"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { + dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_ddr_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x021c>; }; - dpll_ddr_ck: dpll_ddr_ck@210 { + dpll_ddr_ck: clock@210 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -473,24 +535,27 @@ ti,invert-autoidle-bit; }; - dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { + dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_gmac_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02b4>; }; - dpll_gmac_ck: dpll_gmac_ck@2a8 { + dpll_gmac_ck: clock@2a8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gmac_ck"; clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; }; - dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { + dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m2_ck"; clocks = <&dpll_gmac_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -499,72 +564,81 @@ ti,invert-autoidle-bit; }; - video2_dclk_div: video2_dclk_div { + video2_dclk_div: clock-video2-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_dclk_div"; clocks = <&video2_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video1_dclk_div: video1_dclk_div { + video1_dclk_div: clock-video1-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_dclk_div"; clocks = <&video1_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - hdmi_dclk_div: hdmi_dclk_div { + hdmi_dclk_div: clock-hdmi-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_dclk_div"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - per_dpll_hs_clk_div: per_dpll_hs_clk_div { + per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; }; - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { + usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; }; - eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { + eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "eve_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_eve_byp_mux: dpll_eve_byp_mux@290 { + dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_eve_byp_mux"; clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0290>; }; - dpll_eve_ck: dpll_eve_ck@284 { + dpll_eve_ck: clock@284 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_eve_ck"; clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; }; - dpll_eve_m2_ck: dpll_eve_m2_ck@294 { + dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_eve_m2_ck"; clocks = <&dpll_eve_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -573,17 +647,19 @@ ti,invert-autoidle-bit; }; - eve_dclk_div: eve_dclk_div { + eve_dclk_div: clock-eve-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "eve_dclk_div"; clocks = <&dpll_eve_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { + dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -592,9 +668,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { + dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -603,9 +680,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { + dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -614,9 +692,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { + dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -625,9 +704,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { + dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -636,15 +716,17 @@ ti,invert-autoidle-bit; }; - dpll_ddr_x2_ck: dpll_ddr_x2_ck { + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; clocks = <&dpll_ddr_ck>; }; - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { + dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_h11x2_ck"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -653,15 +735,17 @@ ti,invert-autoidle-bit; }; - dpll_dsp_x2_ck: dpll_dsp_x2_ck { + dpll_dsp_x2_ck: clock-dpll-dsp-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_dsp_x2_ck"; clocks = <&dpll_dsp_ck>; }; - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { + dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m3x2_ck"; clocks = <&dpll_dsp_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -672,15 +756,17 @@ assigned-clock-rates = <400000000>; }; - dpll_gmac_x2_ck: dpll_gmac_x2_ck { + dpll_gmac_x2_ck: clock-dpll-gmac-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_gmac_x2_ck"; clocks = <&dpll_gmac_ck>; }; - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { + dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h11x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -689,9 +775,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { + dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h12x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -700,9 +787,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { + dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h13x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -711,9 +799,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { + dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m3x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -722,33 +811,37 @@ ti,invert-autoidle-bit; }; - gmii_m_clk_div: gmii_m_clk_div { + gmii_m_clk_div: clock-gmii-m-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gmii_m_clk_div"; clocks = <&dpll_gmac_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; - hdmi_clk2_div: hdmi_clk2_div { + hdmi_clk2_div: clock-hdmi-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_clk2_div"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - hdmi_div_clk: hdmi_div_clk { + hdmi_div_clk: clock-hdmi-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_div_clk"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - l3_iclk_div: l3_iclk_div@100 { + l3_iclk_div: clock-l3-iclk-div-4@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x0100>; @@ -756,374 +849,420 @@ ti,index-power-of-two; }; - l4_root_clk_div: l4_root_clk_div { + l4_root_clk_div: clock-l4-root-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4_root_clk_div"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <2>; }; - video1_clk2_div: video1_clk2_div { + video1_clk2_div: clock-video1-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_clk2_div"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video1_div_clk: video1_div_clk { + video1_div_clk: clock-video1-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_div_clk"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video2_clk2_div: video2_clk2_div { + video2_clk2_div: clock-video2-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_clk2_div"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video2_div_clk: video2_div_clk { + video2_div_clk: clock-video2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_div_clk"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dummy_ck: dummy_ck { + dummy_ck: clock-dummy { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; &prm_clocks { - sys_clkin1: sys_clkin1@110 { + sys_clkin1: clock-sys-clkin1@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin1"; clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; }; - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { + abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_sys_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0118>; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { + abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x0114>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { + abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x010c>; }; - abe_24m_fclk: abe_24m_fclk@11c { + abe_24m_fclk: clock-abe-24m@11c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x011c>; ti,dividers = <8>, <16>; }; - aess_fclk: aess_fclk@178 { + aess_fclk: clock-aess@178 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; clocks = <&abe_clk>; reg = <0x0178>; ti,max-div = <2>; }; - abe_giclk_div: abe_giclk_div@174 { + abe_giclk_div: clock-abe-giclk-div@174 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_giclk_div"; clocks = <&aess_fclk>; reg = <0x0174>; ti,max-div = <2>; }; - abe_lp_clk_div: abe_lp_clk_div@1d8 { + abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_lp_clk_div"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x01d8>; ti,dividers = <16>, <32>; }; - abe_sys_clk_div: abe_sys_clk_div@120 { + abe_sys_clk_div: clock-abe-sys-clk-div@120 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_sys_clk_div"; clocks = <&sys_clkin1>; reg = <0x0120>; ti,max-div = <2>; }; - adc_gfclk_mux: adc_gfclk_mux@1dc { + adc_gfclk_mux: clock-adc-gfclk-mux@1dc { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "adc_gfclk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; reg = <0x01dc>; }; - sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { + sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sys_clk1_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c8>; ti,index-power-of-two; }; - sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { + sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sys_clk2_dclk_div"; clocks = <&sys_clkin2>; ti,max-div = <64>; reg = <0x01cc>; ti,index-power-of-two; }; - per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { + per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_dclk_div"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x01bc>; ti,index-power-of-two; }; - dsp_gclk_div: dsp_gclk_div@18c { + dsp_gclk_div: clock-dsp-gclk-div@18c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dsp_gclk_div"; clocks = <&dpll_dsp_m2_ck>; ti,max-div = <64>; reg = <0x018c>; ti,index-power-of-two; }; - gpu_dclk: gpu_dclk@1a0 { + gpu_dclk: clock-gpu-dclk@1a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gpu_dclk"; clocks = <&dpll_gpu_m2_ck>; ti,max-div = <64>; reg = <0x01a0>; ti,index-power-of-two; }; - emif_phy_dclk_div: emif_phy_dclk_div@190 { + emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "emif_phy_dclk_div"; clocks = <&dpll_ddr_m2_ck>; ti,max-div = <64>; reg = <0x0190>; ti,index-power-of-two; }; - gmac_250m_dclk_div: gmac_250m_dclk_div@19c { + gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gmac_250m_dclk_div"; clocks = <&dpll_gmac_m2_ck>; ti,max-div = <64>; reg = <0x019c>; ti,index-power-of-two; }; - gmac_main_clk: gmac_main_clk { + gmac_main_clk: clock-gmac-main { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gmac_main_clk"; clocks = <&gmac_250m_dclk_div>; clock-mult = <1>; clock-div = <2>; }; - l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { + l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_480m_dclk_div"; clocks = <&dpll_usb_m2_ck>; ti,max-div = <64>; reg = <0x01ac>; ti,index-power-of-two; }; - usb_otg_dclk_div: usb_otg_dclk_div@184 { + usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "usb_otg_dclk_div"; clocks = <&usb_otg_clkin_ck>; ti,max-div = <64>; reg = <0x0184>; ti,index-power-of-two; }; - sata_dclk_div: sata_dclk_div@1c0 { + sata_dclk_div: clock-sata-dclk-div@1c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sata_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c0>; ti,index-power-of-two; }; - pcie2_dclk_div: pcie2_dclk_div@1b8 { + pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "pcie2_dclk_div"; clocks = <&dpll_pcie_ref_m2_ck>; ti,max-div = <64>; reg = <0x01b8>; ti,index-power-of-two; }; - pcie_dclk_div: pcie_dclk_div@1b4 { + pcie_dclk_div: clock-pcie-dclk-div@1b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "pcie_dclk_div"; clocks = <&apll_pcie_m2_ck>; ti,max-div = <64>; reg = <0x01b4>; ti,index-power-of-two; }; - emu_dclk_div: emu_dclk_div@194 { + emu_dclk_div: clock-emu-dclk-div@194 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "emu_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x0194>; ti,index-power-of-two; }; - secure_32k_dclk_div: secure_32k_dclk_div@1c4 { + secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "secure_32k_dclk_div"; clocks = <&secure_32k_clk_src_ck>; ti,max-div = <64>; reg = <0x01c4>; ti,index-power-of-two; }; - clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { + clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux0_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0158>; }; - clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { + clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux1_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x015c>; }; - clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { + clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux2_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0160>; }; - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { + custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <2>; }; - eve_clk: eve_clk@180 { + eve_clk: clock-eve@180 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "eve_clk"; clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; reg = <0x0180>; }; - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { + hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "hdmi_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0164>; }; - mlb_clk: mlb_clk@134 { + mlb_clk: clock-mlb@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "mlb_clk"; clocks = <&mlb_clkin_ck>; ti,max-div = <64>; reg = <0x0134>; ti,index-power-of-two; }; - mlbp_clk: mlbp_clk@130 { + mlbp_clk: clock-mlbp@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "mlbp_clk"; clocks = <&mlbp_clkin_ck>; ti,max-div = <64>; reg = <0x0130>; ti,index-power-of-two; }; - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { + per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_gfclk2_div"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x0138>; ti,index-power-of-two; }; - timer_sys_clk_div: timer_sys_clk_div@144 { + timer_sys_clk_div: clock-timer-sys-clk-div@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "timer_sys_clk_div"; clocks = <&sys_clkin1>; reg = <0x0144>; ti,max-div = <2>; }; - video1_dpll_clk_mux: video1_dpll_clk_mux@168 { + video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "video1_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0168>; }; - video2_dpll_clk_mux: video2_dpll_clk_mux@16c { + video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "video2_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x016c>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { + wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; clocks = <&sys_clkin1>, <&abe_lp_clk_div>; reg = <0x0108>; }; }; &cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { + dpll_pcie_ref_ck: clock@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_pcie_ref_ck"; clocks = <&sys_clkin1>, <&sys_clkin1>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { + dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2ldo_ck"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1132,23 +1271,26 @@ ti,invert-autoidle-bit; }; - apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { + apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { compatible = "ti,mux-clock"; + clock-output-names = "apll_pcie_in_clk_mux"; clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>; }; - apll_pcie_ck: apll_pcie_ck@21c { + apll_pcie_ck: clock@21c { #clock-cells = <0>; compatible = "ti,dra7-apll-clock"; + clock-output-names = "apll_pcie_ck"; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; reg = <0x021c>, <0x0220>; }; - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { compatible = "ti,divider-clock"; + clock-output-names = "optfclk_pciephy_div"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; @@ -1157,48 +1299,54 @@ ti,max-div = <2>; }; - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { + apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { + apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo_div"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - apll_pcie_m2_ck: apll_pcie_m2_ck { + apll_pcie_m2_ck: clock-apll-pcie-m2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_m2_ck"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_per_byp_mux: dpll_per_byp_mux@14c { + dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck@140 { + dpll_per_ck: clock@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; - dpll_per_m2_ck: dpll_per_m2_ck@150 { + dpll_per_m2_ck: clock-dpll-per-m2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1207,32 +1355,36 @@ ti,invert-autoidle-bit; }; - func_96m_aon_dclk_div: func_96m_aon_dclk_div { + func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_aon_dclk_div"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { + dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck@180 { + dpll_usb_ck: clock@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { + dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -1241,9 +1393,10 @@ ti,invert-autoidle-bit; }; - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { + dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2_ck"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -1252,15 +1405,17 @@ ti,invert-autoidle-bit; }; - dpll_per_x2_ck: dpll_per_x2_ck { + dpll_per_x2_ck: clock-dpll-per-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { + dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1269,9 +1424,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { + dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1280,9 +1436,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { + dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h13x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1291,9 +1448,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { + dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1302,9 +1460,10 @@ ti,invert-autoidle-bit; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { + dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1313,105 +1472,118 @@ ti,invert-autoidle-bit; }; - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { + dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; }; - func_128m_clk: func_128m_clk { + func_128m_clk: clock-func-128m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; - func_12m_fclk: func_12m_fclk { + func_12m_fclk: clock-func-12m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; - func_24m_clk: func_24m_clk { + func_24m_clk: clock-func-24m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - func_48m_fclk: func_48m_fclk { + func_48m_fclk: clock-func-48m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; }; - func_96m_fclk: func_96m_fclk { + func_96m_fclk: clock-func-96m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk@104 { + l3init_60m_fclk: clock-l3init-60m@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; }; - clkout2_clk: clkout2_clk@6b0 { + clkout2_clk: clock-clkout2-8@6b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkout2_clk"; clocks = <&clkoutmux2_clk_mux>; ti,bit-shift = <8>; reg = <0x06b0>; }; - l3init_960m_gfclk: l3init_960m_gfclk@6c0 { + l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "l3init_960m_gfclk"; clocks = <&dpll_usb_clkdcoldo>; ti,bit-shift = <8>; reg = <0x06c0>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; }; - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { + usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy2_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0688>; }; - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { + usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy3_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0698>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { + gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <24>; reg = <0x1220>; @@ -1419,9 +1591,10 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { + gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <26>; reg = <0x1220>; @@ -1429,34 +1602,38 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { + l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3instr_ts_gclk_div"; clocks = <&wkupaon_iclk_mux>; ti,bit-shift = <24>; reg = <0x0e50>; ti,dividers = <8>, <16>, <32>; }; - vip1_gclk_mux: vip1_gclk_mux@1020 { + vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip1_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1020>; }; - vip2_gclk_mux: vip2_gclk_mux@1028 { + vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip2_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1028>; }; - vip3_gclk_mux: vip3_gclk_mux@1030 { + vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip3_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1030>; @@ -1464,48 +1641,54 @@ }; &cm_core_clockdomains { - coreaon_clkdm: coreaon_clkdm { + coreaon_clkdm: clock-coreaon-clkdm { compatible = "ti,clockdomain"; + clock-output-names = "coreaon_clkdm"; clocks = <&dpll_usb_ck>; }; }; &scm_conf_clocks { - dss_deshdcp_clk: dss_deshdcp_clk@558 { + dss_deshdcp_clk: clock-dss-deshdcp-0@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "dss_deshdcp_clk"; clocks = <&l3_iclk_div>; ti,bit-shift = <0>; reg = <0x558>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@558 { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <20>; reg = <0x0558>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk@558 { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <21>; reg = <0x0558>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk@558 { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <22>; reg = <0x0558>; }; - sys_32k_ck: sys_32k_ck { + sys_32k_ck: clock-sys-32k { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_32k_ck"; clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; ti,bit-shift = <8>; reg = <0x6c4>; @@ -1513,97 +1696,110 @@ }; &cm_core_aon { - mpu_cm: mpu-cm@300 { + mpu_cm: clock@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x300 0x100>; - mpu_clkctrl: mpu-clkctrl@20 { + mpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - dsp1_cm: dsp1-cm@400 { + dsp1_cm: clock@400 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp1_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - dsp1_clkctrl: dsp1-clkctrl@20 { + dsp1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - ipu_cm: ipu-cm@500 { + ipu_cm: clock@500 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x500 0x100>; - ipu1_clkctrl: ipu1-clkctrl@20 { + ipu1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; assigned-clock-parents = <&dpll_core_h22x2_ck>; }; - ipu_clkctrl: ipu-clkctrl@50 { + ipu_clkctrl: clock@50 { compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; reg = <0x50 0x34>; #clock-cells = <2>; }; }; - dsp2_cm: dsp2-cm@600 { + dsp2_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp2_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - dsp2_clkctrl: dsp2-clkctrl@20 { + dsp2_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - rtc_cm: rtc-cm@700 { + rtc_cm: clock@700 { compatible = "ti,omap4-cm"; + clock-output-names = "rtc_cm"; reg = <0x700 0x60>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x60>; - rtc_clkctrl: rtc-clkctrl@20 { + rtc_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "rtc_clkctrl"; reg = <0x20 0x28>; #clock-cells = <2>; }; }; - vpe_cm: vpe-cm@760 { + vpe_cm: clock@760 { compatible = "ti,omap4-cm"; + clock-output-names = "vpe_cm"; reg = <0x760 0xc>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x760 0xc>; - vpe_clkctrl: vpe-clkctrl@0 { + vpe_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "vpe_clkctrl"; reg = <0x0 0xc>; #clock-cells = <2>; }; @@ -1612,212 +1808,242 @@ }; &cm_core { - coreaon_cm: coreaon-cm@600 { + coreaon_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "coreaon_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - coreaon_clkctrl: coreaon-clkctrl@20 { + coreaon_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "coreaon_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; - l3main1_cm: l3main1-cm@700 { + l3main1_cm: clock@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; - l3main1_clkctrl: l3main1-clkctrl@20 { + l3main1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; reg = <0x20 0x74>; #clock-cells = <2>; }; }; - ipu2_cm: ipu2-cm@900 { + ipu2_cm: clock@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu2_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - ipu2_clkctrl: ipu2-clkctrl@20 { + ipu2_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - dma_cm: dma-cm@a00 { + dma_cm: clock@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - dma_clkctrl: dma-clkctrl@20 { + dma_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - emif_cm: emif-cm@b00 { + emif_cm: clock@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xb00 0x100>; - emif_clkctrl: emif-clkctrl@20 { + emif_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - atl_cm: atl-cm@c00 { + atl_cm: clock@c00 { compatible = "ti,omap4-cm"; + clock-output-names = "atl_cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xc00 0x100>; - atl_clkctrl: atl-clkctrl@0 { + atl_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "atl_clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - l4cfg_cm: l4cfg-cm@d00 { + l4cfg_cm: clock@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xd00 0x100>; - l4cfg_clkctrl: l4cfg-clkctrl@20 { + l4cfg_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; reg = <0x20 0x84>; #clock-cells = <2>; }; }; - l3instr_cm: l3instr-cm@e00 { + l3instr_cm: clock@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe00 0x100>; - l3instr_clkctrl: l3instr-clkctrl@20 { + l3instr_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - iva_cm: iva-cm@f00 { + iva_cm: clock@f00 { compatible = "ti,omap4-cm"; + clock-output-names = "iva_cm"; reg = <0xf00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xf00 0x100>; - iva_clkctrl: iva-clkctrl@20 { + iva_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "iva_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - cam_cm: cam-cm@1000 { + cam_cm: clock@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "cam_cm"; reg = <0x1000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000 0x100>; - cam_clkctrl: cam-clkctrl@20 { + cam_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "cam_clkctrl"; reg = <0x20 0x2c>; #clock-cells = <2>; }; }; - dss_cm: dss-cm@1100 { + dss_cm: clock@1100 { compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1100 0x100>; - dss_clkctrl: dss-clkctrl@20 { + dss_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; - gpu_cm: gpu-cm@1200 { + gpu_cm: clock@1200 { compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; reg = <0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1200 0x100>; - gpu_clkctrl: gpu-clkctrl@20 { + gpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l3init_cm: l3init-cm@1300 { + l3init_cm: clock@1300 { compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1300 0x100>; - l3init_clkctrl: l3init-clkctrl@20 { + l3init_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; reg = <0x20 0x6c>, <0xe0 0x14>; #clock-cells = <2>; }; - pcie_clkctrl: pcie-clkctrl@b0 { + pcie_clkctrl: clock@b0 { compatible = "ti,clkctrl"; + clock-output-names = "pcie_clkctrl"; reg = <0xb0 0xc>; #clock-cells = <2>; }; - gmac_clkctrl: gmac-clkctrl@d0 { + gmac_clkctrl: clock@d0 { compatible = "ti,clkctrl"; + clock-output-names = "gmac_clkctrl"; reg = <0xd0 0x4>; #clock-cells = <2>; }; }; - l4per_cm: l4per-cm@1700 { + l4per_cm: clock@1700 { compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; reg = <0x1700 0x300>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1700 0x300>; - l4per_clkctrl: l4per-clkctrl@28 { + l4per_clkctrl: clock@28 { compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; #clock-cells = <2>; @@ -1825,20 +2051,23 @@ assigned-clock-parents = <&abe_24m_fclk>; }; - l4sec_clkctrl: l4sec-clkctrl@1a0 { + l4sec_clkctrl: clock@1a0 { compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; reg = <0x1a0 0x2c>; #clock-cells = <2>; }; - l4per2_clkctrl: l4per2-clkctrl@c { + l4per2_clkctrl: clock@c { compatible = "ti,clkctrl"; + clock-output-names = "l4per2_clkctrl"; reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; #clock-cells = <2>; }; - l4per3_clkctrl: l4per3-clkctrl@14 { + l4per3_clkctrl: clock@14 { compatible = "ti,clkctrl"; + clock-output-names = "l4per3_clkctrl"; reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; #clock-cells = <2>; }; @@ -1847,15 +2076,17 @@ }; &prm { - wkupaon_cm: wkupaon-cm@1800 { + wkupaon_cm: clock@1800 { compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1800 0x100>; - wkupaon_clkctrl: wkupaon-clkctrl@20 { + wkupaon_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; From f8ca5f5ae57fa931b6cc6e622500ee7e9ce3bd8e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 10:15:29 +0200 Subject: [PATCH 195/791] ARM: dts: Use clock-output-names for am4 With the TI clocks supporting the use of clock-output-names devicetree property, we no longer need to use non-standard node names for clocks. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204081529.57694-1-tony@atomide.com> --- arch/arm/boot/dts/am43xx-clocks.dtsi | 339 ++++++++++++++++++--------- 1 file changed, 226 insertions(+), 113 deletions(-) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 66e892fa3398..9a5437b3d6a8 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -5,217 +5,246 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { + sys_clkin_ck: clock-sys-clkin-31@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; ti,bit-shift = <31>; reg = <0x0040>; }; - crystal_freq_sel_ck: crystal_freq_sel_ck@40 { + crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "crystal_freq_sel_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <29>; reg = <0x0040>; }; - sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { + sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sysboot_freq_sel_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; }; - adc_tsc_fck: adc_tsc_fck { + adc_tsc_fck: clock-adc-tsc-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan0_fck: dcan0_fck { + dcan0_fck: clock-dcan0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan1_fck: dcan1_fck { + dcan1_fck: clock-dcan1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp0_fck: mcasp0_fck { + mcasp0_fck: clock-mcasp0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp1_fck: mcasp1_fck { + mcasp1_fck: clock-mcasp1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex0_fck: smartreflex0_fck { + smartreflex0_fck: clock-smartreflex0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex1_fck: smartreflex1_fck { + smartreflex1_fck: clock-smartreflex1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - sha0_fck: sha0_fck { + sha0_fck: clock-sha0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - aes0_fck: aes0_fck { + aes0_fck: clock-aes0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - rng_fck: rng_fck { + rng_fck: clock-rng-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@664 { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <0>; reg = <0x0664>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk@664 { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <1>; reg = <0x0664>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk@664 { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <2>; reg = <0x0664>; }; - ehrpwm3_tbclk: ehrpwm3_tbclk@664 { + ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm3_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <4>; reg = <0x0664>; }; - ehrpwm4_tbclk: ehrpwm4_tbclk@664 { + ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm4_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <5>; reg = <0x0664>; }; - ehrpwm5_tbclk: ehrpwm5_tbclk@664 { + ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm5_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <6>; reg = <0x0664>; }; }; &prcm_clocks { - clk_32768_ck: clk_32768_ck { + clk_32768_ck: clock-clk-32768 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; clock-frequency = <32768>; }; - clk_rc32k_ck: clk_rc32k_ck { + clk_rc32k_ck: clock-clk-rc32k { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; clock-frequency = <32768>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_24000000_ck: virt_24000000_ck { + virt_24000000_ck: clock-virt-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; clock-frequency = <24000000>; }; - virt_25000000_ck: virt_25000000_ck { + virt_25000000_ck: clock-virt-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; clock-frequency = <25000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - tclkin_ck: tclkin_ck { + tclkin_ck: clock-tclkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; clock-frequency = <26000000>; }; - dpll_core_ck: dpll_core_ck@2d20 { + dpll_core_ck: clock@2d20 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck@2d38 { + dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -224,9 +253,10 @@ ti,invert-autoidle-bit; }; - dpll_core_m5_ck: dpll_core_m5_ck@2d3c { + dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -235,9 +265,10 @@ ti,invert-autoidle-bit; }; - dpll_core_m6_ck: dpll_core_m6_ck@2d40 { + dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -246,16 +277,18 @@ ti,invert-autoidle-bit; }; - dpll_mpu_ck: dpll_mpu_ck@2d60 { + dpll_mpu_ck: clock@2d60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -264,24 +297,27 @@ ti,invert-autoidle-bit; }; - mpu_periphclk: mpu_periphclk { + mpu_periphclk: clock-mpu-periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - dpll_ddr_ck: dpll_ddr_ck@2da0 { + dpll_ddr_ck: clock@2da0 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -290,16 +326,18 @@ ti,invert-autoidle-bit; }; - dpll_disp_ck: dpll_disp_ck@2e20 { + dpll_disp_ck: clock@2e20 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_disp_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { + dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; clocks = <&dpll_disp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -309,16 +347,18 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck@2de0 { + dpll_per_ck: clock@2de0 { #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; - dpll_per_m2_ck: dpll_per_m2_ck@2df0 { + dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -327,119 +367,135 @@ ti,invert-autoidle-bit; }; - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - clk_24mhz: clk_24mhz { + clk_24mhz: clock-clk-24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <8>; }; - clkdiv32k_ck: clkdiv32k_ck { + clkdiv32k_ck: clock-clkdiv32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; clocks = <&clk_24mhz>; clock-mult = <1>; clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick@2a38 { + clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkdiv32k_ick"; clocks = <&clkdiv32k_ck>; ti,bit-shift = <8>; reg = <0x2a38>; }; - sysclk_div: sysclk_div { + sysclk_div: clock-sysclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk@4248 { + pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; reg = <0x4248>; }; - clk_32k_tpm_ck: clk_32k_tpm_ck { + clk_32k_tpm_ck: clock-clk-32k-tpm { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32k_tpm_ck"; clock-frequency = <32768>; }; - timer1_fck: timer1_fck@4200 { + timer1_fck: clock-timer1-fck@4200 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4200>; }; - timer2_fck: timer2_fck@4204 { + timer2_fck: clock-timer2-fck@4204 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4204>; }; - timer3_fck: timer3_fck@4208 { + timer3_fck: clock-timer3-fck@4208 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4208>; }; - timer4_fck: timer4_fck@420c { + timer4_fck: clock-timer4-fck@420c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x420c>; }; - timer5_fck: timer5_fck@4210 { + timer5_fck: clock-timer5-fck@4210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4210>; }; - timer6_fck: timer6_fck@4214 { + timer6_fck: clock-timer6-fck@4214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4214>; }; - timer7_fck: timer7_fck@4218 { + timer7_fck: clock-timer7-fck@4218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4218>; }; - wdt1_fck: wdt1_fck@422c { + wdt1_fck: clock-wdt1-fck@422c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; reg = <0x422c>; }; @@ -451,125 +507,141 @@ reg = <0x424c>; }; - l3_gclk: l3_gclk { + l3_gclk: clock-l3-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <2>; }; - l4hs_gclk: l4hs_gclk { + l4hs_gclk: clock-l4hs-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - l3s_gclk: l3s_gclk { + l3s_gclk: clock-l3s-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4ls_gclk: l4ls_gclk { + l4ls_gclk: clock-l4ls-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; reg = <0x4238>; }; - dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { + dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_clksel_mac_clk"; clocks = <&dpll_core_m5_ck>; reg = <0x4234>; ti,bit-shift = <2>; ti,dividers = <2>, <5>; }; - clk_32k_mosc_ck: clk_32k_mosc_ck { + clk_32k_mosc_ck: clock-clk-32k-mosc { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32k_mosc_ck"; clock-frequency = <32768>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; reg = <0x4240>; }; - mmc_clk: mmc_clk { + mmc_clk: clock-mmc { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; clocks = <&sysclk_div>, <&dpll_per_m2_ck>; ti,bit-shift = <1>; reg = <0x423c>; }; - gfx_fck_div_ck: gfx_fck_div_ck@423c { + gfx_fck_div_ck: clock-gfx-fck-div@423c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; clocks = <&gfx_fclk_clksel_ck>; reg = <0x423c>; ti,max-div = <2>; }; - disp_clk: disp_clk@4244 { + disp_clk: clock-disp@4244 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "disp_clk"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x4244>; ti,set-rate-parent; }; - dpll_extdev_ck: dpll_extdev_ck@2e60 { + dpll_extdev_ck: clock@2e60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_extdev_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; - dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { + dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_extdev_m2_ck"; clocks = <&dpll_extdev_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -578,66 +650,75 @@ ti,invert-autoidle-bit; }; - mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { + mux_synctimer32k_ck: clock-mux-synctimer32k@4230 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mux_synctimer32k_ck"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; reg = <0x4230>; }; - timer8_fck: timer8_fck@421c { + timer8_fck: clock-timer8-fck@421c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer8_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x421c>; }; - timer9_fck: timer9_fck@4220 { + timer9_fck: clock-timer9-fck@4220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer9_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4220>; }; - timer10_fck: timer10_fck@4224 { + timer10_fck: clock-timer10-fck@4224 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer10_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4224>; }; - timer11_fck: timer11_fck@4228 { + timer11_fck: clock-timer11-fck@4228 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer11_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4228>; }; - cpsw_50m_clkdiv: cpsw_50m_clkdiv { + cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_50m_clkdiv"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_5m_clkdiv: cpsw_5m_clkdiv { + cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_5m_clkdiv"; clocks = <&cpsw_50m_clkdiv>; clock-mult = <1>; clock-div = <10>; }; - dpll_ddr_x2_ck: dpll_ddr_x2_ck { + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; clocks = <&dpll_ddr_ck>; }; - dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { + dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m4_ck"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -646,9 +727,10 @@ ti,invert-autoidle-bit; }; - dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { + dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_per_clkdcoldo"; clocks = <&dpll_per_ck>; ti,clock-mult = <1>; ti,clock-div = <1>; @@ -657,91 +739,102 @@ ti,invert-autoidle-bit; }; - dll_aging_clk_div: dll_aging_clk_div@4250 { + dll_aging_clk_div: clock-dll-aging-clk-div@4250 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dll_aging_clk_div"; clocks = <&sys_clkin_ck>; reg = <0x4250>; ti,dividers = <8>, <16>, <32>; }; - div_core_25m_ck: div_core_25m_ck { + div_core_25m_ck: clock-div-core-25m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "div_core_25m_ck"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <8>; }; - func_12m_clk: func_12m_clk { + func_12m_clk: clock-func-12m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <16>; }; - vtp_clk_div: vtp_clk_div { + vtp_clk_div: clock-vtp-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "vtp_clk_div"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <2>; }; - usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { + usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "usbphy_32khz_clkmux"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { + usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy0_always_on_clk32k"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a40>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a48>; }; - clkout1_osc_div_ck: clkout1-osc-div-ck { + clkout1_osc_div_ck: clock-clkout1-osc-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_osc_div_ck"; clocks = <&sys_clkin_ck>; ti,bit-shift = <20>; ti,max-div = <4>; reg = <0x4100>; }; - clkout1_src2_mux_ck: clkout1-src2-mux-ck { + clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkout1_src2_mux_ck"; clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, <&dpll_mpu_m2_ck>; reg = <0x4100>; }; - clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { + clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_pre_div_ck"; clocks = <&clkout1_src2_mux_ck>; ti,bit-shift = <4>; ti,max-div = <8>; reg = <0x4100>; }; - clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { + clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_post_div_ck"; clocks = <&clkout1_src2_pre_div_ck>; ti,bit-shift = <8>; ti,max-div = <32>; @@ -749,18 +842,20 @@ reg = <0x4100>; }; - clkout1_mux_ck: clkout1-mux-ck { + clkout1_mux_ck: clock-clkout1-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkout1_mux_ck"; clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; ti,bit-shift = <16>; reg = <0x4100>; }; - clkout1_ck: clkout1-ck { + clkout1_ck: clock-clkout1-ck { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkout1_ck"; clocks = <&clkout1_mux_ck>; ti,bit-shift = <23>; reg = <0x4100>; @@ -768,120 +863,138 @@ }; &prcm { - wkup_cm: wkup-cm@2800 { + wkup_cm: clock@2800 { compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; reg = <0x2800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2800 0x400>; - l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { + l3s_tsc_clkctrl: clock@120 { compatible = "ti,clkctrl"; + clock-output-names = "l3s_tsc_clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { + l4_wkup_aon_clkctrl: clock@228 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; reg = <0x228 0xc>; #clock-cells = <2>; }; - l4_wkup_clkctrl: l4-wkup-clkctrl@220 { + l4_wkup_clkctrl: clock@220 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x220 0x4>, <0x328 0x44>; #clock-cells = <2>; }; }; - mpu_cm: mpu-cm@8300 { + mpu_cm: clock@8300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x8300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8300 0x100>; - mpu_clkctrl: mpu-clkctrl@20 { + mpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx-l3-cm@8400 { + gfx_l3_cm: clock@8400 { compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; reg = <0x8400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8400 0x100>; - gfx_l3_clkctrl: gfx-l3-clkctrl@20 { + gfx_l3_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4-rtc-cm@8500 { + l4_rtc_cm: clock@8500 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; reg = <0x8500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; - l4_rtc_clkctrl: l4-rtc-clkctrl@20 { + l4_rtc_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - per_cm: per-cm@8800 { + per_cm: clock@8800 { compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; reg = <0x8800 0xc00>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8800 0xc00>; - l3_clkctrl: l3-clkctrl@20 { + l3_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; reg = <0x20 0x3c>, <0x78 0x2c>; #clock-cells = <2>; }; - l3s_clkctrl: l3s-clkctrl@68 { + l3s_clkctrl: clock@68 { compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; reg = <0x68 0xc>, <0x220 0x4c>; #clock-cells = <2>; }; - pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { + pruss_ocp_clkctrl: clock@320 { compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; reg = <0x320 0x4>; #clock-cells = <2>; }; - l4ls_clkctrl: l4ls-clkctrl@420 { + l4ls_clkctrl: clock@420 { compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; reg = <0x420 0x1a4>; #clock-cells = <2>; }; - emif_clkctrl: emif-clkctrl@720 { + emif_clkctrl: clock@720 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x720 0x4>; #clock-cells = <2>; }; - dss_clkctrl: dss-clkctrl@a20 { + dss_clkctrl: clock@a20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0xa20 0x4>; #clock-cells = <2>; }; - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { + cpsw_125mhz_clkctrl: clock@b20 { compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; reg = <0xb20 0x4>; #clock-cells = <2>; }; From da541a6c196e60cbad74a4c941afbef1b0331f7f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 10:43:35 +0200 Subject: [PATCH 196/791] ARM: dts: Add clock-output-names for omap4 To stop using the non-standard node name based clock naming, let's first add the clock-output-names property. This allows us to stop using the internal legacy clock naming and unify the naming for the TI SoCs in the following patches. Note that we must wait on fixing the node naming issues until after the internal clock names have been updated to avoid adding name translation unnecessarily. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204084339.12341-2-tony@atomide.com> --- arch/arm/boot/dts/omap443x-clocks.dtsi | 1 + arch/arm/boot/dts/omap446x-clocks.dtsi | 2 + arch/arm/boot/dts/omap44xx-clocks.dtsi | 165 +++++++++++++++++++++++++ 3 files changed, 168 insertions(+) diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi index 39297868ec85..581e088231b5 100644 --- a/arch/arm/boot/dts/omap443x-clocks.dtsi +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi @@ -8,6 +8,7 @@ bandgap_fclk: bandgap_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "bandgap_fclk"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x1888>; diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi index 0f41714cffbb..d9362fef6720 100644 --- a/arch/arm/boot/dts/omap446x-clocks.dtsi +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi @@ -8,6 +8,7 @@ div_ts_ck: div_ts_ck@1888 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_ts_ck"; clocks = <&l4_wkup_clk_mux_ck>; ti,bit-shift = <24>; reg = <0x1888>; @@ -17,6 +18,7 @@ bandgap_ts_fclk: bandgap_ts_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "bandgap_ts_fclk"; clocks = <&div_ts_ck>; ti,bit-shift = <8>; reg = <0x1888>; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 1f1c04d8f472..8fc963e8ed39 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -8,18 +8,21 @@ extalt_clkin_ck: extalt_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "extalt_clkin_ck"; clock-frequency = <59000000>; }; pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; @@ -28,24 +31,28 @@ pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_slimbus_core_clks_ck"; clock-frequency = <12000000>; }; secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; @@ -54,84 +61,98 @@ sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; tie_low_clock_ck: tie_low_clock_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tie_low_clock_ck"; clock-frequency = <0>; }; utmi_phy_clkout_ck: utmi_phy_clkout_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "utmi_phy_clkout_ck"; clock-frequency = <60000000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; clock-frequency = <60000000>; }; xclk60motg_ck: xclk60motg_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60motg_ck"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; @@ -139,6 +160,7 @@ dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; reg = <0x01f0>; }; @@ -146,6 +168,7 @@ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -157,6 +180,7 @@ abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -165,6 +189,7 @@ abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; @@ -175,6 +200,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -186,6 +212,7 @@ core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "core_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; @@ -194,6 +221,7 @@ dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; @@ -201,12 +229,14 @@ dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -218,6 +248,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -229,6 +260,7 @@ ddrphy_ck: ddrphy_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "ddrphy_ck"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <2>; @@ -237,6 +269,7 @@ dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -248,6 +281,7 @@ div_core_ck: div_core_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_core_ck"; clocks = <&dpll_core_m5x2_ck>; reg = <0x0100>; ti,max-div = <2>; @@ -256,6 +290,7 @@ div_iva_hs_clk: div_iva_hs_clk@1dc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_iva_hs_clk"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x01dc>; @@ -265,6 +300,7 @@ div_mpu_hs_clk: div_mpu_hs_clk@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_mpu_hs_clk"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x019c>; @@ -274,6 +310,7 @@ dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -285,6 +322,7 @@ dll_clk_div_ck: dll_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dll_clk_div_ck"; clocks = <&dpll_core_m4x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -293,6 +331,7 @@ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; reg = <0x01f0>; @@ -302,6 +341,7 @@ dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_core_m3x2_gate_ck"; clocks = <&dpll_core_x2_ck>; ti,bit-shift = <8>; reg = <0x0134>; @@ -310,6 +350,7 @@ dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_core_m3x2_div_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; @@ -319,12 +360,14 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "dpll_core_m3x2_ck"; clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; }; dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m7x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -336,6 +379,7 @@ iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "iva_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; ti,bit-shift = <23>; reg = <0x01ac>; @@ -344,6 +388,7 @@ dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; @@ -353,12 +398,14 @@ dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; clocks = <&dpll_iva_ck>; }; dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m4x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -372,6 +419,7 @@ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m5x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -385,6 +433,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; @@ -392,6 +441,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -403,6 +453,7 @@ per_hs_clk_div_ck: per_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_hs_clk_div_ck"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -411,6 +462,7 @@ usb_hs_clk_div_ck: usb_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_hs_clk_div_ck"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; @@ -419,6 +471,7 @@ l3_div_ck: l3_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_div_ck"; clocks = <&div_core_ck>; ti,bit-shift = <4>; ti,max-div = <2>; @@ -428,6 +481,7 @@ l4_div_ck: l4_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l4_div_ck"; clocks = <&l3_div_ck>; ti,bit-shift = <8>; ti,max-div = <2>; @@ -437,6 +491,7 @@ lp_clk_div_ck: lp_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "lp_clk_div_ck"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -445,6 +500,7 @@ mpu_periphclk: mpu_periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; clocks = <&dpll_mpu_ck>; clock-mult = <1>; clock-div = <2>; @@ -453,6 +509,7 @@ ocp_abe_iclk: ocp_abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "ocp_abe_iclk"; clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; ti,bit-shift = <24>; reg = <0x0528>; @@ -462,6 +519,7 @@ per_abe_24m_fclk: per_abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_abe_24m_fclk"; clocks = <&dpll_abe_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -470,6 +528,7 @@ dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; @@ -478,6 +537,7 @@ sys_clkin_ck: sys_clkin_ck@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; @@ -486,6 +546,7 @@ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; reg = <0x0108>; @@ -494,6 +555,7 @@ abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_refclk_mux_ck"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; reg = <0x010c>; }; @@ -501,6 +563,7 @@ dbgclk_mux_ck: dbgclk_mux_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dbgclk_mux_ck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; @@ -509,6 +572,7 @@ l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "l4_wkup_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; reg = <0x0108>; }; @@ -516,6 +580,7 @@ syc_clk_div_ck: syc_clk_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "syc_clk_div_ck"; clocks = <&sys_clkin_ck>; reg = <0x0100>; ti,max-div = <2>; @@ -524,6 +589,7 @@ usim_ck: usim_ck@1858 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "usim_ck"; clocks = <&dpll_per_m4x2_ck>; ti,bit-shift = <24>; reg = <0x1858>; @@ -533,6 +599,7 @@ usim_fclk: usim_fclk@1858 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usim_fclk"; clocks = <&usim_ck>; ti,bit-shift = <8>; reg = <0x1858>; @@ -541,6 +608,7 @@ trace_clk_div_ck: trace_clk_div_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; + clock-output-names = "trace_clk_div_ck"; clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; }; }; @@ -548,6 +616,7 @@ &prm_clockdomains { emu_sys_clkdm: emu_sys_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "emu_sys_clkdm"; clocks = <&trace_clk_div_ck>; }; }; @@ -556,6 +625,7 @@ per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "per_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; ti,bit-shift = <23>; reg = <0x014c>; @@ -564,6 +634,7 @@ dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; @@ -571,6 +642,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -580,6 +652,7 @@ dpll_per_x2_ck: dpll_per_x2_ck@150 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; reg = <0x0150>; }; @@ -587,6 +660,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -598,6 +672,7 @@ dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_per_m3x2_gate_ck"; clocks = <&dpll_per_x2_ck>; ti,bit-shift = <8>; reg = <0x0154>; @@ -606,6 +681,7 @@ dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_per_m3x2_div_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; @@ -615,12 +691,14 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "dpll_per_m3x2_ck"; clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; }; dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m4x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -632,6 +710,7 @@ dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m5x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -643,6 +722,7 @@ dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m6x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -654,6 +734,7 @@ dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m7x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -665,6 +746,7 @@ dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; @@ -672,6 +754,7 @@ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo_ck"; clocks = <&dpll_usb_ck>; ti,clock-div = <1>; ti,autoidle-shift = <8>; @@ -683,6 +766,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -694,6 +778,7 @@ ducati_clk_mux_ck: ducati_clk_mux_ck@100 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "ducati_clk_mux_ck"; clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; reg = <0x0100>; }; @@ -701,6 +786,7 @@ func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -709,6 +795,7 @@ func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -717,6 +804,7 @@ func_24mc_fclk: func_24mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24mc_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -725,6 +813,7 @@ func_48m_fclk: func_48m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <4>, <8>; @@ -733,6 +822,7 @@ func_48mc_fclk: func_48mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48mc_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; @@ -741,6 +831,7 @@ func_64m_fclk: func_64m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_64m_fclk"; clocks = <&dpll_per_m4x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; @@ -749,6 +840,7 @@ func_96m_fclk: func_96m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; @@ -757,6 +849,7 @@ init_60m_fclk: init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; @@ -765,6 +858,7 @@ per_abe_nc_fclk: per_abe_nc_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_nc_fclk"; clocks = <&dpll_abe_m2_ck>; reg = <0x0108>; ti,max-div = <2>; @@ -773,6 +867,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; @@ -782,6 +877,7 @@ &cm2_clockdomains { l3_init_clkdm: l3_init_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "l3_init_clkdm"; clocks = <&dpll_usb_ck>; }; }; @@ -790,6 +886,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; @@ -798,6 +895,7 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; @@ -806,12 +904,14 @@ auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -821,6 +921,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; @@ -829,6 +930,7 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; @@ -837,12 +939,14 @@ auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -852,6 +956,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; @@ -860,6 +965,7 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; @@ -868,12 +974,14 @@ auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -883,6 +991,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; @@ -891,6 +1000,7 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; @@ -899,12 +1009,14 @@ auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -914,6 +1026,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; @@ -922,6 +1035,7 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; @@ -930,12 +1044,14 @@ auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -945,6 +1061,7 @@ auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk5_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0324>; @@ -953,6 +1070,7 @@ auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk5_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0324>; @@ -961,12 +1079,14 @@ auxclk5_src_ck: auxclk5_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk5_src_ck"; clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; }; auxclk5_ck: auxclk5_ck@324 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk5_ck"; clocks = <&auxclk5_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -976,6 +1096,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0210>; @@ -984,6 +1105,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0214>; @@ -992,6 +1114,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0218>; @@ -1000,6 +1123,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x021c>; @@ -1008,6 +1132,7 @@ auxclkreq4_ck: auxclkreq4_ck@220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq4_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0220>; @@ -1016,6 +1141,7 @@ auxclkreq5_ck: auxclkreq5_ck@224 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq5_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0224>; @@ -1025,6 +1151,7 @@ &cm1 { mpuss_cm: mpuss_cm@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpuss_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1032,6 +1159,7 @@ mpuss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpuss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1039,6 +1167,7 @@ tesla_cm: tesla_cm@400 { compatible = "ti,omap4-cm"; + clock-output-names = "tesla_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1046,6 +1175,7 @@ tesla_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "tesla_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1053,6 +1183,7 @@ abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1060,6 +1191,7 @@ abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; @@ -1070,6 +1202,7 @@ &cm2 { l4_ao_cm: l4_ao_cm@600 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_ao_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1077,6 +1210,7 @@ l4_ao_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_ao_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1084,6 +1218,7 @@ l3_1_cm: l3_1_cm@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1091,6 +1226,7 @@ l3_1_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1098,6 +1234,7 @@ l3_2_cm: l3_2_cm@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_2_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1105,6 +1242,7 @@ l3_2_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_2_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1112,6 +1250,7 @@ ducati_cm: ducati_cm@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ducati_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1119,6 +1258,7 @@ ducati_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ducati_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1126,6 +1266,7 @@ l3_dma_cm: l3_dma_cm@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1133,6 +1274,7 @@ l3_dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1140,6 +1282,7 @@ l3_emif_cm: l3_emif_cm@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1147,6 +1290,7 @@ l3_emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_emif_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1154,6 +1298,7 @@ d2d_cm: d2d_cm@c00 { compatible = "ti,omap4-cm"; + clock-output-names = "d2d_cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1161,6 +1306,7 @@ d2d_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "d2d_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1168,6 +1314,7 @@ l4_cfg_cm: l4_cfg_cm@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1175,6 +1322,7 @@ l4_cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_cfg_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1182,6 +1330,7 @@ l3_instr_cm: l3_instr_cm@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1189,6 +1338,7 @@ l3_instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_instr_clkctrl"; reg = <0x20 0x24>; #clock-cells = <2>; }; @@ -1196,6 +1346,7 @@ ivahd_cm: ivahd_cm@f00 { compatible = "ti,omap4-cm"; + clock-output-names = "ivahd_cm"; reg = <0xf00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1203,6 +1354,7 @@ ivahd_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ivahd_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; @@ -1210,6 +1362,7 @@ iss_cm: iss_cm@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "iss_cm"; reg = <0x1000 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1217,6 +1370,7 @@ iss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "iss_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; @@ -1224,6 +1378,7 @@ l3_dss_cm: l3_dss_cm@1100 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_dss_cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1231,6 +1386,7 @@ l3_dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_dss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1238,6 +1394,7 @@ l3_gfx_cm: l3_gfx_cm@1200 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_gfx_cm"; reg = <0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1245,6 +1402,7 @@ l3_gfx_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_gfx_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1252,6 +1410,7 @@ l3_init_cm: l3_init_cm@1300 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_init_cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1259,6 +1418,7 @@ l3_init_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_init_clkctrl"; reg = <0x20 0xc4>; #clock-cells = <2>; }; @@ -1266,6 +1426,7 @@ l4_per_cm: l4_per_cm@1400 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_per_cm"; reg = <0x1400 0x200>; #address-cells = <1>; #size-cells = <1>; @@ -1288,6 +1449,7 @@ &prm { l4_wkup_cm: l4_wkup_cm@1800 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_wkup_cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1295,6 +1457,7 @@ l4_wkup_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; @@ -1302,6 +1465,7 @@ emu_sys_cm: emu_sys_cm@1a00 { compatible = "ti,omap4-cm"; + clock-output-names = "emu_sys_cm"; reg = <0x1a00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1309,6 +1473,7 @@ emu_sys_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "emu_sys_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; From 0752506039c4ea0309979166042544ff2026ea6a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 10:43:36 +0200 Subject: [PATCH 197/791] ARM: dts: Drop custom clkctrl compatible and update omap4 l4per We can now use the clock-output-names and don't need custom compatible values for each clkctrl instance. And we can use a generic name also for the clock manager instance. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204084339.12341-3-tony@atomide.com> --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 8fc963e8ed39..8df73d285638 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -1424,7 +1424,7 @@ }; }; - l4_per_cm: l4_per_cm@1400 { + l4_per_cm: clock@1400 { compatible = "ti,omap4-cm"; clock-output-names = "l4_per_cm"; reg = <0x1400 0x200>; @@ -1433,13 +1433,15 @@ ranges = <0 0x1400 0x200>; l4_per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_per_clkctrl"; reg = <0x20 0x144>; #clock-cells = <2>; }; l4_secure_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_secure_clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; }; From 7359c0aee7616107fe07c47525c54d76281a1619 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 10:43:37 +0200 Subject: [PATCH 198/791] ARM: dts: Add clock-output-names for omap5 To stop using the non-standard node name based clock naming, let's first add the clock-output-names property. This allows us to stop using the internal legacy clock naming and unify the naming for the TI SoCs in the following patches. Note that we must wait on fixing the node naming issues until after the internal clock names have been updated to avoid adding name translation unnecessarily. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204084339.12341-4-tony@atomide.com> --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 152 +++++++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 42f2c447727d..8426ab2cae95 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -8,12 +8,14 @@ pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; @@ -22,18 +24,21 @@ secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; @@ -42,66 +47,77 @@ sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; @@ -109,12 +125,14 @@ dpll_abe_x2_ck: dpll_abe_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; }; dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f0>; @@ -124,6 +142,7 @@ abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -132,6 +151,7 @@ abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; @@ -141,6 +161,7 @@ abe_iclk: abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_iclk"; clocks = <&aess_fclk>; ti,bit-shift = <24>; reg = <0x0528>; @@ -150,6 +171,7 @@ abe_lp_clk_div: abe_lp_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_lp_clk_div"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -158,6 +180,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f4>; @@ -167,6 +190,7 @@ dpll_core_byp_mux: dpll_core_byp_mux@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; @@ -175,6 +199,7 @@ dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; @@ -182,12 +207,14 @@ dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h21x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0150>; @@ -197,6 +224,7 @@ c2c_fclk: c2c_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "c2c_fclk"; clocks = <&dpll_core_h21x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -205,6 +233,7 @@ c2c_iclk: c2c_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "c2c_iclk"; clocks = <&c2c_fclk>; clock-mult = <1>; clock-div = <2>; @@ -213,6 +242,7 @@ dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h11x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0138>; @@ -222,6 +252,7 @@ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x013c>; @@ -231,6 +262,7 @@ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0140>; @@ -240,6 +272,7 @@ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0144>; @@ -249,6 +282,7 @@ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0154>; @@ -258,6 +292,7 @@ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0158>; @@ -267,6 +302,7 @@ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x015c>; @@ -276,6 +312,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; reg = <0x0130>; @@ -285,6 +322,7 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m3x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; @@ -294,6 +332,7 @@ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -302,6 +341,7 @@ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; @@ -310,6 +350,7 @@ dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; @@ -319,12 +360,14 @@ dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; clocks = <&dpll_iva_ck>; }; dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h11x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01b8>; @@ -336,6 +379,7 @@ dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h12x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01bc>; @@ -347,6 +391,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -355,6 +400,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; @@ -362,6 +408,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; reg = <0x0170>; @@ -371,6 +418,7 @@ per_dpll_hs_clk_div: per_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -379,6 +427,7 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; @@ -387,6 +436,7 @@ l3_iclk_div: l3_iclk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x100>; @@ -397,6 +447,7 @@ gpu_l3_iclk: gpu_l3_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gpu_l3_iclk"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <1>; @@ -405,6 +456,7 @@ l4_root_clk_div: l4_root_clk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l4_root_clk_div"; ti,max-div = <2>; ti,bit-shift = <8>; reg = <0x100>; @@ -415,6 +467,7 @@ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus1_slimbus_clk"; clocks = <&slimbus_clk>; ti,bit-shift = <11>; reg = <0x0560>; @@ -423,6 +476,7 @@ aess_fclk: aess_fclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; clocks = <&abe_clk>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -432,6 +486,7 @@ mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mcasp_sync_mux_ck"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; ti,bit-shift = <26>; reg = <0x0540>; @@ -440,6 +495,7 @@ mcasp_gfclk: mcasp_gfclk@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mcasp_gfclk"; clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; ti,bit-shift = <24>; reg = <0x0540>; @@ -448,6 +504,7 @@ dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; @@ -455,6 +512,7 @@ sys_clkin: sys_clkin@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; @@ -463,6 +521,7 @@ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x0108>; }; @@ -470,6 +529,7 @@ abe_dpll_clk_mux: abe_dpll_clk_mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x010c>; }; @@ -477,6 +537,7 @@ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <2>; @@ -485,6 +546,7 @@ dss_syc_gfclk_div: dss_syc_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dss_syc_gfclk_div"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <1>; @@ -493,6 +555,7 @@ wkupaon_iclk_mux: wkupaon_iclk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; clocks = <&sys_clkin>, <&abe_lp_clk_div>; reg = <0x0108>; }; @@ -500,6 +563,7 @@ l3instr_ts_gclk_div: l3instr_ts_gclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3instr_ts_gclk_div"; clocks = <&wkupaon_iclk_mux>; clock-mult = <1>; clock-div = <1>; @@ -511,6 +575,7 @@ dpll_per_byp_mux: dpll_per_byp_mux@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; @@ -519,6 +584,7 @@ dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; @@ -526,12 +592,14 @@ dpll_per_x2_ck: dpll_per_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; }; dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0158>; @@ -541,6 +609,7 @@ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x015c>; @@ -550,6 +619,7 @@ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0164>; @@ -559,6 +629,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -568,6 +639,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -577,6 +649,7 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m3x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; @@ -586,6 +659,7 @@ dpll_unipro1_ck: dpll_unipro1_ck@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro1_ck"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; @@ -593,6 +667,7 @@ dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro1_clkdcoldo"; clocks = <&dpll_unipro1_ck>; clock-mult = <1>; clock-div = <1>; @@ -601,6 +676,7 @@ dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro1_m2_ck"; clocks = <&dpll_unipro1_ck>; ti,max-div = <127>; reg = <0x0210>; @@ -610,6 +686,7 @@ dpll_unipro2_ck: dpll_unipro2_ck@1c0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro2_ck"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; }; @@ -617,6 +694,7 @@ dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro2_clkdcoldo"; clocks = <&dpll_unipro2_ck>; clock-mult = <1>; clock-div = <1>; @@ -625,6 +703,7 @@ dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro2_m2_ck"; clocks = <&dpll_unipro2_ck>; ti,max-div = <127>; reg = <0x01d0>; @@ -634,6 +713,7 @@ dpll_usb_byp_mux: dpll_usb_byp_mux@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; @@ -642,6 +722,7 @@ dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; @@ -649,6 +730,7 @@ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; @@ -657,6 +739,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; reg = <0x0190>; @@ -666,6 +749,7 @@ func_128m_clk: func_128m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -674,6 +758,7 @@ func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -682,6 +767,7 @@ func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -690,6 +776,7 @@ func_48m_fclk: func_48m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; @@ -698,6 +785,7 @@ func_96m_fclk: func_96m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -706,6 +794,7 @@ l3init_60m_fclk: l3init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; @@ -714,6 +803,7 @@ iss_ctrlclk: iss_ctrlclk@1320 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "iss_ctrlclk"; clocks = <&func_96m_fclk>; ti,bit-shift = <8>; reg = <0x1320>; @@ -722,6 +812,7 @@ lli_txphy_clk: lli_txphy_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_clk"; clocks = <&dpll_unipro1_clkdcoldo>; ti,bit-shift = <8>; reg = <0x0f20>; @@ -730,6 +821,7 @@ lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_ls_clk"; clocks = <&dpll_unipro1_m2_ck>; ti,bit-shift = <9>; reg = <0x0f20>; @@ -738,6 +830,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; @@ -746,6 +839,7 @@ fdif_fclk: fdif_fclk@1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "fdif_fclk"; clocks = <&dpll_per_h11x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -755,6 +849,7 @@ gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <24>; reg = <0x1520>; @@ -763,6 +858,7 @@ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <25>; reg = <0x1520>; @@ -771,6 +867,7 @@ hsi_fclk: hsi_fclk@1638 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "hsi_fclk"; clocks = <&dpll_per_m2x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -781,6 +878,7 @@ &cm_core_clockdomains { l3init_clkdm: l3init_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "l3init_clkdm"; clocks = <&dpll_usb_ck>; }; }; @@ -789,6 +887,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; @@ -797,6 +896,7 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; @@ -805,12 +905,14 @@ auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -820,6 +922,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; @@ -828,6 +931,7 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; @@ -836,12 +940,14 @@ auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -851,6 +957,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; @@ -859,6 +966,7 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; @@ -867,12 +975,14 @@ auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -882,6 +992,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; @@ -890,6 +1001,7 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; @@ -898,12 +1010,14 @@ auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -913,6 +1027,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; @@ -921,6 +1036,7 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; @@ -929,12 +1045,14 @@ auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -944,6 +1062,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0210>; @@ -952,6 +1071,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0214>; @@ -960,6 +1080,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0218>; @@ -968,6 +1089,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x021c>; @@ -977,6 +1099,7 @@ &cm_core_aon { mpu_cm: mpu_cm@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -984,6 +1107,7 @@ mpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -991,6 +1115,7 @@ dsp_cm: dsp_cm@400 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -998,6 +1123,7 @@ dsp_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1005,6 +1131,7 @@ abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1012,6 +1139,7 @@ abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; reg = <0x20 0x64>; #clock-cells = <2>; }; @@ -1022,6 +1150,7 @@ &cm_core { l3main1_cm: l3main1_cm@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1029,6 +1158,7 @@ l3main1_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1036,6 +1166,7 @@ l3main2_cm: l3main2_cm@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main2_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1043,6 +1174,7 @@ l3main2_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1050,6 +1182,7 @@ ipu_cm: ipu_cm@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1057,6 +1190,7 @@ ipu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1064,6 +1198,7 @@ dma_cm: dma_cm@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1071,6 +1206,7 @@ dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1078,6 +1214,7 @@ emif_cm: emif_cm@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1085,6 +1222,7 @@ emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1092,6 +1230,7 @@ l4cfg_cm: l4cfg_cm@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1099,6 +1238,7 @@ l4cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1106,6 +1246,7 @@ l3instr_cm: l3instr_cm@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1113,6 +1254,7 @@ l3instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; @@ -1120,6 +1262,7 @@ l4per_cm: l4per_cm@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; reg = <0x1000 0x200>; #address-cells = <1>; #size-cells = <1>; @@ -1140,6 +1283,7 @@ dss_cm: dss_cm@1400 { compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; reg = <0x1400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1147,6 +1291,7 @@ dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1154,6 +1299,7 @@ gpu_cm: gpu_cm@1500 { compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; reg = <0x1500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1161,6 +1307,7 @@ gpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1168,6 +1315,7 @@ l3init_cm: l3init_cm@1600 { compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; reg = <0x1600 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1175,6 +1323,7 @@ l3init_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; reg = <0x20 0xd4>; #clock-cells = <2>; }; @@ -1184,6 +1333,7 @@ &prm { wkupaon_cm: wkupaon_cm@1900 { compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; reg = <0x1900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1191,6 +1341,7 @@ wkupaon_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; @@ -1201,6 +1352,7 @@ fref_xtal_ck: fref_xtal_ck { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "fref_xtal_ck"; clocks = <&sys_clkin>; ti,bit-shift = <28>; reg = <0x14>; From c7d7d0ce29175251f0212a91703ab8e78b1e2784 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 10:43:38 +0200 Subject: [PATCH 199/791] ARM: dts: Drop custom clkctrl compatible and update omap5 l4per We can now use the clock-output-names and don't need custom compatible values for each clkctrl instance. And we can use a generic name also for the clock manager instance. Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren Message-Id: <20220204084339.12341-5-tony@atomide.com> --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 8426ab2cae95..5cf3b0e78c15 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -1260,7 +1260,7 @@ }; }; - l4per_cm: l4per_cm@1000 { + l4per_cm: clock@1000 { compatible = "ti,omap4-cm"; clock-output-names = "l4per_cm"; reg = <0x1000 0x200>; @@ -1269,13 +1269,15 @@ ranges = <0 0x1000 0x200>; l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; reg = <0x20 0x15c>; #clock-cells = <2>; }; l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; }; From f31c834d3976652753f39eb319170c8c4ac3ce55 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 24 Mar 2022 15:33:31 -0700 Subject: [PATCH 200/791] arm64: dts: qcom: sc7280: Fix sar1_irq_odl node name This node should be named sar1-irq-odl, not sar0-irq-odl. Otherwise we'll overwrite the settings for sar0 with what is intended for sar1, leading to probe failures for sar1 that are quite confusing. Fixes: 116f7cc43d28 ("arm64: dts: qcom: sc7280: Add herobrine-r1") Cc: Douglas Anderson Cc: Matthias Kaehlcke Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Tested-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220324223331.876199-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index dc17f2079695..7b8fe20afcea 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -741,7 +741,7 @@ ap_ec_spi: &spi10 { bias-pull-up; }; - sar1_irq_odl: sar0-irq-odl { + sar1_irq_odl: sar1-irq-odl { pins = "gpio140"; function = "gpio"; bias-pull-up; From 70137d1d8a63d5bbb1ad8bf8181299dbc3aab3e7 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 29 Mar 2022 10:59:33 -0700 Subject: [PATCH 201/791] arm64: dts: qcom: sc7280: Add SAR sensors for herobrine Add nodes for the two SX9324 SAR proximity sensors. Not all herobrine boards have these sensors, so leave them disabled by default. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220329105854.v3.1.Icedb2e3cd5e21f3a4ec535ddf756fa44d053b6ed@changeid --- .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 7b8fe20afcea..5f00fa2abaf6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -341,6 +341,43 @@ vreg_edp_3p3: &pp3300_left_in_mlb {}; /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ +ap_sar_sensor_i2c: &i2c1 { + clock-frequency = <400000>; + status = "disabled"; + + ap_sar_sensor0: proximity@28 { + compatible = "semtech,sx9324"; + reg = <0x28>; + #io-channel-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sar0_irq_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <141 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&pp1800_prox>; + + label = "proximity-wifi-lte0"; + status = "disabled"; + }; + + ap_sar_sensor1: proximity@2c { + compatible = "semtech,sx9324"; + reg = <0x2c>; + #io-channel-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sar1_irq_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <140 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&pp1800_prox>; + + label = "proximity-wifi-lte1"; + status = "disabled"; + }; +}; + ap_i2c_tpm: &i2c14 { status = "okay"; clock-frequency = <400000>; From ee2a621160156000da338280c0b8e45bcfb5db8f Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 29 Mar 2022 10:59:34 -0700 Subject: [PATCH 202/791] arm64: dts: qcom: sc7280: Add device tree for herobrine villager Add a basic device tree for the herobrine villager board. Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220329105854.v3.2.Iebdb5af0db7d3d6364cb229a27cd7c668f1063ae@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sc7280-herobrine-villager-r0.dts | 296 ++++++++++++++++++ 2 files changed, 297 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f9e6343acd03..f1b597512352 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts new file mode 100644 index 000000000000..6c2b9a14535a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Villager board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Google Villager (rev0+)"; + compatible = "google,villager", "qcom,sc7280"; +}; + +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_codec { + status = "okay"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + hid-descr-addr = <0x20>; + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&ap_sar_sensor0 { + status = "okay"; +}; + +&ap_sar_sensor1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to herobrine board and is named it gets that name. + * - If a pin goes to herobrine board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_SAR_SDA", + "AP_SAR_SCL", + "PRB_SC_GPIO_6", + "TP_INT_ODL", + "HP_I2C_SDA", + "HP_I2C_SCL", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "SPI_AP_MOSI", + "SPI_AP_MISO", + "SPI_AP_CLK", + "SPI_AP_CS0_L", + /* + * AP_FLASH_WP is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_OD. + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_L", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "PRB_SC_GPIO_32", + "HUB_RST_L", + "", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + + "AP_EC_SPI_MISO", /* 40 */ + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "LCM_RST_L", + "EARLY_EUD_N", + "", + "DP_HOT_PLUG_DET", + "IO_BRD_MLB_ID0", + "IO_BRD_MLB_ID1", + + "IO_BRD_MLB_ID2", /* 50 */ + "SSD_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "PRB_SC_GPIO_58", + "PRB_SC_GPIO_59", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "WF_CAM_MCLK", + "PRB_SC_GPIO_67", + "FPMCU_BOOT0", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "", + "", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "EN_FP_RAILS", + "FP_RST_L", + "PCIE1_CLKREQ_ODL", + + "EN_PP3300_DX_EDP", /* 80 */ + "SC_GPIO_81", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CD_ODL", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "", + "", + "GSC_AP_INT_ODL", + "EN_PP3300_CODEC", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "PRB_SC_GPIO_112", + "UIM0_DATA", + "UIM0_CLK", + "UIM0_RST", + "UIM0_PRESENT_ODL", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "WF_CAM_EN", + + "FASTBOOT_SEL_0", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "PRB_SC_GPIO_129", + + "LCM_ID0", /* 130 */ + "LCM_ID1", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "PRB_SC_GPIO_139", + + "SAR1_IRQ_ODL", /* 140 */ + "SAR0_IRQ_ODL", + "PRB_SC_GPIO_142", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_ODL", + "HUB_EN", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; From 476dce6e50bb21ec0752d54b6754306e30b3f868 Mon Sep 17 00:00:00 2001 From: Rakesh Pillai Date: Mon, 28 Mar 2022 12:37:01 +0530 Subject: [PATCH 203/791] arm64: dts: qcom: sc7280: Add WPSS remoteproc node Add the WPSS remoteproc node in dts for PIL loading. Reviewed-by: Stephen Boyd Signed-off-by: Rakesh Pillai Signed-off-by: Manikanta Pubbisetty Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220328070701.28551-1-quic_mpubbise@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 51 ++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index ecbf2b89d896..069ffbc37bc4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -547,3 +547,7 @@ }; }; +&remoteproc_wpss { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f0b64be63c21..b757e8ad1199 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2842,6 +2842,57 @@ status = "disabled"; }; + remoteproc_wpss: remoteproc@8a00000 { + compatible = "qcom,sc7280-wpss-pil"; + reg = <0 0x08a00000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, + <&gcc GCC_WPSS_AHB_CLK>, + <&gcc GCC_WPSS_RSCP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ahb_bdg", "ahb", + "rscp", "xo"; + + power-domains = <&rpmhpd SC7280_CX>, + <&rpmhpd SC7280_MX>; + power-domain-names = "cx", "mx"; + + memory-region = <&wpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, + <&pdc_reset PDC_WPSS_SYNC_RESET>; + reset-names = "restart", "pdc_sync"; + + qcom,halt-regs = <&tcsr_mutex 0x37000>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "wpss"; + qcom,remote-pid = <13>; + }; + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; From 33495eb77ee4ed1850aa70801afd2a24e8d738bd Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Tue, 22 Mar 2022 09:25:26 +0800 Subject: [PATCH 204/791] arm64: dts: qcom: switch panel compatible to "edp-panel" for limozeen some panel can't light up with new board with ps8640, switch compatible panel define to make it workable. Signed-off-by: Pan Sheng-Liang Signed-off-by: Ivy Jian Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220322092524.1.Ied05fc4b996737e3481861c6ab130a706f288412@changeid --- .../boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts index 4e35aec6a1e5..c44ed54af690 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts @@ -20,7 +20,7 @@ /delete-node/&ap_ts; &panel { - compatible = "innolux,n116bca-ea1", "innolux,n116bge"; + compatible = "edp-panel"; }; &sdhc_2 { From 737f9ea6cee76fb0004c116479a9db34a67fb814 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:17 -0700 Subject: [PATCH 205/791] arm64: dts: qcom: sc7280: Rename crd to crd-r3 There are multiple revisions of CRD boards. The current sc7280-crd.dts describes revision 3 and 4 (aka CRD 1.0 and 2.0). Support for a newer version will be added by another patch. Add the revision number to distinguish it from the versionn. Also add the revision numbers to the compatible string. Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.1.I2deda8f2cd6adfbb525a97d8fee008a8477b7b0e@changeid --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../arm64/boot/dts/qcom/{sc7280-crd.dts => sc7280-crd-r3.dts} | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm64/boot/dts/qcom/{sc7280-crd.dts => sc7280-crd-r3.dts} (91%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f1b597512352..d91fdae81487 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -88,7 +88,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts similarity index 91% rename from arch/arm64/boot/dts/qcom/sc7280-crd.dts rename to arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index e2efbdde53a3..7a028b9248c3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -11,8 +11,8 @@ #include "sc7280-idp-ec-h1.dtsi" / { - model = "Qualcomm Technologies, Inc. sc7280 CRD platform"; - compatible = "qcom,sc7280-crd", "google,hoglin", "qcom,sc7280"; + model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)"; + compatible = "qcom,sc7280-crd", "google,hoglin-rev3", "google,hoglin-rev4", "qcom,sc7280"; aliases { serial0 = &uart5; From f226c660533416c308fcde62d1b785527528974d Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:18 -0700 Subject: [PATCH 206/791] arm64: dts: qcom: sc7280: Add 'piglin' to the crd-r3 compatible strings With newer bootloader versions the crd-r3 (aka CRD 1.0 and 2.0) is identified as a 'piglin' board (like the IDP2 board), instead of 'hoglin' Add the compatible strings 'google,piglin-rev{3,4}'. The hoglin entries are kept to make sure the board keeps booting with older bootloader versions. The compatible string 'google,piglin' (without revision information) is still used by the IDP2 board, which is not expected to evolve further. Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.2.Ib0fbb7e5218201c81a2d064ff13c9bc1b0863212@changeid --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index 7a028b9248c3..344338ad8a01 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -12,7 +12,10 @@ / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)"; - compatible = "qcom,sc7280-crd", "google,hoglin-rev3", "google,hoglin-rev4", "qcom,sc7280"; + compatible = "qcom,sc7280-crd", + "google,hoglin-rev3", "google,hoglin-rev4", + "google,piglin-rev3", "google,piglin-rev4", + "qcom,sc7280"; aliases { serial0 = &uart5; From 533ca1c3c1996ea49a1b31a83ba978f2f96fea9b Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:19 -0700 Subject: [PATCH 207/791] arm64: dts: qcom: sc7280: herobrine: disable some regulators by default Not all herobrine boards have a world facing camera or a fingerprint sensor, disable the regulators that feed these devices by default and only enable them for the boards that use them. Similarly the audio configuration can vary between boards, not all boards have the regulator pp3300_codec, disable it by default. Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.3.Iad21bd53f3ac14956b8dbbf3825fc7ab29abdf97@changeid --- .../qcom/sc7280-herobrine-herobrine-r1.dts | 30 +++++++++++++++++++ .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 ++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index f95273052da0..29c4ca095294 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -14,6 +14,36 @@ compatible = "google,herobrine", "qcom,sc7280"; }; +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_codec { + status = "okay"; +}; + +&pp3300_fp_mcu { + status = "okay"; +}; + +&pp2850_vcm_wf_cam { + status = "okay"; +}; + +&pp2850_wf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp1200_wf_cam { + status = "okay"; +}; + /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ &ap_spi_fp { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5f00fa2abaf6..d57ea4881fa1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -92,6 +92,7 @@ pinctrl-0 = <&en_pp3300_codec>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp3300_left_in_mlb: pp3300-left-in-mlb-regulator { @@ -132,6 +133,7 @@ pinctrl-0 = <&en_fp_rails>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp3300_hub: pp3300-hub-regulator { @@ -194,6 +196,7 @@ pinctrl-0 = <&wf_cam_en>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp2850_wf_cam: pp2850-wf-cam-regulator { @@ -214,6 +217,7 @@ */ vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp1800_fp: pp1800-fp-regulator { @@ -258,6 +262,7 @@ */ vin-supply = <&vreg_l19b_s0>; + status = "disabled"; }; pp1200_wf_cam: pp1200-wf-cam-regulator { @@ -278,6 +283,7 @@ */ vin-supply = <&pp3300_z1>; + status = "disabled"; }; /* BOARD-SPECIFIC TOP LEVEL NODES */ From 6675ac9d0046201af945c7abfe5dd794df22230b Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:20 -0700 Subject: [PATCH 208/791] arm64: dts: qcom: sc7280: Add CRD rev5 Add support for Qualcomm's SC7280 CRD rev5 (aka CRD 3.0/3.1). Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.4.I37bdb77fdd06fb4143056366d7ec35b929528002@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sc7280-herobrine-crd.dts | 313 ++++++++++++++++++ 2 files changed, 314 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d91fdae81487..512084804439 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts new file mode 100644 index 000000000000..fd6eadc8581a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 CRD 3+ board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; + compatible = "google,hoglin", "qcom,sc7280"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&apps_rsc { + pmg1110-regulators { + compatible = "qcom,pmg1110-rpmh-regulators"; + qcom,pmic-id = "k"; + + vreg_s1k_1p0: smps1 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + }; +}; + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +ap_ts_pen_1v8: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&pp3300_left_in_mlb>; + }; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* For SD Card */ +&sdhc_2 { + status = "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to CRD board and is named it gets that name. + * - If a pin goes to CRD board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "EDP_BL_REG_EN", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "PCIE1_RESET_N", + "PCIE1_WAKE_N", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "", + "TPAD_INT_N", + "", + "", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "QSPI_DATA_0", + "QSPI_DATA_1", + "QSPI_CLK", + "QSPI_CS_N_1", + /* + * AP_FLASH_WP is crossystem ABI. Schematics call it + * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the + * signal is active high). + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_N", + "", + + "CAM0_RST_N", /* 20 */ + "CAM1_RST_N", + "SM_DBG_UART_TX", + "SM_DBG_UART_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "", + "HUB_RST", + "", + "", + "", + "", + "", + "", + + "EC_SPI_MISO_GPIO40", /* 40 */ + "EC_SPI_MOSI_GPIO41", + "EC_SPI_CLK_GPIO42", + "EC_SPI_CS_GPIO43", + "", + "EARLY_EUD_EN", + "", + "DP_HOT_PLUG_DETECT", + "AP_BRD_ID_0", + "AP_BRD_ID_1", + + "AP_BRD_ID_2", /* 50 */ + "NVME_PWR_REG_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "", + "", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "", + "", + "", + "CCI_I2C_SDA0", + + "CCI_I2C_SCL0", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "PCIE1_CLK_REQ_N", + + "EN_PP3300_DX_EDP", /* 80 */ + "US_EURO_HS_SEL", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CARD_DET_CONN", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "", + "", + "", + "", + + "", /* 100 */ + "", + "", + "", + "H1_AP_INT_N", + "", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "UIM1_PRESENT", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "", + + "SDM_RFFE1_DATA", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "", + + "", /* 130 */ + "", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "", + + "SAR1_INT_N", /* 140 */ + "SAR0_INT_N", + "", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_N", + "EN_PP3300_HUB", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; From 0d40497d054194768b3ddbf3a676d481b38b96eb Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 10 Mar 2022 13:04:34 -0800 Subject: [PATCH 209/791] arm64: dts: qcom: sc7280-herobrine: Fix PCIe regulator glitch at bootup While scoping signals, we found that the PCIe signals weren't compliant at bootup. Specifically, the bootloader was setting up PCIe and leaving it configured, then jumping to the kernel. The kernel was turning off the regulator while leaving the PCIe clock running, which was a violation. In the regulator bindings (and the Linux kernel driver that uses them), there's currently no way to specify that a GPIO-controlled regulator should keep its state at bootup. You've got to pick either "on" or "off". Let's switch it so that the PCIe regulator defaults to "on" instead of "off". This should be a much safer way to go and avoids the timing violation. The regulator will still be turned off later if there are no users. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220310130429.1.Id41fda1d7f5d9230bc45c1b85b06b0fb0ddd29af@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index d57ea4881fa1..3d9b870d440b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -180,6 +180,13 @@ pinctrl-names = "default"; pinctrl-0 = <&ssd_en>; + /* + * The bootloaer may have left PCIe configured. Powering this + * off while the PCIe clocks are still running isn't great, + * so it's better to default to this regulator being on. + */ + regulator-boot-on; + vin-supply = <&pp3300_z1>; }; From 9464b00e6a118b2712092d453b07ec835deb327f Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 8 Mar 2022 12:52:35 -0800 Subject: [PATCH 210/791] arm64: dts: qcom: sc7280: Delete herobrine-r0 As talked about in commit 61a6262f95e0 ("arm64: dts: qcom: sc7280: Move herobrine-r0 to its own dts"), herobrine evolved pretty significantly after -r0 and newer revisions are pretty different. Nobody needs the old boards to keep working, so let's delete to avoid the maintenance burden. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220308125044.1.I3e4a1a9c102d194698b68661e69efebafec8af1c@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 - .../qcom/sc7280-herobrine-herobrine-r0.dts | 1352 ----------------- 2 files changed, 1353 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 512084804439..2f8aec2cc6db 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -84,7 +84,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts deleted file mode 100644 index 1779d96c30f6..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ /dev/null @@ -1,1352 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Herobrine board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include - -#include "sc7280.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm7325.dtsi" -#include "pm8350c.dtsi" -#include "pmk8350.dtsi" - -#include "sc7280-chrome-common.dtsi" - -/ { - model = "Google Herobrine (rev0)"; - compatible = "google,herobrine-rev0", "qcom,sc7280"; -}; - -/ { - aliases { - serial0 = &uart5; - serial1 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_s3: pp5000-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_s3"; - - /* EC turns on with en_pp5000_s3; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_z1: pp3300-z1-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_z1"; - - /* EC turns on with en_pp3300_z1; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_audio: - pp3300_codec: pp3300-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_codec"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_codec>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_cam: - pp3300_edp: - pp3300_ts: pp3300-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_fp: - pp3300_fp_ls: - pp3300_mcu: pp3300-fp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_fp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-boot-on; - regulator-always-on; - - /* - * WARNING: it is intentional that GPIO 42 isn't listed here. - * The userspace script for updating the fingerprint firmware - * needs to control the FP regulators during a FW update, - * hence the signal can't be owned by the kernel regulator. - */ - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_hub: pp3300-hub-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_hub"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-boot-on; - regulator-always-on; - - gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_hub>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_tp: pp3300-tp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_tp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* AP turns on with PP1800_L18B_S0; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&pp3300_z1>; - }; - - pp2850_uf_cam: pp2850-uf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp2850_uf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&uf_cam_en>; - - vin-supply = <&pp3300_cam>; - }; - - pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp2850_vcm_wf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wf_cam_en>; - - vin-supply = <&pp3300_cam>; - }; - - pp2850_wf_cam: pp2850-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp2850_wf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp3300_cam>; - }; - - pp1800_fp: pp1800-fp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1800_fp"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - regulator-always-on; - - /* - * WARNING: it is intentional that GPIO 42 isn't listed here. - * The userspace script for updating the fingerprint firmware - * needs to control the FP regulators during a FW update, - * hence the signal can't be owned by the kernel regulator. - */ - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; - - vin-supply = <&pp1800_l18b_s0>; - status = "disabled"; - }; - - pp1800_uf_cam: pp1800-uf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1800_uf_cam"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&uf_cam_en>; - */ - - vin-supply = <&pp1800_l19b>; - }; - - pp1800_wf_cam: pp1800-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1800_wf_cam"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp1800_l19b>; - }; - - pp1200_wf_cam: pp1200-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1200_wf_cam"; - - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp1200_l6b>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_pdct_l>; - - pen_insert: pen-insert { - label = "Pen Insert"; - - /* Insert = low, eject = high */ - gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - status = "disabled"; - keyboard_backlight: keyboard-backlight { - status = "disabled"; - label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; - max-brightness = <1023>; - }; - }; -}; - -&apps_rsc { - pm7325-regulators { - compatible = "qcom,pm7325-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd19_pmu_pcie_i: - vdd19_pmu_rfa_i: - vreg_s1b_wlan: - vreg_s1b: smps1 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2040000>; - }; - - vdd_pmu_aon_i: - vreg_s7b_wlan: - vreg_s7b: smps7 { - regulator-min-microvolt = <535000>; - regulator-max-microvolt = <1120000>; - }; - - vdd13_pmu_pcie_i: - vdd13_pmu_rfa_i: - vreg_s8b_wlan: - vreg_s8b: smps8 { - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1500000>; - }; - - vdda_usb_ss_dp_core: - vreg_l1b: ldo1 { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <925000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs0_3p1: - vreg_l2b: ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1200_l6b: - vdd_ufs_1p2: - vdd_vref: - vdda_csi01_1p2: - vdda_csi23_1p2: - vdda_csi4_1p2: - vdda_dsi0_1p2: - vdda_pcie0_1p2: - vdda_pcie1_1p2: - vdda_usb_ss_dp_1p2: - vdda_qlink0_1p2_ck: - vdda_qlink1_1p2_ck: - vreg_l6b_1p2: - vreg_l6b: ldo6 { - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - regulator-initial-mode = ; - }; - - pp2950_l7b: - vreg_l7b: ldo7 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - codec_vcc: - pp1800_l18b_s0: - pp1800_ts: - vdd1: - vddpx_0: - vddpx_3: - vddpx_7: - vreg_l18b: ldo18 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp1800_l19b: - vddpx_ts: - vddpx_wl4otp: - vreg_l19b: ldo19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - pm8350c-regulators { - compatible = "qcom,pm8350c-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_s1c: smps1 { - regulator-min-microvolt = <2190000>; - regulator-max-microvolt = <2210000>; - }; - - vddpx_1: - vreg_s9c: smps9 { - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - }; - - pp1800_l1c: - pp1800_pen: - vdd_a_gfx_cs_1p1: - vdd_a_cxo_1p8: - vdd_qfprom: - vdda_apc_cs_1p8: - vdda_qrefs_1p8: - vdda_turing_q6_cs_1p8: - vdda_usb_hs0_1p8: - vreg_l1c: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; - - dmic_vdd: - pp1800_alc5682: - pp1800_l2c: - pp1800_vreg_alc5682: - vreg_l2c: ldo2 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; - - pp3300_sar: - pp3300_sensor: - vreg_l3c: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3540000>; - regulator-initial-mode = ; - }; - - ppvar_uim1: - vddpx_5: - vreg_l4c: ldo4 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; - - pp2950_l5c: - uim_vcc: - vddpx_6: - vreg_l5c: ldo5 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; - - ppvar_l6c: - vddpx_2: - vreg_l6c: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-initial-mode = ; - }; - - vreg_l7c: ldo7 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_prox: - pp1800_sar: - vreg_l8c: ldo8 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp2950_l9c: - vreg_l9c: ldo9 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vdd_a_gnss_0p9: - vdd_ufs_core: - vdd_usb_hs0_core: - vdd_vref_0p9: - vdda_csi01_0p9: - vdda_csi23_0p9: - vdda_csi4_0p9: - vdda_dsi0_pll_0p9: - vdda_dsi0_0p9: - vdda_pcie0_core: - vdda_pcie1_core: - vdda_qlink0_0p9: - vdda_qlink1_0p9: - vdda_qlink0_0p9_ck: - vdda_qlink1_0p9_ck: - vdda_qrefs_0p875: - vreg_l10c_0p8: - vreg_l10c: ldo10 { - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1050000>; - regulator-initial-mode = ; - }; - - pp2800_l11c: - vreg_l11c: ldo11 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_l12c: - vreg_l12c: ldo12 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp3300_l13c: - vreg_l13c: ldo13 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - }; -}; - -ap_tp_i2c: &i2c1 { - status = "okay"; - clock-frequency = <400000>; - - trackpad: trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <102 IRQ_TYPE_EDGE_FALLING>; - - vcc-supply = <&pp3300_z1>; - - wakeup-source; - }; -}; - -ap_h1_i2c: &i2c12 { - status = "okay"; - clock-frequency = <400000>; - - tpm@50 { - compatible = "google,cr50"; - reg = <0x50>; - - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_EDGE_RISING>; - }; -}; - -ap_ts_pen: &i2c13 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <81 IRQ_TYPE_LEVEL_LOW>; - - post-power-on-delay-ms = <20>; - hid-descr-addr = <0x0001>; - - vdd-supply = <&pp3300_ts>; - }; -}; - -&pm7325_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_rtc { - status = "disabled"; -}; - -&pmk8350_vadc { - pmk8350_die_temp { - reg = ; - label = "pmk8350_die_temp"; - qcom,pre-scaling = <1 1>; - }; - - pmr735a_die_temp { - reg = ; - label = "pmr735a_die_temp"; - qcom,pre-scaling = <1 1>; - }; -}; - -&qfprom { - vcc-supply = <&vdd_qfprom>; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pp2950_l7b>; - vqmmc-supply = <&pp1800_l19b>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; - pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; - vmmc-supply = <&pp2950_l9c>; - vqmmc-supply = <&ppvar_l6c>; - - cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; -}; - -ap_ec_spi: &spi8 { - status = "okay"; - - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs_gpio_init_high>, <&qup_spi8_cs_gpio>; - cs-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <142 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_ec_int_l>; - spi-max-frequency = <3000000>; - - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - typec { - compatible = "google,cros-ec-typec"; - #address-cells = <1>; - #size-cells = <0>; - - usb_c0: connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - label = "left"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - - usb_c1: connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - label = "right"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - }; - }; -}; - -#include -#include - -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_REFRESH) - MATRIX_KEY(0x02, 0x02, KEY_ZOOM) - MATRIX_KEY(0x01, 0x02, KEY_SCALE) - MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; -}; - -&uart5 { - compatible = "qcom,geni-debug-uart"; - status = "okay"; -}; - -&uart7 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; -}; - -/* PINCTRL - additions to nodes defined in sc7280.dtsi */ - -&dp_hot_plug_det { - bias-disable; -}; - -&pcie1_clkreq_n { - bias-pull-up; - drive-strength = <2>; -}; - -&qspi_cs0 { - bias-disable; -}; - -&qspi_clk { - bias-disable; -}; - -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; -}; - -&qup_uart5_rx { - drive-strength = <2>; - bias-pull-up; -}; - -&qup_uart5_tx { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; -}; - -&qup_uart7_rts { - /* We'll drive RTS, so no pull */ - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_tx { - /* We'll drive TX, so no pull */ - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - bias-pull-up; -}; - -&sdc1_clk { - bias-disable; - drive-strength = <16>; -}; - -&sdc1_cmd { - bias-pull-up; - drive-strength = <10>; -}; - -&sdc1_data { - bias-pull-up; - drive-strength = <10>; -}; - -&sdc1_rclk { - bias-pull-down; -}; - -&sdc2_clk { - bias-disable; - drive-strength = <16>; -}; - -&sdc2_cmd { - bias-pull-up; - drive-strength = <10>; -}; - -&sdc2_data { - bias-pull-up; - drive-strength = <10>; -}; - -/* PINCTRL - board-specific pinctrl */ - -&pm8350c_gpios { - gpio-line-names = "AP_SUSPEND", - "", - "", - "AP_BL_EN", - "", - "SD_CD_ODL", - "", - "", - "AP_BL_PWM"; - - ap_bl_en: ap-bl-en { - pins = "gpio4"; - function = "normal"; - qcom,drive-strength = ; - bias-disable; - - /* Force backlight to be disabled to match state at boot. */ - output-low; - }; -}; - -&tlmm { - gpio-line-names = "HP_I2C_SDA", /* 0 */ - "HP_I2C_SCL", - "SSD_RST_L", - "PE_WAKE_ODL", - "AP_TP_I2C_SDA", - "AP_TP_I2C_SCL", - "UF_CAM_EN", - "WF_CAM_EN", - "AP_SAR_SENSOR_SDA", - "AP_SAR_SENSOR_SCL", - - "", /* 10 */ - "", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "AP_SPI_CLK", - "AP_SPI_CS0_L", - "", - "", - "EDP_HPD", - "", - - "UF_CAM_RST_L", /* 20 */ - "WF_CAM_RST_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "EN_PP3300_HUB", - "", - "HOST2WLAN_SOL", - "WLAN2HOST_SOL", - "BT_UART_CTS", - "BT_UART_RTS", - - "BT_UART_TXD", /* 30 */ - "BT_UART_RXD", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "", - "", - "", - "PEN_PDCT_L", - - "IO_BRD_ID0", /* 40 */ - "IO_BRD_ID1", - "EN_FP_RAILS", - "PEN_IRQ_L", - "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - - "AP_H1_SPI_CLK", /* 50 */ - "AP_H1_SPI_CS_L", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "H1_AP_INT_ODL", - "", - "LCM_RST_1V8_L", - "AMP_EN", - "", - "DP_HOT_PLUG_DET", - - "HUB_RST_L", /* 60 */ - "FP_TO_AP_IRQ_L", - "", - "", - "UF_CAM_MCLK", - "WF_CAM_MCLK", - "IO_BRD_ID2", - "EN_PP3300_CODEC", - "EC_IN_RW_ODL", - "UF_CAM_SDA", - - "UF_CAM_SCL", /* 70 */ - "WF_CAM_SDA", - "WF_CAM_SCL", - "AP_BRD_ID0", - "AP_BRD_ID1", - "AP_BRD_ID2", - "", - "FPMCU_BOOT0", - "FP_RST_L", - "PE_CLKREQ_ODL", - - "EN_EDP_PP3300", /* 80 */ - "TS_INT_L", - "FORCE_USB_BOOT", - "WCD_RST_L", - "WLAN_EN", - "BT_EN", - "WLAN_SW_CTRL", - "PCIE0_RESET_L", - "PCIE0_CLK_REQ_L", - "PCIE0_WAKE_L", - - "AS_EN", /* 90 */ - "SD_CD_ODL", - "", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "BT_WLAN_SB_CLK", - "BT_WLAN_SB_DATA", - "HP_MCLK", - "HP_BCLK", - "HP_DOUT", - "HP_DIN", - - "HP_LRCLK", /* 100 */ - "HP_IRQ", - "TP_INT_ODL", - "", - "IO_SKU_ID2", - "TS_RESET_L", - "AMP_BCLK", - "AMP_DIN", - "AMP_LRCLK", - "UIM2_DATA", - - "UIM2_CLK", /* 110 */ - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "RFFE0_CLK", - "RFFE0_DATA/BOOT_CONFIG_0", - "RFFE1_CLK", - - "RFFE1_DATA/BOOT_CONFIG_1", /* 120 */ - "RFFE2_CLK", - "RFFE2_DATA/BOOT_CONFIG_2", - "RFFE3_CLK", - "RFFE3_DATA/BOOT_CONFIG_3", - "RFFE4_CLK", - "RFFE4_DATA", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "IO_SKU_ID0", - - "IO_SKU_ID1", /* 130 */ - "", - "", - "QLINK0_REQ", - "QLINK0_EN", - "QLINK0_WMSS_RESET_L", - "QLINK1_REQ", - "QLINK1_EN", - "QLINK1_WMSS_RESET_L", - "FORCED_USB_BOOT_POL", - - "", /* 140 */ - "P_SENSOR_INT_L", - "AP_EC_INT_L", - "", - "WCD_SWR_TX_CLK", - "WCD_SWR_TX_DATA_0", - "WCD_SWR_TX_DATA_1", - "WCD_SWR_RX_CLK", - "WCD_SWR_RX_DATA_0", - "WCD_SWR_RX_DATA_1", - - "", /* 150 */ - "", - "", - "", - "", - "", - "", - "", - "WCD_SWR_TX_DATA_2", - "", - - "", /* 160 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - - "", /* 170 */ - "SENS_UART_TXD", - "SENS_UART_RXD", - "", - "", - ""; - - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default"; - pinctrl-0 = <&bios_flash_wp_l>; - - amp_en: amp-en { - pins = "gpio57"; - function = "gpio"; - bias-pull-down; - }; - - ap_ec_int_l: ap-ec-int-l { - pins = "gpio142"; - input-enable; - bias-pull-up; - }; - - bios_flash_wp_l: bios-flash-wp-l { - pins = "gpio93"; - function = "gpio"; - input-enable; - bias-disable; - }; - - bt_en: bt-en { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - en_fp_rails: en-fp-rails { - pins = "gpio42"; - drive-strength = <2>; - output-high; - bias-disable; - }; - - en_pp3300_codec: en-pp3300-codec { - pins = "gpio67"; - drive-strength = <2>; - bias-disable; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp { - pins = "gpio80"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - en_pp3300_hub: en-pp3300-hub { - pins = "gpio24"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - fp_to_ap_irq_l: fp-to-ap-irq-l { - pins = "gpio61"; - function = "gpio"; - input-enable; - /* Has external pullup */ - bias-disable; - }; - - h1_ap_int_odl: h1-ap-int-odl { - pins = "gpio54"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - - hp_irq: hp-irq { - pins = "gpio101"; - function = "gpio"; - bias-pull-up; - }; - - p_sensor_int_l: p-sensor-int-l { - pins = "gpio141"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - - pen_irq_l: pen-irq-l { - pins = "gpio43"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - pen_pdct_l: pen-pdct-l { - pins = "gpio39"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - qup_spi8_cs_gpio_init_high: qup-spi8-cs-gpio-init-high { - pins = "gpio35"; - output-high; - }; - - qup_spi11_cs_gpio_init_high: qup-spi11-cs-gpio-init-high { - pins = "gpio47"; - output-high; - }; - - qup_spi12_cs_gpio_init_high: qup-spi12-cs-gpio-init-high { - pins = "gpio51"; - output-high; - }; - - qup_uart7_sleep_cts: qup-uart7-sleep-cts { - pins = "gpio28"; - function = "gpio"; - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; - }; - - qup_uart7_sleep_rts: qup-uart7-sleep-rts { - pins = "gpio29"; - function = "gpio"; - /* - * Configure pull-down on RTS. As RTS is active low - * signal, pull it low to indicate the BT SoC that it - * can wakeup the system anytime from suspend state by - * pulling RX low (by sending wakeup bytes). - */ - bias-pull-down; - }; - - qup_uart7_sleep_rx: qup-uart7-sleep-rx { - pins = "gpio31"; - function = "gpio"; - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module - * is floating which may cause spurious wakeups. - */ - bias-pull-up; - }; - - qup_uart7_sleep_tx: qup-uart7-sleep-tx { - pins = "gpio30"; - function = "gpio"; - /* - * Configure pull-up on TX when it isn't actively driven - * to prevent BT SoC from receiving garbage during sleep. - */ - bias-pull-up; - }; - - sd_cd: sd-cd { - pins = "gpio91"; - function = "gpio"; - bias-pull-up; - }; - - tp_int_odl: tp-int-odl { - pins = "gpio102"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - ts_int_l: ts-int-l { - pins = "gpio81"; - function = "gpio"; - /* Has external pullup */ - bias-pull-up; - }; - - ts_reset_l: ts-reset-l { - pins = "gpio105"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - drive-strength = <2>; - }; - - uf_cam_en: uf-cam-en { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - wf_cam_en: wf-cam-en { - pins = "gpio7"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; -}; From dbcbeed94f3b6f7f24349a7f335cc603a682e7a7 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Mar 2022 18:06:39 -0700 Subject: [PATCH 211/791] arm64: dts: qcom: sc7280-herobrine: Drop outputs on fpmcu pins Having these pins with outputs is good on a fresh boot because it puts the boot and reset pins in a known "good" state. Unfortunately, that conflicts with the fingerprint firmware flashing code. The firmware flashing process binds and unbinds the cros-ec and spidev drivers and that reapplies the pin output values after the flashing code has overridden the gpio values. This causes a problem because we try to put the device into bootloader mode, bind the spidev driver and that inadvertently puts it right back into normal boot mode, breaking the flashing process. Fix this by removing the outputs. We'll introduce a binding for fingerprint cros-ec specifically to set the gpios properly via gpio APIs during cros-ec driver probe instead. Cc: Douglas Anderson Cc: Matthias Kaehlcke Cc: Alexandru M Stan Fixes: 116f7cc43d28 ("arm64: dts: qcom: sc7280: Add herobrine-r1") Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220317010640.2498502-2-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 3d9b870d440b..10de5e104b4f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -727,7 +727,6 @@ ap_ec_spi: &spi10 { function = "gpio"; bias-disable; drive-strength = <2>; - output-high; }; fp_to_ap_irq_l: fp-to-ap-irq-l { @@ -741,7 +740,6 @@ ap_ec_spi: &spi10 { pins = "gpio68"; function = "gpio"; bias-disable; - output-low; }; gsc_ap_int_odl: gsc-ap-int-odl { From 516ca27b6033a07d7654e7838520f2c00b1ec606 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 25 Mar 2022 14:16:40 -0700 Subject: [PATCH 212/791] arm64: dts: qcom: sc7180-trogdor: Simplify SAR sensor enabling The SAR node, ap_sar_sensor, needs to be enabled in addition to the i2c bus it resides on. Let's simplify this by leaving the sensor node enabled by default while leaving the i2c bus disabled by default. On boards that use the sensor, we already enable the i2c bus so we can simply remove the extra bit that enables the sar sensor node. This saves some lines but is otherwise a non-functional change. Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325211640.54228-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 - 4 files changed, 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index e16ba7b01f25..eb20157f6af9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -13,10 +13,6 @@ compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180"; }; -&ap_sar_sensor { - status = "okay"; -}; - &ap_sar_sensor_i2c { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index c5c9feff41b8..8913592b2d82 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -20,10 +20,6 @@ "qcom,sc7180"; }; -&ap_sar_sensor { - status = "okay"; -}; - &ap_sar_sensor_i2c { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts index 344b57c035d0..8107f3d932eb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -17,10 +17,6 @@ compatible = "google,lazor-sku0", "qcom,sc7180"; }; -&ap_sar_sensor { - status = "okay"; -}; - &ap_sar_sensor_i2c { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 732e1181af48..b0efb354458c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -722,7 +722,6 @@ ap_sar_sensor_i2c: &i2c5 { vdd-supply = <&pp3300_a>; svdd-supply = <&pp1800_prox>; - status = "disabled"; label = "proximity-wifi"; }; }; From e7773dbc87674aec210432185d9624ed346a46f1 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Wed, 23 Mar 2022 21:48:40 +0100 Subject: [PATCH 213/791] arm64: dts: qcom: msm8994-huawei-angler: Add sdhc1 definition Angler does not have SD card, thus sdhc2 kept disabled. Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220323204840.22832-1-petr.vorel@gmail.com --- arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 0e3dd48f0dbf..6e43e4339f55 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2015, Huawei Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel + * Copyright (c) 2021-2022, Petr Vorel */ /dts-v1/; @@ -41,3 +41,8 @@ &tlmm { gpio-reserved-ranges = <85 4>; }; + +&sdhc1 { + status = "okay"; + mmc-hs400-1_8v; +}; From 9e5c45a5aac0ccb0d3433c8ea6b577c0473351ef Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 8 Apr 2022 13:42:04 +0200 Subject: [PATCH 214/791] arm64: dts: qcom: sm6350: Fix naming of uart9 The uart9 was previously mistakenly called uart2. Fix this. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220408114205.234635-1-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d7c9edff19f7..ef43af39569c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -529,13 +529,13 @@ ranges; status = "disabled"; - uart2: serial@98c000 { + uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x98c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; + pinctrl-0 = <&qup_uart9_default>; interrupts = ; status = "disabled"; }; @@ -974,7 +974,7 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; - qup_uart2_default: qup-uart2-default { + qup_uart9_default: qup-uart9-default { pins = "gpio25", "gpio26"; function = "qup13_f2"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index adb6ca2be2a5..67d14bda3797 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -23,7 +23,7 @@ qcom,board-id = <8 32>; aliases { - serial0 = &uart2; + serial0 = &uart9; }; chosen { @@ -332,7 +332,7 @@ gpio-reserved-ranges = <13 4>, <56 2>; }; -&uart2 { +&uart9 { status = "okay"; }; From 7be9f3ae250e97859e28c26daf457b1be3f58d17 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 8 Apr 2022 13:42:05 +0200 Subject: [PATCH 215/791] arm64: dts: qcom: sm6350: Add I2C busses Add nodes for the I2C busses on sm6350. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220408114205.234635-2-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 134 +++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index ef43af39569c..81db25952cf1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -517,6 +517,45 @@ }; }; + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x8c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu 0x43 0x0>; + ranges; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; @@ -529,6 +568,45 @@ ranges; status = "disabled"; + i2c6: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x98c000 0 0x4000>; @@ -539,6 +617,20 @@ interrupts = ; status = "disabled"; }; + + i2c10: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; tcsr_mutex: hwlock@1f40000 { @@ -980,6 +1072,48 @@ drive-strength = <2>; bias-disable; }; + + qup_i2c0_default: qup-i2c0-default { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default { + pins = "gpio13", "gpio14"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default { + pins = "gpio27", "gpio28"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default { + pins = "gpio19", "gpio20"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default { + pins = "gpio4", "gpio5"; + function = "qup14"; + drive-strength = <2>; + bias-pull-up; + }; }; apps_smmu: iommu@15000000 { From 413821b7777d062b57f8dc66ab088ed390cbc3ec Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 8 Apr 2022 13:53:10 +0200 Subject: [PATCH 216/791] arm64: dts: qcom: sm7225-fairphone-fp4: Add AW8695 haptics Add a node for the haptics driver found on the phone. Signed-off-by: Luca Weiss Reported-by: kernel test robot Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220408115311.237039-3-luca.weiss@fairphone.com --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 67d14bda3797..4691a5e5c8e5 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -296,6 +296,35 @@ firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; }; +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + haptics@5a { + compatible = "awinic,aw8695"; + reg = <0x5a>; + interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 90 GPIO_ACTIVE_HIGH>; + + awinic,f0-preset = <2350>; + awinic,f0-coefficient = <260>; + awinic,f0-calibration-percent = <7>; + awinic,drive-level = <125>; + + awinic,f0-detection-play-time = <5>; + awinic,f0-detection-wait-time = <3>; + awinic,f0-detection-repeat = <2>; + awinic,f0-detection-trace = <15>; + + awinic,boost-debug = /bits/ 8 <0x30 0xeb 0xd4>; + awinic,tset = /bits/ 8 <0x12>; + awinic,r-spare = /bits/ 8 <0x68>; + + awinic,bemf-upper-threshold = <4104>; + awinic,bemf-lower-threshold = <1016>; + }; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; From 50769f32af218c07b07096b55a5ecad319458609 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:11 +0200 Subject: [PATCH 217/791] ARM: dts: qcom: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407143112.294930-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 2 +- arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index 7a337dc08741..2fba904491d9 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -89,7 +89,7 @@ status = "okay"; cs-gpios = <&tlmm 12 0>; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts index 06f9f2cb2fe9..d596dd1180ae 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts @@ -52,7 +52,7 @@ status = "okay"; cs-gpios = <&tlmm 12 0>; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index 65330065390a..5c802b99e15f 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -36,7 +36,7 @@ cs-gpios = <&qcom_pinmux 20 0>; - flash: m25p80@0 { + flash: flash@0 { compatible = "s25fl256s1"; #address-cells = <1>; #size-cells = <1>; From 0f375d3aa6e2bde1c7c642caa0da37989d31f3e1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:57:50 +0200 Subject: [PATCH 218/791] ARM: dts: qcom: rename WCNSS child name to bluetooth The "bluetooth" is more popular and more descriptive than "bt", for a Bluetooth device. The WCNSS DT schema will expect such naming. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405065752.27389-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index a1c8ae516d21..4cdb1f7eae1e 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1548,7 +1548,7 @@ qcom,mmio = <&riva>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 412d94736c35..a249b05af9b1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -930,7 +930,7 @@ qcom,mmio = <&pronto>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; From 17c15a4ccf93e1bae322f1748bbd404165d90d92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:45 +0200 Subject: [PATCH 219/791] ARM: dts: qcom: ipq4019: align dmas in SPI/UART with DT schema The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-4-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index a9d0566a3190..1f6c4ab7f37e 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -253,8 +253,8 @@ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -267,8 +267,8 @@ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -281,8 +281,8 @@ clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -295,8 +295,8 @@ clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -382,8 +382,8 @@ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; }; blsp1_uart2: serial@78b0000 { @@ -394,8 +394,8 @@ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; }; watchdog: watchdog@b017000 { From bec819180790f27659176056273ffa4b6aa6c397 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:46 +0200 Subject: [PATCH 220/791] ARM: dts: qcom: ipq4019: align clocks in I2C with DT schema The DT schema expects clocks core-iface order. No functional change. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-5-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 1f6c4ab7f37e..897442157f5f 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -276,9 +276,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; dmas = <&blsp_dma 8>, <&blsp_dma 9>; @@ -290,9 +290,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b8000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; dmas = <&blsp_dma 10>, <&blsp_dma 11>; From e4cbe44ec67b0073aefdbcf6d0d6aa213b9b4328 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:47 +0200 Subject: [PATCH 221/791] ARM: dts: qcom: msm8660: disable GSBI8 The GSBI8 child node (I2C controller) is disabled, so as parent GSBI node should be the same. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-6-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8660.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index a258abb23a64..47b97daecef1 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -212,6 +212,7 @@ ranges; syscon-tcsr = <&tcsr>; + status = "disabled"; gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; From 09e3dac420316dbeedbf8d1d5d28901e87af5f4f Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Wed, 9 Feb 2022 16:57:41 +0000 Subject: [PATCH 222/791] ARM: dts: qcom: pm8226: add node for RTC Add a node for PM8226's real time clock. Signed-off-by: Jack Matthews Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220209165742.652890-1-jm5112356@gmail.com --- arch/arm/boot/dts/qcom-pm8226.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi index b3d0f7b5874d..bd23e4f9be02 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -40,6 +40,13 @@ chg_otg: otg-vbus { }; }; + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + pm8226_mpps: mpps@a000 { compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; reg = <0xa000>; From aff4d695b4eb3b279bfff53d2f06f464e363ee4a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 7 Apr 2022 17:52:54 -0500 Subject: [PATCH 223/791] arm64: dts: qcom: sdm845: shift6mq: Fix boolean properties with values Boolean properties in DT are present or not present and don't take a value. A property such as 'foo = <0>;' evaluated to true. IOW, the value doesn't matter. It may have been intended that 0 values are false, but there is no change in behavior with this patch. Cc: Andy Gross Cc: Bjorn Andersson Cc: Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring [bjorn: Updated subject prefix] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407225254.2178644-1-robh@kernel.org --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 8553c8bf79bd..103cc40816fd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -563,7 +563,7 @@ config { pins = "gpio6", "gpio11"; drive-strength = <8>; - bias-disable = <0>; + bias-disable; }; }; From 2b6d37f6b7fe2f98197b77adcce81d4198aeb305 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:12 +0200 Subject: [PATCH 224/791] arm64: dts: qcom: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407143112.294930-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 +- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 5aec18308712..821cb7c0c183 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -39,7 +39,7 @@ cs-select = <0>; status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index b5e1eaa367bf..de20cb98acd3 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -35,7 +35,7 @@ &blsp1_spi1 { status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 07e670829676..ce86d9b10d69 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -29,7 +29,7 @@ &blsp1_spi1 { status = "ok"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; From b32846a38fc2a68f6a9c1149b495fa4ca2552f20 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 11:27:23 +0200 Subject: [PATCH 225/791] arm64: dts: qcom: msm8996: drop unsupported UFS vddp-ref-clk-max-microamp The property vddp-ref-clk-max-microamp (for VDDP ref clk supply which is l25 regulator) is not documented in MSM8996 UFS PHY bindings (qcom,msm8996-qmp-ufs-phy). It is mentioned in the other UFS PHY bindings for qcom,msm8996-ufs-phy-qmp-14nm. The MSM8996-based Xiaomi devices configure l25 regulator in a conflicting way: 1. with maximum 100 uAmp for VDDP ref clk supply of UFS PHY, 2. with maximum 450 mAmp for VCCQ supply of UFS. Since the vddp-ref-clk-max-microamp property is basically not documented for that UFS PHY and has a conflicting values, drop it entirely as it looks like not tested and not used ever. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407092725.232463-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 7a9fcbe9bb31..3ade756e1cd9 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -341,7 +341,6 @@ vdda-pll-max-microamp = <9440>; vddp-ref-clk-supply = <&vreg_l25a_1p2>; - vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; }; From 64ff698424433dc5d2e827de2a4cc927300d7fe2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 11:27:24 +0200 Subject: [PATCH 226/791] arm64: dts: qcom: msm8996: correct UFS compatible The Qualcomm UFS bindings require to use specific (qcom,msm8996-ufshc) and generic (jedec,ufs-2.0) compatibles. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407092725.232463-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f0f81c23c16f..fa491f2271ff 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1730,7 +1730,8 @@ }; ufshc: ufshc@624000 { - compatible = "qcom,ufshc"; + compatible = "qcom,msm8996-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; reg = <0x00624000 0x2500>; interrupts = ; From 7ba57d11e5bb57095e6d312b518ae9ceb7efcbf1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 11:27:25 +0200 Subject: [PATCH 227/791] arm64: dts: qcom: sm8350: drop duplicated ref_clk in UFS ref_clk clock in UFS node is already there with a <0 0> frequency, which matches other DTSI files. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407092725.232463-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 20f850b94158..e70687d6c2da 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1916,7 +1916,6 @@ iommus = <&apps_smmu 0xe0 0x0>; clock-names = - "ref_clk", "core_clk", "bus_aggr_clk", "iface_clk", @@ -1926,7 +1925,6 @@ "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -1936,7 +1934,6 @@ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = - <75000000 300000000>, <75000000 300000000>, <0 0>, <0 0>, From cdbfb815d63a792fb565ab15c8f565833bb86c8b Mon Sep 17 00:00:00 2001 From: Manikanta Pubbisetty Date: Wed, 6 Apr 2022 16:43:03 +0530 Subject: [PATCH 228/791] arm64: dts: qcom: sc7280: Add WCN6750 WiFi node Add DTS node for WCN6750 WiFi chipset. Signed-off-by: Manikanta Pubbisetty Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220406111303.27670-1-quic_mpubbise@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 6 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 46 ++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 069ffbc37bc4..015a3474d401 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -551,3 +551,9 @@ status = "okay"; }; +&wifi { + status = "okay"; + wifi-firmware { + iommus = <&apps_smmu 0x1c02 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index b757e8ad1199..26f66f46a950 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -85,6 +85,11 @@ #size-cells = <2>; ranges; + wlan_ce_mem: memory@4cd000 { + no-map; + reg = <0x0 0x004cd000 0x0 0x1000>; + }; + hyp_mem: memory@80000000 { reg = <0x0 0x80000000 0x0 0x600000>; no-map; @@ -1808,6 +1813,47 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + wifi: wifi@17a10040 { + compatible = "qcom,wcn6750-wifi"; + reg = <0 0x17a10040 0 0x0>; + iommus = <&apps_smmu 0x1c00 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,rproc = <&remoteproc_wpss>; + memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; + status = "disabled"; + }; + pcie1: pci@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, From 0fa44edd0f8fe2bd829827adcc5659304c8ab7fa Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 6 Apr 2022 15:03:48 +0530 Subject: [PATCH 229/791] arm64: dts: qcom: sc7280: Set the default dr_mode for usb2 Set the default dr_mode for usb2 node to "otg" to enable role-switch for EUD(Embedded USB Debugger) connector node. Signed-off-by: Souradeep Chowdhury Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/451392a942f90aa9805b00afad7dff894604d189.1649235218.git.quic_schowdhu@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index a7be133a782f..6d3ff80582ae 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -90,7 +90,7 @@ }; &usb_2_dwc3 { - dr_mode = "host"; + dr_mode = "otg"; }; &usb_2_hsphy { From dcd0a663544fe978d658520709dfeaeb95ee855a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:57:51 +0200 Subject: [PATCH 230/791] arm64: dts: qcom: msm8916: rename WCNSS child name to bluetooth The "bluetooth" is more popular and more descriptive than "bt", for a Bluetooth device. The WCNSS DT schema will expect such naming. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405065752.27389-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e34963505e07..4209fbd52359 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1788,7 +1788,7 @@ qcom,mmio = <&pronto>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; From 0e1b27f4f69e86b8b62ba5bedb78936341433247 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:43 +0200 Subject: [PATCH 231/791] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 +++---- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 +++++++------- arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 +++++++++++++-------------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++--------- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index aac56575e30d..87c28ffa44d3 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -322,8 +322,8 @@ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -337,8 +337,8 @@ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index d80b1cefab10..2072638006a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -471,8 +471,8 @@ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-0 = <&i2c_0_pins>; pinctrl-names = "default"; status = "disabled"; @@ -488,8 +488,8 @@ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <100000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -503,8 +503,8 @@ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 21>, <&blsp_dma 20>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -518,8 +518,8 @@ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <100000>; - dmas = <&blsp_dma 23>, <&blsp_dma 22>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 22>, <&blsp_dma 23>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4209fbd52359..e90e9eb22810 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1485,8 +1485,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart1_default>; pinctrl-1 = <&blsp1_uart1_sleep>; @@ -1499,8 +1499,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart2_default>; pinctrl-1 = <&blsp1_uart2_sleep>; @@ -1529,8 +1529,8 @@ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_default>; pinctrl-1 = <&spi1_sleep>; @@ -1561,8 +1561,8 @@ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi2_default>; pinctrl-1 = <&spi2_sleep>; @@ -1593,8 +1593,8 @@ clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi3_default>; pinctrl-1 = <&spi3_sleep>; @@ -1625,8 +1625,8 @@ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi4_default>; pinctrl-1 = <&spi4_sleep>; @@ -1657,8 +1657,8 @@ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 13>, <&blsp_dma 12>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi5_default>; pinctrl-1 = <&spi5_sleep>; @@ -1689,8 +1689,8 @@ clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi6_default>; pinctrl-1 = <&spi6_sleep>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3f06f7cd3cf2..6b3a8e1006d0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -823,8 +823,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart0_default>; status = "disabled"; @@ -836,8 +836,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart1_default>; status = "disabled"; @@ -849,8 +849,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart2_default>; status = "okay"; @@ -903,8 +903,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart3_default>; status = "disabled"; @@ -1067,8 +1067,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_uart0_default>; status = "disabled"; From 2374b99e19ac7f2beca2d4e62ebb96803db0e66b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:44 +0200 Subject: [PATCH 232/791] arm64: dts: qcom: align clocks in I2C/SPI with DT schema The DT schema expects clocks core-iface order. No functional change. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++--- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++----- arch/arm64/boot/dts/qcom/msm8916.dtsi | 36 +++++++------- arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++--------- arch/arm64/boot/dts/qcom/msm8994.dtsi | 42 ++++++++-------- arch/arm64/boot/dts/qcom/msm8996.dtsi | 36 +++++++------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 72 +++++++++++++-------------- 7 files changed, 135 insertions(+), 135 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 87c28ffa44d3..8032d7933c66 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -318,9 +318,9 @@ #size-cells = <0>; reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; @@ -333,9 +333,9 @@ #size-cells = <0>; reg = <0x0 0x078b7000 0x0 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 2072638006a4..8e41c910b8f9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -467,9 +467,9 @@ #size-cells = <0>; reg = <0x078b6000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; @@ -484,9 +484,9 @@ #size-cells = <0>; reg = <0x078b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <100000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; @@ -499,9 +499,9 @@ #size-cells = <0>; reg = <0x78b9000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 20>, <&blsp_dma 21>; dma-names = "tx", "rx"; @@ -514,9 +514,9 @@ #size-cells = <0>; reg = <0x078ba000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <100000>; dmas = <&blsp_dma 22>, <&blsp_dma 23>; dma-names = "tx", "rx"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e90e9eb22810..c2713d307833 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1511,9 +1511,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b5000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; @@ -1543,9 +1543,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_default>; pinctrl-1 = <&i2c2_sleep>; @@ -1575,9 +1575,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b7000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c3_default>; pinctrl-1 = <&i2c3_sleep>; @@ -1607,9 +1607,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b8000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_default>; pinctrl-1 = <&i2c4_sleep>; @@ -1639,9 +1639,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b9000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_default>; pinctrl-1 = <&i2c5_sleep>; @@ -1671,9 +1671,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078ba000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c6_default>; pinctrl-1 = <&i2c6_sleep>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 431228faacdd..2a70263a701d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -923,9 +923,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b5000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_1_default>; @@ -941,9 +941,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b6000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_2_default>; @@ -959,9 +959,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b7000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_3_default>; pinctrl-1 = <&i2c_3_sleep>; @@ -976,9 +976,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b8000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_4_default>; pinctrl-1 = <&i2c_4_sleep>; @@ -993,9 +993,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af5000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_5_default>; pinctrl-1 = <&i2c_5_sleep>; @@ -1010,9 +1010,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af6000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_6_default>; pinctrl-1 = <&i2c_6_sleep>; @@ -1027,9 +1027,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af7000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_7_default>; pinctrl-1 = <&i2c_7_sleep>; @@ -1044,9 +1044,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af8000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_8_default>; pinctrl-1 = <&i2c_8_sleep>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8c1dc5155b71..209f9ef030e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -519,9 +519,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9923000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; @@ -555,9 +555,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; dma-names = "tx", "rx"; @@ -575,9 +575,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9926000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; dma-names = "tx", "rx"; @@ -593,9 +593,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9927000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; @@ -611,9 +611,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9928000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; dma-names = "tx", "rx"; @@ -657,9 +657,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9963000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; dma-names = "tx", "rx"; @@ -693,9 +693,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9967000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <355000>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index fa491f2271ff..db3eb160d1bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2787,9 +2787,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07577000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_i2c3_default>; pinctrl-1 = <&blsp1_i2c3_sleep>; @@ -2835,9 +2835,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b5000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c1_default>; pinctrl-1 = <&blsp2_i2c1_sleep>; @@ -2852,9 +2852,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b6000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c2_default>; pinctrl-1 = <&blsp2_i2c2_sleep>; @@ -2869,9 +2869,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b7000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c3_default>; @@ -2887,9 +2887,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x75b9000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_i2c5_default>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; @@ -2903,9 +2903,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x75ba000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c6_default>; pinctrl-1 = <&blsp2_i2c6_sleep>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 6b3a8e1006d0..acf120f91b42 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -914,9 +914,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c0_default>; #address-cells = <1>; @@ -928,9 +928,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi0_default>; #address-cells = <1>; @@ -942,9 +942,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c1_default>; #address-cells = <1>; @@ -956,9 +956,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b6000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi1_default>; #address-cells = <1>; @@ -970,9 +970,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c2_default>; #address-cells = <1>; @@ -984,9 +984,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi2_default>; #address-cells = <1>; @@ -998,9 +998,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b8000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c3_default>; #address-cells = <1>; @@ -1012,9 +1012,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b8000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi3_default>; #address-cells = <1>; @@ -1026,9 +1026,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b9000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c4_default>; #address-cells = <1>; @@ -1040,9 +1040,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b9000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi4_default>; #address-cells = <1>; @@ -1078,9 +1078,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_i2c0_default>; #address-cells = <1>; @@ -1092,9 +1092,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x07af5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_spi0_default>; #address-cells = <1>; From 6b834df8391b5f1ee710b4750d2ed39a6d0c693d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 3 Apr 2022 13:57:11 +0300 Subject: [PATCH 233/791] arm64: dts: qcom: sdm845-db845c: add wifi variant property Dragonboard845c doesn't have board-specific board-id programmed, it uses generic 0xff. Thus add the property with the 'variant' of the calibration data. Note: the driver will check for the calibration data for the following IDs, so older board-2.bin files that were distributed as a part of Linaro releases will continue to work. - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=30214,variant=Thundercomm_DB845C' - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=30214' - 'bus=snoc,qmi-board-id=ff' For the reference, the board is identified by the driver in the following way: ath10k_snoc 18800000.wifi: qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40030001 ath10k_snoc 18800000.wifi: qmi fw_version 0x2009856b fw_build_timestamp 2018-07-19 12:28 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.2.0-01387-QCAHLSWMTPLZ-1 Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403105711.1173161-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 28fe45c5d516..9206efa9d6d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1051,6 +1051,7 @@ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; qcom,snoc-host-cap-8bit-quirk; + qcom,ath10k-calibration-variant = "Thundercomm_DB845C"; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ From 876644c7603440279545fab4988edd424aea6d9f Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 3 Apr 2022 20:11:50 +0530 Subject: [PATCH 234/791] arm64: dts: qcom: sm8150: Add support for SDC2 Add support for SDC2 which can be used to interface uSD card. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403144151.92572-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 45 ++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 13547c15f321..c0128c960950 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3515,6 +3515,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd 0>; + operating-points-v2 = <&sdhc2_opp_table>; + + status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + dc_noc: interconnect@9160000 { compatible = "qcom,sm8150-dc-noc"; reg = <0 0x09160000 0 0x3200>; From 0deb2624e2d09aa158495ead66906fb437a67148 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 3 Apr 2022 20:11:51 +0530 Subject: [PATCH 235/791] arm64: dts: qcom: sa8155p-adp: Add support for uSD card Add support for uSD card on SA8155p-ADP board using the SDHC2 interface. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403144151.92572-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 676e4fe3f848..8e781125e8d0 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -317,6 +317,20 @@ firmware-name = "qcom/sa8155p/cdsp.mdt"; }; +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */ + vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */ + bus-width = <4>; + no-sdio; + no-emmc; +}; + &uart2 { status = "okay"; }; @@ -405,6 +419,60 @@ &tlmm { gpio-reserved-ranges = <0 4>; + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; /* No pull */ + drive-strength = <16>; /* 16 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + sd-cd { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; /* No pull */ + drive-strength = <2>; /* 2 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + sd-cd { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + usb2phy_ac_en1_default: usb2phy_ac_en1_default { mux { pins = "gpio113"; From 902d97a44211b17bae49442b770ac5311b7c0b32 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:16 +0000 Subject: [PATCH 236/791] arm64: dts: qcom: msm8996: Revamp reserved memory Fix a total overlap between zap_shader_region and slpi_region, and rename all regions to match the naming convention in other Qualcomm SoC device trees. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-2-y.oudjana@protonmail.com --- .../dts/qcom/msm8996-sony-xperia-tone.dtsi | 18 +++-- .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 18 ++--- arch/arm64/boot/dts/qcom/msm8996.dtsi | 67 ++++++++++--------- 3 files changed, 57 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 3bb50cecd62d..ca3c633f5a45 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -13,9 +13,10 @@ #include #include -/delete-node/ &slpi_region; -/delete-node/ &venus_region; -/delete-node/ &zap_shader_region; +/delete-node/ &adsp_mem; +/delete-node/ &slpi_mem; +/delete-node/ &venus_mem; +/delete-node/ &gpu_mem; / { qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */ @@ -46,18 +47,23 @@ no-map; }; - zap_shader_region: gpu@90400000 { + adsp_mem: adsp@8ea00000 { + reg = <0x0 0x8ea00000 0x0 0x1a00000>; + no-map; + }; + + gpu_mem: gpu@90400000 { compatible = "shared-dma-pool"; reg = <0x0 0x90400000 0x0 0x2000>; no-map; }; - slpi_region: memory@90500000 { + slpi_mem: memory@90500000 { reg = <0 0x90500000 0 0xa00000>; no-map; }; - venus_region: memory@90f00000 { + venus_mem: memory@90f00000 { reg = <0 0x90f00000 0 0x500000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 3ade756e1cd9..d3ac943a00fb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -66,32 +66,32 @@ /* This platform has all PIL regions offset by 0x1400000 */ /delete-node/ mpss@88800000; - mpss_region: mpss@89c00000 { + mpss_mem: mpss@89c00000 { reg = <0x0 0x89c00000 0x0 0x6200000>; no-map; }; /delete-node/ adsp@8ea00000; - adsp_region: adsp@8ea00000 { + adsp_mem: adsp@8fe00000 { reg = <0x0 0x8fe00000 0x0 0x1b00000>; no-map; }; - /delete-node/ slpi@90b00000; - slpi_region: slpi@91900000 { + /delete-node/ slpi@90500000; + slpi_mem: slpi@91900000 { reg = <0x0 0x91900000 0x0 0xa00000>; no-map; }; - /delete-node/ gpu@8f200000; - zap_shader_region: gpu@92300000 { + /delete-node/ gpu@90f00000; + gpu_mem: gpu@92300000 { compatible = "shared-dma-pool"; reg = <0x0 0x92300000 0x0 0x2000>; no-map; }; /delete-node/ venus@91000000; - venus_region: venus@90400000 { + venus_mem: venus@92400000 { reg = <0x0 0x92400000 0x0 0x500000>; no-map; }; @@ -107,7 +107,7 @@ pmsg-size = <0x40000>; }; - /delete-node/ rmtfs@86700000; + /delete-node/ rmtfs; rmtfs@f6c00000 { compatible = "qcom,rmtfs-mem"; reg = <0 0xf6c00000 0 0x200000>; @@ -118,7 +118,7 @@ }; /delete-node/ mba@91500000; - mba_region: mba@f6f00000 { + mba_mem: mba@f6f00000 { reg = <0x0 0xf6f00000 0x0 0x100000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index db3eb160d1bb..dd4b2b370264 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -384,28 +384,13 @@ #size-cells = <2>; ranges; - mba_region: mba@91500000 { - reg = <0x0 0x91500000 0x0 0x200000>; + hyp_mem: memory@85800000 { + reg = <0x0 0x85800000 0x0 0x600000>; no-map; }; - slpi_region: slpi@90b00000 { - reg = <0x0 0x90b00000 0x0 0xa00000>; - no-map; - }; - - venus_region: venus@90400000 { - reg = <0x0 0x90400000 0x0 0x700000>; - no-map; - }; - - adsp_region: adsp@8ea00000 { - reg = <0x0 0x8ea00000 0x0 0x1a00000>; - no-map; - }; - - mpss_region: mpss@88800000 { - reg = <0x0 0x88800000 0x0 0x6200000>; + xbl_mem: memory@85e00000 { + reg = <0x0 0x85e00000 0x0 0x200000>; no-map; }; @@ -414,17 +399,12 @@ no-map; }; - memory@85800000 { - reg = <0x0 0x85800000 0x0 0x800000>; - no-map; - }; - - memory@86200000 { + tz_mem: memory@86200000 { reg = <0x0 0x86200000 0x0 0x2600000>; no-map; }; - rmtfs@86700000 { + rmtfs_mem: rmtfs { compatible = "qcom,rmtfs-mem"; size = <0x0 0x200000>; @@ -435,9 +415,34 @@ qcom,vmid = <15>; }; - zap_shader_region: gpu@8f200000 { + mpss_mem: mpss@88800000 { + reg = <0x0 0x88800000 0x0 0x6200000>; + no-map; + }; + + adsp_mem: adsp@8ea00000 { + reg = <0x0 0x8ea00000 0x0 0x1b00000>; + no-map; + }; + + slpi_mem: slpi@90500000 { + reg = <0x0 0x90500000 0x0 0xa00000>; + no-map; + }; + + gpu_mem: gpu@90f00000 { compatible = "shared-dma-pool"; - reg = <0x0 0x90b00000 0x0 0xa00000>; + reg = <0x0 0x90f00000 0x0 0x100000>; + no-map; + }; + + venus_mem: venus@91000000 { + reg = <0x0 0x91000000 0x0 0x500000>; + no-map; + }; + + mba_mem: mba@91500000 { + reg = <0x0 0x91500000 0x0 0x200000>; no-map; }; }; @@ -1033,7 +1038,7 @@ }; zap-shader { - memory-region = <&zap_shader_region>; + memory-region = <&gpu_mem>; }; }; @@ -2027,7 +2032,7 @@ <&venus_smmu 0x2c>, <&venus_smmu 0x2d>, <&venus_smmu 0x31>; - memory-region = <&venus_region>; + memory-region = <&venus_mem>; status = "disabled"; video-decoder { @@ -3034,7 +3039,7 @@ clocks = <&rpmcc RPM_SMD_BB_CLK1>; clock-names = "xo"; - memory-region = <&adsp_region>; + memory-region = <&adsp_mem>; qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; From 6d338feb553a32efee3ca50f503ab36e01455924 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:28 +0000 Subject: [PATCH 237/791] arm64: dts: qcom: msm8996: Unify smp2p naming Rename smp2p-modem to smp2p-mpss, and make the subnode labels of smp2p_adsp and smp2p_slpi follow the _smp2p_ layout. Also move smp2p_slpi_out above smp2p_slpi_in to make it match mpss and adsp where master-kernel is the first subnode. This patch brings no functional change. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-4-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 35 ++++++++++++++------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index dd4b2b370264..b7b5b17f9dd7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -518,12 +518,12 @@ qcom,local-pid = <0>; qcom,remote-pid = <2>; - smp2p_adsp_out: master-kernel { + adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; - smp2p_adsp_in: slave-kernel { + adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; @@ -531,7 +531,7 @@ }; }; - smp2p-modem { + smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -542,12 +542,12 @@ qcom,local-pid = <0>; qcom,remote-pid = <1>; - modem_smp2p_out: master-kernel { + mpss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; - modem_smp2p_in: slave-kernel { + mpss_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; @@ -566,16 +566,17 @@ qcom,local-pid = <0>; qcom,remote-pid = <3>; - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - smp2p_slpi_out: master-kernel { + slpi_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; + + slpi_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; }; soc: soc { @@ -3029,10 +3030,10 @@ reg = <0x09300000 0x80000>; interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; @@ -3041,7 +3042,7 @@ memory-region = <&adsp_mem>; - qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; power-domains = <&rpmpd MSM8996_VDDCX>; From 127dd2f08d274d9be9a6b1172035ebf7b7d51bc7 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:35 +0000 Subject: [PATCH 238/791] arm64: dts: qcom: msm8996: Add MSS and SLPI Add nodes for the MSS and SLPI remoteprocs. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-5-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 99 +++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b7b5b17f9dd7..e918038e8bd3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2129,6 +2129,105 @@ clock-names = "iface", "bus"; }; + slpi_pil: remoteproc@1c00000 { + compatible = "qcom,msm8996-slpi-pil"; + reg = <0x01c00000 0x4000>; + + interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&xo_board>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + clock-names = "xo", "aggre2"; + + memory-region = <&slpi_mem>; + + qcom,smem-states = <&slpi_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + power-domains = <&rpmpd MSM8996_VDDSSCX>; + power-domain-names = "ssc_cx"; + + status = "disabled"; + + smd-edge { + interrupts = ; + + label = "dsps"; + mboxes = <&apcs_glb 25>; + qcom,smd-edge = <3>; + qcom,remote-pid = <3>; + }; + }; + + mss_pil: remoteproc@2080000 { + compatible = "qcom,msm8996-mss-pil"; + reg = <0x2080000 0x100>, + <0x2180000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>, + <&gcc GCC_MSS_GPLL0_DIV_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, + <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", + "snoc_axi", "mnoc_axi", "pnoc", "qdss"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + power-domains = <&rpmpd MSM8996_VDDCX>, + <&rpmpd MSM8996_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&mpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + smd-edge { + interrupts = ; + + label = "mpss"; + mboxes = <&apcs_glb 12>; + qcom,smd-edge = <0>; + qcom,remote-pid = <1>; + }; + }; + stm@3002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x3002000 0x1000>, From 73f7731b6831876fb61c32be1e75c4ad6ac25dbf Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:45 +0000 Subject: [PATCH 239/791] arm64: dts: qcom: msm8996-xiaomi-*: Enable MSS and SLPI Enable mss_pil and slpi_pil and set their firmware paths. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-6-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 9 +++++++++ arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts | 9 +++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index d3ac943a00fb..fdb70227c0fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -267,6 +267,12 @@ vdd-gfx-supply = <&vdd_gfx>; }; +&mss_pil { + status = "okay"; + + pll-supply = <&vreg_l12a_1p8>; +}; + &pcie0 { status = "okay"; @@ -291,6 +297,12 @@ linux,code = ; }; +&slpi_pil { + status = "okay"; + + px-supply = <&vreg_lvs2a_1p8>; +}; + &usb3 { status = "okay"; extcon = <&typec>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 34f82e06ef53..22978d06f85b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -130,6 +130,11 @@ status = "okay"; }; +&mss_pil { + firmware-name = "qcom/msm8996/gemini/mba.mbn", + "qcom/msm8996/gemini/modem.mbn"; +}; + &q6asmdai { dai@0 { reg = <0>; @@ -144,6 +149,10 @@ }; }; +&slpi_pil { + firmware-name = "qcom/msm8996/gemini/slpi.mbn"; +}; + &sound { compatible = "qcom,apq8096-sndcard"; model = "gemini"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index 27a45ddbb5bd..1e2dd6763ad1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -111,6 +111,11 @@ status = "disabled"; }; +&mss_pil { + firmware-name = "qcom/msm8996/scorpio/mba.mbn", + "qcom/msm8996/scorpio/modem.mbn"; +}; + &q6asmdai { dai@0 { reg = <0>; @@ -125,6 +130,10 @@ }; }; +&slpi_pil { + firmware-name = "qcom/msm8996/scorpio/slpi.mbn"; +}; + &sound { compatible = "qcom,apq8096-sndcard"; model = "scorpio"; From 61fd9113f0c743153c76f6bc72938800bbb57ccc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 3 Apr 2022 22:39:11 +0300 Subject: [PATCH 240/791] arm64: dts: qcom: apq8096-db820c: enable MSS node APQ8096 provides a 'modem' with reduced functionality, mainly targeting location services. Enable corresponding device tree node. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403193911.1393920-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index f623db8451f1..56e54ce4d10e 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -258,6 +258,12 @@ vdd-gfx-supply = <&vdd_gfx>; }; +&mss_pil { + status = "okay"; + pll-supply = <&vreg_l12a_1p8>; + firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn"; +}; + &pm8994_resin { status = "okay"; linux,code = ; From b4f3996c756ad9e13a6c5ce06c56c2f1dd05768d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 11 Apr 2022 14:58:07 +0300 Subject: [PATCH 241/791] arm64: dts: qcom: sdm845: remove snps,dw-pcie compatibles On SDM845 PCI controller bindings are not compatible with snps,dw-pcie binding. The platform doesn't provide second (global) IRQ, it requires additional glue code. To prevent it from probing against the dw-pcie driver, remove corresponding compatible. Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Fixes: 42ad231338c1 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411115808.1976500-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b31bf62e8680..85dfa0842003 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2027,7 +2027,7 @@ }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -2132,7 +2132,7 @@ }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + compatible = "qcom,pcie-sdm845"; reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, From 66d7cadb7a4362b317764b7bb859ef76bddfe43a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 11 Apr 2022 14:58:08 +0300 Subject: [PATCH 242/791] arm64: dts: qcom: msm8996: remove snps,dw-pcie compatibles On MSM8996 PCI controller bindings are not compatible with snps,dw-pcie binding. The platform doesn't provide second (global) IRQ, it requires additional glue code. To prevent it from probing against the dw-pcie driver, remove corresponding compatible. Fixes: ed965ef89227 ("arm64: dts: qcom: msm8996: add support to pcie") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411115808.1976500-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e918038e8bd3..1a1539399a87 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1580,7 +1580,7 @@ ranges; pcie0: pcie@600000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; status = "disabled"; power-domains = <&gcc PCIE0_GDSC>; bus-range = <0x00 0xff>; @@ -1632,7 +1632,7 @@ }; pcie1: pcie@608000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; power-domains = <&gcc PCIE1_GDSC>; bus-range = <0x00 0xff>; num-lanes = <1>; @@ -1685,7 +1685,7 @@ }; pcie2: pcie@610000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; power-domains = <&gcc PCIE2_GDSC>; bus-range = <0x00 0xff>; num-lanes = <1>; From b36e493cecae89038ccafc59fb45ded3ae8a9bf4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Apr 2022 23:59:00 +0300 Subject: [PATCH 243/791] arm64: dts: qcom: sm8450-hdk: Enable remoteproc instances Enable the audio, compute, sensor and modem remoteproc and specify firmware path for these on the Qualcomm SM8450 HDK. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410205901.1672089-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index f0fcb1428449..34e37991c0c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -349,6 +349,26 @@ }; }; +&remoteproc_adsp { + status = "okay"; + firmware-name = "qcom/sm8450/adsp.mbn"; +}; + +&remoteproc_cdsp { + status = "okay"; + firmware-name = "qcom/sm8450/cdsp.mbn"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8450/modem.mbn"; +}; + +&remoteproc_slpi { + status = "okay"; + firmware-name = "qcom/sm8450/slpi.mbn"; +}; + &qupv3_id_0 { status = "okay"; }; From 91d70eb70867f3fa4f0380c68253cda9e77e8bfc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Apr 2022 23:59:01 +0300 Subject: [PATCH 244/791] arm64: dts: qcom: sm8450: add fastrpc nodes Add fastrpc device tree nodes for aDSP, cDSP and SLPI. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410205901.1672089-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 119 +++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 934e29b9e153..385892330017 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -887,6 +887,33 @@ label = "slpi"; qcom,remote-pid = <3>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + /* note: shared-cb = <4> in downstream */ + }; + }; }; }; @@ -927,6 +954,32 @@ label = "lpass"; qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1803 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1804 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1805 0x0>; + }; + }; }; }; @@ -967,6 +1020,72 @@ label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x2161 0x0400>, + <&apps_smmu 0x1021 0x1420>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x2162 0x0400>, + <&apps_smmu 0x1022 0x1420>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x2163 0x0400>, + <&apps_smmu 0x1023 0x1420>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x2164 0x0400>, + <&apps_smmu 0x1024 0x1420>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x2165 0x0400>, + <&apps_smmu 0x1025 0x1420>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x2166 0x0400>, + <&apps_smmu 0x1026 0x1420>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x2167 0x0400>, + <&apps_smmu 0x1027 0x1420>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x2168 0x0400>, + <&apps_smmu 0x1028 0x1420>; + }; + + /* note: secure cb9 in downstream */ + }; }; }; From 6127d8e4cd096c4f5c8590617e22a2fdc80aee30 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 27 Feb 2022 00:10:28 +0530 Subject: [PATCH 245/791] arm64: dts: qcom: sm8150: Add PDC as the interrupt parent for tlmm Several wakeup gpios supported by the Top Level Mode Multiplexer (TLMM) block on sm8150 can be used as interrupt sources and these interrupts are routed to the PDC interrupt controller. So, specify PDC as the interrupt parent for the TLMM block. Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226184028.111566-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c0128c960950..068cf3e3e89f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2247,6 +2247,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; qup_i2c0_default: qup-i2c0-default { mux { From 0e0a8e35d72533b3eef3365e900baacd7cede8e2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Mar 2022 17:11:04 +0300 Subject: [PATCH 246/791] arm64: dts: qcom: sdm845: correct dynamic power coefficients MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Following sm8150/sm8250 update sdm845 capacity-dmips-mhz and dynamic-power-coefficient based on the measurements [1], [2]. The energy model dynamic-power-coefficient values were calculated with DPC = µW / MHz / V^2 for each OPP, and averaged across all OPPs within each cluster for the final coefficient. Voltages were obtained from the qcom-cpufreq-hw driver that reads voltages from the OSM LUT programmed into the SoC. Normalized DMIPS/MHz capacity scale values for each CPU were calculated from CoreMarks/MHz (CoreMark iterations per second per MHz), which serves the same purpose. For each CPU, the final capacity-dmips-mhz value is the C/MHz value of its maximum frequency normalized to SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system. For more details on measurement process see the commit message for the commit 6aabed5526ee ("arm64: dts: qcom: sm8250: Add CPU capacities and energy model"). [1] https://github.com/kdrag0n/freqbench [2] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main Cc: Danny Lin Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220315141104.730235-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 85dfa0842003..a49376d8ecbf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -200,8 +200,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -225,8 +225,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -247,8 +247,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -269,8 +269,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -292,7 +292,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -314,7 +314,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -336,7 +336,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -358,7 +358,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, From 5a814af5fc229b2649c814921a39ae1f652e366d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 21 Mar 2022 14:33:17 +0100 Subject: [PATCH 247/791] arm64: dts: qcom: sm6350: Add UFS nodes Add the necessary nodes for UFS and its PHY. Signed-off-by: Luca Weiss Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220321133318.99406-6-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 81db25952cf1..f6fb97d5ca92 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -633,6 +633,83 @@ }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm6350-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>, + <0 0x01d90000 0 0x8000>; + reg-names = "std", "ice"; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0x80 0x0>; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk", + "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_QLINK_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm6350-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x18c>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x128>, + <0 0x01d87600 0 0x1fc>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x128>, + <0 0x01d87a00 0 0x1fc>; + #phy-cells = <0>; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; From 606efee95767b54e8da4cce0429f1587ff1a3cb0 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 21 Mar 2022 14:33:18 +0100 Subject: [PATCH 248/791] arm64: dts: qcom: sm7225-fairphone-fp4: Enable UFS Configure and enable the nodes for UFS that are used for internal storage on FP4. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220321133318.99406-7-luca.weiss@fairphone.com --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 4691a5e5c8e5..f70174a342c6 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -365,6 +365,24 @@ status = "okay"; }; +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7e>; + vcc-max-microamp = <800000>; + vccq2-supply = <&vreg_l12a>; + vccq2-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l18a>; + vdda-pll-supply = <&vreg_l22a>; +}; + &usb_1 { status = "okay"; }; From 05f333b746d48c985f6df3c4e7cc8e63a0f30840 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 25 Mar 2022 22:05:36 +0530 Subject: [PATCH 249/791] arm64: dts: qcom: sm8150: add ethernet node SM8150 SoC supports ethqos ethernet controller so add the node for it Cc: Bjorn Andersson Signed-off-by: Vinod Koul [bhsharma: Correct ethernet interrupt numbers and add power-domain] Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325163537.1579969-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 068cf3e3e89f..f0c550155d03 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -915,6 +915,33 @@ status = "disabled"; }; + ethernet: ethernet@20000 { + compatible = "qcom,sm8150-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + resets = <&gcc GCC_EMAC_BCR>; + + iommus = <&apps_smmu 0x3C0 0x0>; + + snps,tso; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; From c5cb42cc8411c8313b0265777b90715e6d032ba1 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 25 Mar 2022 22:05:37 +0530 Subject: [PATCH 250/791] arm64: dts: qcom: sa8155p-adp: Enable ethernet node Enable the ethernet node, add the phy node and pinctrl for ethernet. [bhsharma: Correct ethernet/rgmii related pinmuxs, specify multi-queues and plug in the PHY interrupt for WOL] Cc: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325163537.1579969-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 146 +++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 8e781125e8d0..8034d0d31bd0 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -47,6 +47,65 @@ vin-supply = <&vreg_3p3>; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xC>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; }; &apps_rsc { @@ -303,6 +362,44 @@ }; }; +ðernet { + status = "okay"; + + snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 70000>; + + snps,ptp-ref-clk-rate = <250000000>; + snps,ptp-req-clk-rate = <96000000>; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet_defaults>; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + max-speed = <1000>; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + + compatible = "snps,dwmac-mdio"; + + /* Micrel KSZ9031RNZ PHY */ + rgmii_phy: phy@7 { + reg = <0x7>; + + interrupt-parent = <&tlmm>; + interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ + device_type = "ethernet-phy"; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + &qupv3_id_1 { status = "okay"; }; @@ -490,4 +587,53 @@ drive-strength = <2>; }; }; + + ethernet_defaults: ethernet-defaults { + mdc { + pins = "gpio7"; + function = "rgmii"; + bias-pull-up; + }; + + mdio { + pins = "gpio59"; + function = "rgmii"; + bias-pull-up; + }; + + rgmii-rx { + pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx { + pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + + phy-intr { + pins = "gpio124"; + function = "emac_phy"; + bias-disable; + drive-strength = <8>; + }; + + pps { + pins = "gpio81"; + function = "emac_pps"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset { + pins = "gpio79"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + }; }; From e036b77be77d232f41a1f6dd91e4f1f238cbb680 Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Wed, 16 Mar 2022 23:05:46 +0530 Subject: [PATCH 251/791] arm64: dts: qcom: sc7280: rename edp_out label to mdss_edp_out Rename the edp_out label in the sc7280 platform to mdss_edp_out so that the nodes related to mdss are all grouped together in the board specific files. Signed-off-by: Sankeerth Billakanti Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647452154-16361-2-git-send-email-quic_sbillaka@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 26f66f46a950..0cb126a7a8d0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3393,7 +3393,7 @@ port@1 { reg = <1>; - edp_out: endpoint { }; + mdss_edp_out: endpoint { }; }; }; From 726111e687192575e47de9e286ad0e45e2ce1466 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 25 Feb 2022 23:56:42 +0200 Subject: [PATCH 252/791] arm64: dts: qcom: msm8998-oneplus-common: Add NFC The OnePlus 5/5T both have an NXP PN553 which is supported by the nxp-nci-i2c driver in mainline. It detects/reads NFC tags using "nfctool" and with the NearD test scripts data can also be written to be received by another device. Signed-off-by: Jami Kettunen Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220225215642.3916-1-jami.kettunen@somainline.org --- .../boot/dts/qcom/msm8998-oneplus-common.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 9823d48a91b1..dbaea360bffc 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -188,6 +188,23 @@ }; }; +&blsp1_i2c6 { + status = "okay"; + + nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + }; +}; + &blsp1_uart3 { status = "okay"; @@ -462,6 +479,20 @@ drive-strength = <8>; bias-pull-up; }; + + nfc_int_active: nfc-int-active { + pins = "gpio92"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + nfc_enable_active: nfc-enable-active { + pins = "gpio12", "gpio116"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; }; &ufshc { From a2d2c809cfeeb35b9e0a17940fcee90ff195b592 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 28 Feb 2022 08:58:44 +0200 Subject: [PATCH 253/791] arm64: dts: qcom: ipq6018: Add mdio bus description The IPQ60xx has the same MDIO bug block as IPQ4019. Add IO range and clock resources description. Reviewed-by: Bryan O'Donoghue Signed-off-by: Baruch Siach Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/ef01a79ccc6ef86dc3a10d0fa3331794d49e9859.1646031524.git.baruch@tkos.co.il --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 8032d7933c66..bbe58b92079a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -630,6 +630,16 @@ }; }; + mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; + reg = <0x0 0x90000 0x0 0x64>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + qusb_phy_1: qusb@59000 { compatible = "qcom,ipq6018-qusb2-phy"; reg = <0x0 0x059000 0x0 0x180>; From 7a79b95f4288c67b72a1c90c90a4fb6ad6fc0c6d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:29 +0300 Subject: [PATCH 254/791] arm64: dts: qcom: pm8350: add temp sensor and thermal zone config Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8350.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index 308f9ca7c744..b10f33afa5e3 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -6,6 +6,30 @@ #include #include +/ { + thermal-zones { + pm8350_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350_temp_alarm>; + + trips { + pm8350_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8350: pmic@1 { compatible = "qcom,pm8350", "qcom,spmi-pmic"; @@ -13,6 +37,13 @@ #address-cells = <1>; #size-cells = <0>; + pm8350_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm8350_gpios: gpio@8800 { compatible = "qcom,pm8350-gpio"; reg = <0x8800>; From 5c1399299d9d82cb378bd22049da0ae08c4efa54 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:30 +0300 Subject: [PATCH 255/791] arm64: dts: qcom: pm8350b: add temp sensor and thermal zone config Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8350b.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index b23bb1d49a4d..f1d1d4c8edf8 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -6,6 +6,30 @@ #include #include +/ { + thermal-zones { + pm8350b_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_temp_alarm>; + + trips { + pm8350b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350b_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8350b: pmic@3 { compatible = "qcom,pm8350b", "qcom,spmi-pmic"; @@ -13,6 +37,13 @@ #address-cells = <1>; #size-cells = <0>; + pm8350b_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm8350b_gpios: gpio@8800 { compatible = "qcom,pm8350b-gpio"; reg = <0x8800>; From 6f3426b3dea42abbe8d797560966056303d7cbd6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:31 +0300 Subject: [PATCH 256/791] arm64: dts: qcom: pmr735b: add temp sensor and thermal zone config Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pmr735b.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index 1144086280f5..604324188603 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -6,6 +6,30 @@ #include #include +/ { + thermal-zones { + pmr735a_thermal: pmr735a-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmr735b_temp_alarm>; + + trips { + pmr735b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735b_crit: pmr735a-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmr735b: pmic@5 { compatible = "qcom,pmr735b", "qcom,spmi-pmic"; @@ -13,6 +37,13 @@ #address-cells = <1>; #size-cells = <0>; + pmr735b_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmr735b_gpios: gpio@8800 { compatible = "qcom,pmr735b-gpio"; reg = <0x8800>; From d67ddd17dedd1b7f1c287a9f32f5db084a7c85eb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:32 +0300 Subject: [PATCH 257/791] arm64: dts: qcom: pm8350c: stop depending on thermal_zones label Most of SoC device trees do not provide the thermal_zones label. Thus stop depending on it and use the full path to the thermal zones nodes. Fixes: 3795fe7d497b ("arm64: dts: qcom: pm8350c: Add temp-alarm support") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 32 ++++++++++++++------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index e1b75ae0a823..9bc6464477bd 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -32,23 +32,25 @@ }; }; -&thermal_zones { - pm8350c_thermal: pm8350c-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&pm8350c_temp_alarm>; +/ { + thermal-zones { + pm8350c_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350c_temp_alarm>; - trips { - pm8350c_trip0: trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; + trips { + pm8350c_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; - pm8350c_crit: pm8350c-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; + pm8350c_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; }; }; }; From 7dc11169a0990f7efcd9515e012f9257aa6035b6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:33 +0300 Subject: [PATCH 258/791] arm64: dts: qcom: pmr735a: stop depending on thermal_zones label Most of SoC device trees do not provide the thermal_zones label. Thus stop depending on it and use the full path to the thermal zones nodes. Fixes: 7a3544e5d4e8 ("arm64: dts: qcom: pmr735a: Add temp-alarm support") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pmr735a.dtsi | 32 ++++++++++++++------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi index b4b6ba24f845..febda50779f9 100644 --- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi @@ -32,23 +32,25 @@ }; }; -&thermal_zones { - pmr735a_thermal: pmr735a-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&pmr735a_temp_alarm>; +/ { + thermal-zones { + pmr735a_thermal: pmr735a-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmr735a_temp_alarm>; - trips { - pmr735a_trip0: trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; + trips { + pmr735a_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; - pmr735a_crit: pmr735a-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; + pmr735a_crit: pmr735a-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; }; }; }; From 64d3cb73b317a60d162f08533533aa5f1d9cfe72 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:35 +0300 Subject: [PATCH 259/791] arm64: dts: qcom: add pm8450 support Add PM8450 PMIC device tree include file. It is going to be used by SM8450-based devices. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-8-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8450.dtsi | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8450.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8450.dtsi b/arch/arm64/boot/dts/qcom/pm8450.dtsi new file mode 100644 index 000000000000..ae5bce3cf46e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8450.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8450-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8450_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8450: pmic@7 { + compatible = "qcom,pm8450", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8450_gpios: gpio@8800 { + compatible = "qcom,pm8450-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8450_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From c38406aa46da8f417ee30e6ba1fad71f891ec8be Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 28 Feb 2022 23:54:00 +0100 Subject: [PATCH 260/791] arm64: dts: qcom: msm8916: Add BAM-DMUX for WWAN network interfaces The BAM Data Multiplexer provides access to the network data channels of modems integrated into many older Qualcomm SoCs, including MSM8916. Add the nodes for the BAM DMA engine and BAM-DMUX to enable using WWAN on smartphones/tablets based on MSM8916. This should work out of the box with open-source WWAN userspace such as ModemManager. The nodes are disabled by default to avoid loading unnecessary drivers on devices that cannot use BAM-DMUX (e.g. DragonBoard 410c). However, strictly speaking the nodes could be enabled by default since both the bam_dma and bam_dmux driver will simply do nothing if the modem does not announce any BAM-DMUX channels. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228225400.146555-3-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c2713d307833..0f72349d4067 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1314,6 +1314,20 @@ #interrupt-cells = <4>; }; + bam_dmux_dma: dma-controller@4044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x04044000 0x19000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + + status = "disabled"; + }; + mpss: remoteproc@4080000 { compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; reg = <0x04080000 0x100>, @@ -1357,6 +1371,22 @@ memory-region = <&mpss_mem>; }; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&hexagon_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + smd-edge { interrupts = ; From cde8b4d070bd98587f5e13a5a5e63e88cfe31322 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:14 +0530 Subject: [PATCH 261/791] arm64: dts: qcom: msm8996-xiaomi: Drop max-microamp and vddp-ref-clk properties from QMP PHY The following properties are not supported and causing dtbs_check warnings. - vdda-phy-max-microamp - vdda-pll-max-microamp - vddp-ref-clk-max-microamp - vddp-ref-clk-always-on arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dt.yaml: phy@627000: 'vdda-phy-max-microamp', 'vddp-ref-clk-always-on', 'vddp-ref-clk-max-microamp' do not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Drop them from QMP PHY nodes for 'msm8996-xiaomi' dts. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-4-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index fdb70227c0fa..be4f643b1fd1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -348,12 +348,7 @@ vdda-phy-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; - - vdda-phy-max-microamp = <18380>; - vdda-pll-max-microamp = <9440>; - vddp-ref-clk-supply = <&vreg_l25a_1p2>; - vddp-ref-clk-always-on; }; &venus { From 56205c56ea2a050ee6a237ba686cea0b38860c84 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:15 +0530 Subject: [PATCH 262/791] arm64: dts: qcom: sc7280: Fix qmp phy node (use phy@ instead of lanes@) Fix the 'make dtbs_check' warning: arch/arm64/boot/dts/qcom/sc7280-idp.dt.yaml: phy@1c0e000: 'lanes@1c0e200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0cb126a7a8d0..ebbf4a41a63d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1949,7 +1949,7 @@ status = "disabled"; - pcie1_lane: lanes@1c0e200 { + pcie1_lane: phy@1c0e200 { reg = <0 0x01c0e200 0 0x170>, <0 0x01c0e400 0 0x200>, <0 0x01c0ea00 0 0x1f0>, From c769a3521dd5b8605b35ed246b7a0cb4567cdec4 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:16 +0530 Subject: [PATCH 263/791] arm64: dts: qcom: sm8450: Fix qmp ufs phy node (use phy@ instead of lanes@) Fix the 'make dtbs_check' warning: arch/arm64/boot/dts/qcom/sm8450-qrd.dt.yaml: phy@1d87000: 'lanes@1d87400' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-6-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 385892330017..b576d34ca40e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1544,7 +1544,7 @@ reset-names = "ufsphy"; status = "disabled"; - ufs_mem_phy_lanes: lanes@1d87400 { + ufs_mem_phy_lanes: phy@1d87400 { reg = <0 0x01d87400 0 0x108>, <0 0x01d87600 0 0x1e0>, <0 0x01d87c00 0 0x1dc>, From 7011db96f69316e8055961b366ac92b6c28403dd Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:17 +0530 Subject: [PATCH 264/791] arm64: dts: qcom: ipq6018: Fix qmp usb3 phy node Fix the following 'make dtbs_check' warning(s) by using phy@ instead of lanes@ and by moving '#clock-cells' to sub-node: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: ssphy@78000: 'lane@78200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Shawn Guo [bjorn: s/clock-names/clock-cells/ per Shawn's feedback] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-7-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index bbe58b92079a..a4d363c187fc 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -693,7 +693,6 @@ reg = <0x0 0x78000 0x0 0x1C4>; #address-cells = <2>; #size-cells = <2>; - #clock-cells = <1>; ranges; clocks = <&gcc GCC_USB0_AUX_CLK>, @@ -705,12 +704,13 @@ reset-names = "phy","common"; status = "disabled"; - usb0_ssphy: lane@78200 { + usb0_ssphy: phy@78200 { reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ <0x0 0x00078400 0x0 0x200>, /* Rx */ <0x0 0x00078800 0x0 0x1F8>, /* PCS */ <0x0 0x00078600 0x0 0x044>; /* PCS misc */ #phy-cells = <0>; + #clock-cells = <1>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb0_pipe_clk_src"; From 5a026558d2a994a5e58ca6fcab34008b95fea7e1 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 11 Apr 2022 14:13:39 -0700 Subject: [PATCH 265/791] arm64: dts: qcom: sc7280-herobrine: Audio codec wants 1.8V, not 1.62V The L2C rail on herobrine boards is intended to go to the audio codec. Let's override the 1.62V specified in the qcard.dtsi file to be 1.8V. Signed-off-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411141332.v2.1.I9f06fec63b978699fe62591fec9e5ac31bb3a69d@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 10de5e104b4f..d58045dd7334 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -308,7 +308,10 @@ }; /* - * BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD + * ADJUSTMENTS TO QCARD REGULATORS + * + * Mostly this is just board-local names for regulators that come from + * Qcard, but this also has some minor regulator overrides. * * Names are only listed here if regulators go somewhere other than a * testpoint. @@ -352,6 +355,16 @@ vreg_edp_bl: &ppvar_sys {}; ts_avdd: &pp3300_left_in_mlb {}; vreg_edp_3p3: &pp3300_left_in_mlb {}; +/* Regulator overrides from Qcard */ + +/* + * Herobrine boards only use l2c to power an external audio codec (like + * alc5682) and we want that to be at 1.8V, not at some slightly lower voltage. + */ +&vreg_l2c_1p8 { + regulator-min-microvolt = <1800000>; +}; + /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ ap_sar_sensor_i2c: &i2c1 { From 959cb513074386954629cbdc914612d6ff755b8c Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Tue, 12 Apr 2022 16:02:08 +0530 Subject: [PATCH 266/791] arm64: dts: qcom: sc7280: Add reset entries for SDCC controllers Add gcc hardware reset entries for eMMC and SD card. Signed-off-by: Shaik Sajida Bhanu Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649759528-15125-3-git-send-email-quic_c_sbhanu@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ebbf4a41a63d..ce766a86e146 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -886,6 +886,8 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + resets = <&gcc GCC_SDCC1_BCR>; + sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2732,6 +2734,8 @@ qcom,dll-config = <0x0007642c>; + resets = <&gcc GCC_SDCC2_BCR>; + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; From 551b614e235389063341b47f3b5bade763353589 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 22 Feb 2022 02:48:05 +0100 Subject: [PATCH 267/791] arm64: dts: qcom: sm8250-edo: Add dual CS35L41 amps Add nodes for dual Cirrus Logic CS35L41 audio amps connected via I2C. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220222014806.22446-1-konrad.dybcio@somainline.org --- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 30 ++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index d63f7a9bc4e9..e819b5b77363 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -441,7 +441,35 @@ status = "okay"; clock-frequency = <1000000>; - /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */ + cs35l41_l: cs35l41@40 { + compatible = "cirrus,cs35l41"; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; + + cs35l41_r: cs35l41@41 { + compatible = "cirrus,cs35l41"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; }; &i2c5 { From fbf64afd16b9581ae5a89c6924b50f83041463e0 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 10 Apr 2022 23:20:52 +0530 Subject: [PATCH 268/791] ARM: dts: qcom: mdm9615: User generic node name for DMA Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410175056.79330-3-singh.kuldeep87k@gmail.com --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 4d4f37cebf21..8f0752ce1c7b 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -330,7 +330,7 @@ }; }; - sdcc1bam: dma@12182000{ + sdcc1bam: dma-controller@12182000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = ; @@ -340,7 +340,7 @@ qcom,ee = <0>; }; - sdcc2bam: dma@12142000{ + sdcc2bam: dma-controller@12142000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12142000 0x8000>; interrupts = ; From fb1bdb7e787a6037f501869b5aaf9e5cabe7a7bc Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 10 Apr 2022 23:20:51 +0530 Subject: [PATCH 269/791] ARM: dts: qcom: apq8064: User generic node name for DMA Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410175056.79330-2-singh.kuldeep87k@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 4cdb1f7eae1e..91e5a40de6f8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1040,7 +1040,7 @@ }; /* Temporary fixed regulator */ - sdcc1bam:dma@12402000{ + sdcc1bam: dma-controller@12402000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -1050,7 +1050,7 @@ qcom,ee = <0>; }; - sdcc3bam:dma@12182000{ + sdcc3bam: dma-controller@12182000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; @@ -1060,7 +1060,7 @@ qcom,ee = <0>; }; - sdcc4bam:dma@121c2000{ + sdcc4bam: dma-controller@121c2000{ compatible = "qcom,bam-v1.3.0"; reg = <0x121c2000 0x8000>; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; From d317344d6e5ecc8cfa90463e801f9ec60bb4ef50 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 10 Apr 2022 21:51:12 +0200 Subject: [PATCH 270/791] arm64: dts: qcom: msm8916-huawei-g7: Clarify installation instructions The comment with installation instructions in the huawei-g7 device tree is a bit misleading and does not describe the recommended installation steps very well. The bootloader is actually not patched; to avoid all trouble with the vendor bootloader it is easier to bypass it completely by jumping to a custom bootloader (e.g. based on the open-source LK released by Qualcomm). To avoid confusion, simplify the comment to state only the problem and then refer to the wiki article which contains detailed suggested installation instructions. This will also make it easier to keep it up to date with new developments in the future. Fixes: 55056b229189 ("arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7") Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410195113.13646-2-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 42d93d3fba36..8ad9eb436a0c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -11,15 +11,10 @@ /* * Note: The original firmware from Huawei can only boot 32-bit kernels. - * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware - * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei - * forgot to set up (firmware) secure boot for some reason. - * - * Also note that Huawei no longer provides bootloader unlock codes. - * This can be bypassed by patching the bootloader from a custom HYP firmware, - * making it think the bootloader is unlocked. - * - * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7) + * To boot this device tree using arm64 it is necessary to flash 64-bit TZ/HYP + * firmware (e.g. taken from the DragonBoard 410c). + * See https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7) + * for suggested installation instructions. */ / { From 372c1c3dd709700bdec6c0d377363783fc7c1618 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 10 Apr 2022 21:51:13 +0200 Subject: [PATCH 271/791] arm64: dts: qcom: msm8916-huawei-g7: Add sound card The huawei-g7 uses the msm8916-wcd-digital/analog audio codecs similar to apq8016-sbc, so we can mostly copy paste it from there to make audio work correctly. The main difference is the hphl-jack-type-normally-open property, which is needed to avoid inverted audio jack detection. Note that at least on my device the jack detection is not fully reliable: sometimes headphones are detected as headsets (with microphone). However, this is not a big problem for typical usage. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410195113.13646-3-stephan@gerhold.net --- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 8ad9eb436a0c..00488afb413d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -8,6 +8,7 @@ #include #include #include +#include /* * Note: The original firmware from Huawei can only boot 32-bit kernels. @@ -211,6 +212,10 @@ status = "okay"; }; +&lpass { + status = "okay"; +}; + &pm8916_resin { status = "okay"; linux,code = ; @@ -255,6 +260,40 @@ cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>; }; +&sound { + status = "okay"; + + model = "msm8916"; + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS External2", + "AMIC3", "MIC BIAS External1"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cdc_pdm_lines_act>; + pinctrl-1 = <&cdc_pdm_lines_sus>; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; +}; + &usb { status = "okay"; extcon = <&usb_id>, <&usb_id>; @@ -264,6 +303,13 @@ extcon = <&usb_id>; }; +&wcd_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,hphl-jack-type-normally-open; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; From 095a7137ba3630bcca11e6017bfd4ab48b7fc12e Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 10 Apr 2022 23:20:53 +0530 Subject: [PATCH 272/791] arm64: dts: qcom: msm8996: User generic node name for DMA Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410175056.79330-4-singh.kuldeep87k@gmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1a1539399a87..b7eaab8b325a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -713,7 +713,7 @@ #thermal-sensor-cells = <1>; }; - cryptobam: dma@644000 { + cryptobam: dma-controller@644000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00644000 0x24000>; interrupts = ; From a86efc02b34104b93a0f9707d1e61577671fc4ad Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 10 Apr 2022 23:20:54 +0530 Subject: [PATCH 273/791] ARM: dts: qcom: ipq4019: User generic node name for DMA Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410175056.79330-5-singh.kuldeep87k@gmail.com --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 2 +- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++--- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 0c10d9e096db..03bb9e1768c4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -64,7 +64,7 @@ }; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { status = "okay"; }; @@ -89,7 +89,7 @@ status = "okay"; }; - cryptobam: dma@8e04000 { + cryptobam: dma-controller@8e04000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts index a7b1201dd614..79b0c6318e52 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts @@ -8,7 +8,7 @@ compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019"; soc { - dma@7984000 { + dma-controller@7984000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index 2fba904491d9..faeaa6bf0def 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -79,7 +79,7 @@ status = "okay"; }; - dma@7884000 { + dma-controller@7884000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi index 94872518b5a2..0107f552f520 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi @@ -52,7 +52,7 @@ status = "okay"; }; - dma@7884000 { + dma-controller@7884000 { status = "okay"; }; @@ -62,7 +62,7 @@ status = "okay"; }; - dma@7984000 { + dma-controller@7984000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 897442157f5f..9d5e934f2272 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -233,7 +233,7 @@ status = "disabled"; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x23000>; interrupts = ; @@ -300,7 +300,7 @@ status = "disabled"; }; - cryptobam: dma@8e04000 { + cryptobam: dma-controller@8e04000 { compatible = "qcom,bam-v1.7.0"; reg = <0x08e04000 0x20000>; interrupts = ; @@ -471,7 +471,7 @@ status = "disabled"; }; - qpic_bam: dma@7984000 { + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x7984000 0x1a000>; interrupts = ; From 7224013d4b5a64c43be23204bcfb4070dbd7fd76 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 10 Apr 2022 23:20:55 +0530 Subject: [PATCH 274/791] ARM: dts: qcom: ipq8064: User generic node name for DMA Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410175056.79330-6-singh.kuldeep87k@gmail.com --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..8366310ca5e3 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1155,7 +1155,7 @@ regulator-always-on; }; - sdcc1bam: dma@12402000 { + sdcc1bam: dma-controller@12402000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; interrupts = ; @@ -1165,7 +1165,7 @@ qcom,ee = <0>; }; - sdcc3bam: dma@12182000 { + sdcc3bam: dma-controller@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = ; From 4185b27b3bef9ce724a3dafd8193c935e845fcdc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 23 Feb 2022 22:52:47 +0530 Subject: [PATCH 275/791] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for LPASS core clocks and audio clock IDs for LPASS client to request for the clocks. Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Taniya Das Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220223172248.18877-1-tdas@codeaurora.org --- .../clock/qcom,sc7280-lpasscorecc.yaml | 172 ++++++++++++++++++ .../clock/qcom,lpassaudiocc-sc7280.h | 43 +++++ .../clock/qcom,lpasscorecc-sc7280.h | 26 +++ 3 files changed, 241 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml new file mode 100644 index 000000000000..bad9135489de --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280 + +maintainers: + - Taniya Das + +description: | + Qualcomm LPASS core and audio clock control module which supports the + clocks and power domains on SC7280. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7280.h + - dt-bindings/clock/qcom,lpassaudiocc-sc7280.h + +properties: + clocks: true + + clock-names: true + + compatible: + enum: + - qcom,sc7280-lpassaoncc + - qcom,sc7280-lpassaudiocc + - qcom,sc7280-lpasscorecc + - qcom,sc7280-lpasshm + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,sc7280-lpassaudiocc + + then: + properties: + clocks: + items: + - description: Board XO source + - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC + + clock-names: + items: + - const: bi_tcxo + - const: lpass_aon_cc_main_rcg_clk_src + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-lpassaoncc + + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board XO active only source + - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: iface + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-lpasshm + - qcom,sc7280-lpasscorecc + + then: + properties: + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + +examples: + - | + #include + #include + #include + #include + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc7280-lpassaudiocc"; + reg = <0x3300000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include + #include + #include + #include + lpass_hm: clock-controller@3c00000 { + compatible = "qcom,sc7280-lpasshm"; + reg = <0x3c00000 0x28>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include + #include + #include + #include + lpasscore: clock-controller@3900000 { + compatible = "qcom,sc7280-lpasscorecc"; + reg = <0x3900000 0x50000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include + #include + #include + #include + lpass_aon: clock-controller@3380000 { + compatible = "qcom,sc7280-lpassaoncc"; + reg = <0x3380000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, + <&lpasscore LPASS_CORE_CC_CORE_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao","iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h new file mode 100644 index 000000000000..20ef2ea673f3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H + +/* LPASS_AUDIO_CC clocks */ +#define LPASS_AUDIO_CC_PLL 0 +#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1 +#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2 +#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3 +#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4 +#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5 +#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6 +#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7 +#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8 +#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9 +#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10 +#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11 +#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12 +#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13 +#define LPASS_AUDIO_CC_RX_MCLK_CLK 14 +#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15 + +/* LPASS_AON_CC clocks */ +#define LPASS_AON_CC_PLL 0 +#define LPASS_AON_CC_PLL_OUT_EVEN 1 +#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2 +#define LPASS_AON_CC_PLL_OUT_ODD 3 +#define LPASS_AON_CC_AUDIO_HM_H_CLK 4 +#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5 +#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6 +#define LPASS_AON_CC_TX_MCLK_2X_CLK 7 +#define LPASS_AON_CC_TX_MCLK_CLK 8 +#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9 +#define LPASS_AON_CC_VA_MEM0_CLK 10 + +/* LPASS_AON_CC power domains */ +#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h new file mode 100644 index 000000000000..28ed2a07aacc --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_CORE_CC_DIG_PLL 0 +#define LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC 1 +#define LPASS_CORE_CC_DIG_PLL_OUT_ODD 2 +#define LPASS_CORE_CC_CORE_CLK 3 +#define LPASS_CORE_CC_CORE_CLK_SRC 4 +#define LPASS_CORE_CC_EXT_IF0_CLK_SRC 5 +#define LPASS_CORE_CC_EXT_IF0_IBIT_CLK 6 +#define LPASS_CORE_CC_EXT_IF1_CLK_SRC 7 +#define LPASS_CORE_CC_EXT_IF1_IBIT_CLK 8 +#define LPASS_CORE_CC_LPM_CORE_CLK 9 +#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10 +#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11 + +/* LPASS_CORE_CC power domains */ +#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0 + +#endif From 9499240d15f29760d2271371eea963ca6f761463 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 2 Feb 2022 11:02:07 +0530 Subject: [PATCH 276/791] arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers Add the low pass audio clock controller device nodes. Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202053207.14256-1-tdas@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ce766a86e146..e6571de5d293 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -2028,6 +2030,47 @@ #clock-cells = <1>; }; + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc7280-lpassaudiocc"; + reg = <0 0x03300000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_aon: clock-controller@3380000 { + compatible = "qcom,sc7280-lpassaoncc"; + reg = <0 0x03380000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&lpasscore LPASS_CORE_CC_CORE_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpasscore: clock-controller@3900000 { + compatible = "qcom,sc7280-lpasscorecc"; + reg = <0 0x03900000 0 0x50000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_hm: clock-controller@3c00000 { + compatible = "qcom,sc7280-lpasshm"; + reg = <0 0x3c00000 0 0x28>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + lpass_ag_noc: interconnect@3c40000 { reg = <0 0x03c40000 0 0xf080>; compatible = "qcom,sc7280-lpass-ag-noc"; From c20aa951ee14fe0dfa2beed19aaee1fd33d50a6e Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Wed, 9 Feb 2022 16:38:40 +0000 Subject: [PATCH 277/791] ARM: dts: qcom: pm8226: Add VADC node Add a node for the voltage ADC (VADC) found in PM8226. Signed-off-by: Rayyan Ansari Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220209163841.7360-1-rayyan@ansari.sh --- arch/arm/boot/dts/qcom-pm8226.dtsi | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi index bd23e4f9be02..9b7d9d04ded6 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause #include #include +#include &spmi_bus { pm8226_0: pm8226@0 { @@ -47,6 +48,39 @@ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; + pm8226_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@7 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + adc-chan@8 { + reg = ; + label = "die_temp"; + }; + adc-chan@9 { + reg = ; + label = "ref_625mv"; + }; + adc-chan@a { + reg = ; + label = "ref_1250mv"; + }; + adc-chan@e { + reg = ; + }; + adc-chan@f { + reg = ; + }; + }; + pm8226_mpps: mpps@a000 { compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; reg = <0xa000>; From 02c5553523c6cfdab4335ab26ff65f679c7c91ac Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 22 Feb 2022 10:26:23 +0530 Subject: [PATCH 278/791] ARM: dts: qcom: sdx65: Add support for A7 PLL clock On SDX65 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 796641d30e06..6b3a502c0ce2 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -121,6 +121,14 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; From ce91bc005e076acd3415d557d7e7c488aa9ab10d Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 22 Feb 2022 10:26:24 +0530 Subject: [PATCH 279/791] ARM: dts: qcom: sdx65: Add support for APCS block The APCS block on SDX65 acts as a mailbox controller and also provides clock output for the Cortex A7 CPU. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 6b3a502c0ce2..14579121be5a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -129,6 +129,15 @@ #clock-cells = <0>; }; + apcs: mailbox@17810000 { + compatible = "qcom,sdx55-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; From d41a72c24ce3fdbbc75d13e90700d6878cbad49c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:54 +0300 Subject: [PATCH 280/791] arm64: dts: qcom: sm8450: add PCIe0 PHY node Add device tree node for the first PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b576d34ca40e..cd881156a666 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -683,8 +683,12 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie0_lane>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "sleep_clk"; }; qupv3_id_0: geniqup@9c0000 { @@ -750,6 +754,40 @@ }; }; + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0 0x1c06e00 0 0x200>, /* tx */ + <0 0x1c07000 0 0x200>, /* rx */ + <0 0x1c06200 0 0x200>, /* pcs */ + <0 0x1c06600 0 0x200>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; From 7b09b1b47335b7a6d869df6b77a55cdc2b75e14e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:55 +0300 Subject: [PATCH 281/791] arm64: dts: qcom: sm8450: add PCIe0 RC device Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 98 ++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index cd881156a666..d79ad52f4338 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,6 +754,81 @@ }; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8450-pcie0"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "disabled"; + }; + pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x200>; @@ -1208,6 +1283,29 @@ gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + pcie0_default_state: pcie0-default-state { + perst { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; From 334d91d2410d76b9045d3821bc02ae92a9e0b23b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:56 +0300 Subject: [PATCH 282/791] arm64: dts: qcom: sm8450: add PCIe1 PHY node Add device tree node for the second PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d79ad52f4338..4a40045fa480 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -685,9 +685,11 @@ #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie0_lane>, + <&pcie1_lane>, <&sleep_clk>; clock-names = "bi_tcxo", "pcie_0_pipe_clk", + "pcie_1_pipe_clk", "sleep_clk"; }; @@ -863,6 +865,42 @@ }; }; + pcie1_phy: phy@1c0f000 { + compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; + reg = <0 0x01c0f000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c0e000 { + reg = <0 0x1c0e000 0 0x200>, /* tx */ + <0 0x1c0e200 0 0x300>, /* rx */ + <0 0x1c0f200 0 0x200>, /* pcs */ + <0 0x1c0e800 0 0x200>, /* tx */ + <0 0x1c0ea00 0 0x300>, /* rx */ + <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; From bc6588bc25fb30b25125660d39222d3ca4a44eb6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:57 +0300 Subject: [PATCH 283/791] arm64: dts: qcom: sm8450: add PCIe1 root device Add device tree node for the second PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 96 ++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4a40045fa480..2cfc67b75259 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -865,6 +865,79 @@ }; }; + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8450-pcie1"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre1"; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + pcie1_phy: phy@1c0f000 { compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; reg = <0 0x01c0f000 0 0x200>; @@ -1344,6 +1417,29 @@ }; }; + pcie1_default_state: pcie1-default-state { + perst { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio98"; + function = "pcie1_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; From 3795221250b60b1a3a9f60a22fd447f2f9e17b57 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:58 +0300 Subject: [PATCH 284/791] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Enable PCIe0 PHY on the SM8450 QRD device. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 9526632d4029..7b6324969a4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -342,6 +342,12 @@ }; }; +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; From bce9887e0f4e4ef4ffc5a5af4d7b6769fa18c949 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:59 +0300 Subject: [PATCH 285/791] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Enable PCIe0 host on SM8450 QRD device. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-7-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 7b6324969a4e..d33e86a375c0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -342,6 +342,10 @@ }; }; +&pcie0 { + status = "okay"; +}; + &pcie0_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; From 37ebe34fc04e62a019006912d49e0b5fb0731986 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:15:00 +0300 Subject: [PATCH 286/791] arm64: dts: qcom: sm8450-hdk: add pcie nodes Add device tree nodes for PCIe0/PCIe1 controllers and corresponding PHYs. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-8-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 34e37991c0c9..4e51a9d6af98 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -349,6 +349,27 @@ }; }; +&pcie0 { + status = "okay"; + max-link-speed = <2>; +}; + +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l2h_0p91>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; From 7b36ab2673b359d1daf4da9e42597edc5ef866fa Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:06 +0300 Subject: [PATCH 287/791] arm64: dts: qcom: msm8996: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: 12d540375736 ("arm64: dts: qcom: msm8996: Add DSI0 nodes") Fixes: 3a4547c1fc2f ("arm64: qcom: msm8996.dtsi: Add Display nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b7eaab8b325a..67d2253e2c35 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -794,7 +794,7 @@ reg-names = "mdp_phys"; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, @@ -840,7 +840,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE0_CLK>, @@ -910,7 +910,7 @@ "hdcp_physical"; interrupt-parent = <&mdss>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <8>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, From 2a11b3bfc51ac4d5dcb17a22dd98741f26350e5f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:07 +0300 Subject: [PATCH 288/791] arm64: dts: qcom: sdm630: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: b52555d590d1 ("arm64: dts: qcom: sdm630: Add MDSS nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 240293592ef9..7f875bf9390a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1453,7 +1453,7 @@ reg-names = "mdp_phys"; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; assigned-clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_VSYNC_CLK>; @@ -1530,7 +1530,7 @@ power-domains = <&rpmpd SDM660_VDDCX>; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; From 63ddd8a54d4be02976e63ff06bb1cc98226c6981 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:08 +0300 Subject: [PATCH 289/791] arm64: dts: qcom: sdm660: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: ab290284398d ("arm64: dts: qcom: sdm660: Add required nodes for DSI1") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index eccf6fde16b4..1d748c5305f4 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -163,7 +163,7 @@ power-domains = <&rpmpd SDM660_VDDCX>; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; From 0316da6bbcb7d78017f8f177399bff5ff889456a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:09 +0300 Subject: [PATCH 290/791] arm64: dts: qcom: sdm845: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index a49376d8ecbf..692cf4be4eef 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4283,7 +4283,7 @@ power-domains = <&rpmhpd SDM845_CX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; ports { #address-cells = <1>; @@ -4335,7 +4335,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -4407,7 +4407,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, From be633329928a3b33d91b3cd2b41e9b7f522d1416 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:10 +0300 Subject: [PATCH 291/791] arm64: dts: qcom: sm8250: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index af8f22636436..33ea5ed4c0f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3202,7 +3202,7 @@ power-domains = <&rpmhpd SM8250_MMCX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; ports { #address-cells = <1>; @@ -3254,7 +3254,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -3327,7 +3327,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, From 6ffe07ba141b483c432458e881ca39f80f582470 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:11 +0300 Subject: [PATCH 292/791] ARM: dts: qcom: msm8974: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Fixes: 5a9fc531f6ec ("ARM: dts: msm8974: add display support") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-6-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index a249b05af9b1..4a1f3768d75c 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1495,7 +1495,7 @@ reg-names = "mdp_phys"; interrupt-parent = <&mdss>; - interrupts = <0 0>; + interrupts = <0>; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, @@ -1530,7 +1530,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; From f607dd767f5d6800ffbdce5b99ba81763b023781 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 11 Feb 2022 17:44:15 +0530 Subject: [PATCH 293/791] arm64: dts: qcom: ipq8074: fix the sleep clock frequency Sleep clock frequency should be 32768Hz. Lets fix it. Cc: stable@vger.kernel.org Fixes: 41dac73e243d ("arm64: dts: Add ipq8074 SoC and HK01 board support") Link: https://lore.kernel.org/all/e2a447f8-6024-0369-f698-2027b6edcf9e@codeaurora.org/ Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1644581655-11568-1-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 8e41c910b8f9..943243d5515b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -13,7 +13,7 @@ clocks { sleep_clk: sleep_clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32768>; #clock-cells = <0>; }; From b736cedce53390705887d5188678b0f25a9b9c23 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 26 Feb 2022 11:19:38 +0100 Subject: [PATCH 294/791] dt-bindings: arm: qcom: Document asus,sparrow device Document the ASUS ZenWatch 2 ("sparrow") which is a smartwatch based on Snapdragon 400 SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226101939.1011551-1-luca@z3ntu.xyz --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 129cdd246223..7f89ab344d3f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -99,6 +99,7 @@ properties: - items: - enum: + - asus,sparrow - lg,lenok - const: qcom,apq8026 From d3236c598e08ba1ca5106211a8fb5cb1573571c8 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 26 Feb 2022 11:19:39 +0100 Subject: [PATCH 295/791] ARM: dts: qcom: Add support for ASUS ZenWatch 2 Add support for this smartwatch, based on Snapdragon 400 SoC. Currently supported functionality: * Internal storage * USB * Charger * Power button * Vibration motor * Bluetooth * Wifi Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226101939.1011551-2-luca@z3ntu.xyz --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/qcom-apq8026-asus-sparrow.dts | 294 ++++++++++++++++++ arch/arm/boot/dts/qcom-msm8226.dtsi | 9 + 3 files changed, 304 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..093e90b80adb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -977,6 +977,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8016-sbc.dtb \ + qcom-apq8026-asus-sparrow.dtb \ qcom-apq8026-lg-lenok.dtb \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts new file mode 100644 index 000000000000..ace8cea27949 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Luca Weiss + */ + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "qcom-pm8226.dtsi" + +/ { + model = "ASUS ZenWatch 2"; + compatible = "asus,sparrow", "qcom,apq8026"; + chassis-type = "watch"; + qcom,msm-id = <199 0x20000>; + qcom,board-id = <8 3005>; + + reserved-memory { + sbl_region: sbl@2f00000 { + reg = <0x02f00000 0x100000>; + no-map; + }; + external_image_region: external-image@3100000 { + reg = <0x3100000 0x200000>; + no-map; + }; + peripheral_region: peripheral@3300000 { + reg = <0x3300000 0x600000>; + no-map; + }; + adsp_region: adsp@3900000 { + reg = <0x3900000 0x1400000>; + no-map; + }; + modem_region: modem@4d00000 { + reg = <0x4d00000 0x1b00000>; + no-map; + }; + modem_efs_region: modem-efs@7f00000 { + reg = <0x7f00000 0x100000>; + no-map; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_default_state>; + }; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart1_default_state>; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_state>; + + host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + }; +}; + +&pm8226_vib { + status = "okay"; +}; + +&rpm_requests { + pm8226-regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l7: l7 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + }; + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + pm8226_l15: l15 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; +}; + +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + non-removable; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8226_l6>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_hostwake_default_state>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <350000>; + qcom,fast-charge-safe-voltage = <4430000>; + qcom,fast-charge-high-threshold-voltage = <4400000>; + qcom,auto-recharge-threshold-voltage = <4300000>; + qcom,minimum-input-voltage = <4400000>; +}; + +&tlmm { + blsp1_uart1_default_state: blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <8>; + bias-disable; + }; + + bluetooth_default_state: bluetooth-default-state { + pins = "gpio48", "gpio61"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + + wlan_hostwake_default_state: wlan-hostwake-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + wlan_regulator_default_state: wlan-regulator-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb { + status = "okay"; + extcon = <&smbb>; + dr_mode = "peripheral"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 85e56992d2d0..28eca15b5712 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -182,6 +182,15 @@ status = "disabled"; }; + blsp1_uart1: serial@f991d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991d000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_uart3: serial@f991f000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991f000 0x1000>; From a5ba119455c77a07e05f2fe0af446c8bf43d1a00 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:35 +0100 Subject: [PATCH 296/791] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064 Add syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock now requires them for the ipq8064 gcc driver that has now been modernized. Signed-off-by: Ansuel Smith Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-16-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 8366310ca5e3..5b0ce39d2d18 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -298,13 +298,13 @@ }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -736,7 +736,9 @@ }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; From 3bfef00d767124838b4b285de8da66fdf395da0d Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Sat, 26 Feb 2022 00:51:32 +0530 Subject: [PATCH 297/791] arm64: dts: qcom: sc7280: Support gpu speedbin Add speedbin fuse and additional OPPs for gpu to support sc7280 SKUs. Signed-off-by: Akhil P Oommen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226005021.v2.5.I4c2cb95f06f0c37038c80cc1ad20563fdf0618e2@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e6571de5d293..9ece35736515 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -849,6 +849,11 @@ power-domains = <&rpmhpd SC7280_MX>; #address-cells = <1>; #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@1e9 { + reg = <0x1e9 0x2>; + bits = <5 8>; + }; }; sdhc_1: sdhci@7c4000 { @@ -2094,6 +2099,9 @@ interconnect-names = "gfx-mem"; #cooling-cells = <2>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2101,18 +2109,56 @@ opp-hz = /bits/ 64 <315000000>; opp-level = ; opp-peak-kBps = <1804000>; + opp-supported-hw = <0x03>; }; opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-level = ; opp-peak-kBps = <4068000>; + opp-supported-hw = <0x03>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <6832000>; + opp-supported-hw = <0x03>; + }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + opp-level = ; + opp-peak-kBps = <8368000>; + opp-supported-hw = <0x02>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; + }; + + opp-812000000 { + opp-hz = /bits/ 64 <812000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; + }; + + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; }; }; }; From 324db76df18f980a928b8d37c8a6426c09ab52e4 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:47:22 +0530 Subject: [PATCH 298/791] ARM: dts: qcom: sdx65: Add spmi node Add SPMI node to SDX65 dtsi. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647411447-25249-2-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 14579121be5a..ba7b6c5c1562 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -91,6 +91,25 @@ status = "disabled"; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sdx65-tlmm"; reg = <0xf100000 0x300000>; From 26380f298b2b06b9e22155649b822d1e2038e754 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:47:23 +0530 Subject: [PATCH 299/791] ARM: dts: qcom: sdx65-mtp: Add pmk8350b and pm8150b pmic SDX65-mtp features PMK8350b and PM8150B pmic, so include the dts as well Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647411447-25249-3-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 59457da8e5f1..9fa251aaaa45 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -5,6 +5,8 @@ /dts-v1/; #include "qcom-sdx65.dtsi" +#include +#include / { model = "Qualcomm Technologies, Inc. SDX65 MTP"; From 5827e28304673444f8e1cf426c2b08cc16382290 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:31 +0100 Subject: [PATCH 300/791] arm64: dts: qcom: msm8994: Fix sleep clock name The sleep clock name expected by GCC is actually "sleep" and not "sleep_clk". Fix the clock-names value for it to make sure it is provided. Fixes: 9204da57cd65 ("arm64: dts: qcom: msm8994: Provide missing "xo_board" and "sleep_clk" to GCC") Signed-off-by: Konrad Dybcio Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-2-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 209f9ef030e5..499f169ae773 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -714,7 +714,7 @@ #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; - clock-names = "xo", "sleep_clk"; + clock-names = "xo", "sleep"; clocks = <&xo_board>, <&sleep_clk>; }; From 13cff03303676148bc8f0bbe73a6d40d5fdd020e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:32 +0100 Subject: [PATCH 301/791] arm64: dts: qcom: msm8992-libra: Add CPU regulators Specify CPU regulator voltages for both VDD_APC rails. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-3-konrad.dybcio@somainline.org --- .../boot/dts/qcom/msm8992-xiaomi-libra.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 84558ab5fe86..6371719aacc5 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -126,6 +126,23 @@ no-map; }; +&pm8994_spmi_regulators { + VDD_APC0: s8 { + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1180000>; + regulator-always-on; + regulator-boot-on; + }; + + /* APC1 is 3-phase, but quoting downstream, s11 is "the gang leader" */ + VDD_APC1: s11 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; +}; + &rpm_requests { pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; From ed288ae94af0875fba3934893ae3490387d4adc1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:33 +0100 Subject: [PATCH 302/791] arm64: dts: qcom: msm8992-libra: Temporarily restrict CPU count to 1 The phone seems to randomly crash when more than 1 CPU is enabled, which is probably related to lack of some driver. Restrict the device to only use a single core until this is solved. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-4-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 6371719aacc5..7a6ed8b017d1 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -23,7 +23,7 @@ /* This enables graphical output via bootloader-enabled display */ chosen { - bootargs = "earlycon=tty0 console=tty0"; + bootargs = "earlycon=tty0 console=tty0 maxcpus=1"; #address-cells = <2>; #size-cells = <2>; From 2d0f45f760fe8ff5c9b7b58640bd4d665aac80f7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:34 +0100 Subject: [PATCH 303/791] arm64: dts: qcom: msm8992-libra: Remove superfluous status = "okay" The framebuffer is already enabled by default. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-5-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 7a6ed8b017d1..e638fc489539 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -30,7 +30,6 @@ ranges; framebuffer0: framebuffer@3404000 { - status= "okay"; compatible = "simple-framebuffer"; reg = <0 0x3404000 0 (1080 * 1920 * 3)>; width = <1080>; From e9b0eb542027195382c27158ffc83ef77cfb5ba6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:35 +0100 Subject: [PATCH 304/791] arm64: dts: qcom: msm8994: Add MMCC node Describe the Multimedia Clock Controller block in the DT. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-6-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 499f169ae773..096bde7bb4f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -4,6 +4,8 @@ #include #include +#include +#include #include / { @@ -1012,6 +1014,44 @@ drive-strength = <2>; }; }; + + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8994"; + reg = <0xfd8c0000 0x5200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clock-names = "xo", + "gpll0", + "mmssnoc_ahb", + "oxili_gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll"; + clocks = <&xo_board>, + <&gcc GPLL0_OUT_MMSSCC>, + <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>; + + assigned-clocks = <&mmcc MMPLL0_PLL>, + <&mmcc MMPLL1_PLL>, + <&mmcc MMPLL3_PLL>, + <&mmcc MMPLL4_PLL>, + <&mmcc MMPLL5_PLL>; + assigned-clock-rates = <800000000>, + <1167000000>, + <1020000000>, + <960000000>, + <600000000>; + }; }; timer: timer { From 355ea704c887303aa1a4b3c8e228cb7ccc2d54c0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:36 +0100 Subject: [PATCH 305/791] arm64: dts: qcom: msm8992: Use the correct GCC compatible Now that proper msm8992 support is in the driver, switch to the new compatible. Signed-off-by: Konrad Dybcio Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-7-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 58fe58cc7703..1b175b7f1514 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -10,6 +10,10 @@ /delete-node/ &cpu6_map; /delete-node/ &cpu7_map; +&gcc { + compatible = "qcom,gcc-msm8992"; +}; + &rpmcc { compatible = "qcom,rpmcc-msm8992"; }; From b0b5687a2ce5b27dc76acda2b48415c69b5a5a95 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:37 +0100 Subject: [PATCH 306/791] arm64: dts: qcom: msm8992: Use the correct MMCC compatible Now that proper msm8992 support is in the driver, switch to the new compatible. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-8-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 1b175b7f1514..1de1d9c4643d 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -14,6 +14,16 @@ compatible = "qcom,gcc-msm8992"; }; +&mmcc { + compatible = "qcom,mmcc-msm8992"; + + assigned-clock-rates = <800000000>, + <808000000>, + <1020000000>, + <960000000>, + <800000000>; +}; + &rpmcc { compatible = "qcom,rpmcc-msm8992"; }; From 049c46f31a726bf8d202ff1681661513447fac84 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:38 +0100 Subject: [PATCH 307/791] arm64: dts: qcom: msm8994: Fix the cont_splash_mem address The default memory map places cont_splash_mem at 3401000, which was overlooked.. Fix it! Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-9-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 096bde7bb4f1..18cf05535229 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -185,8 +185,8 @@ no-map; }; - cont_splash_mem: memory@3800000 { - reg = <0 0x03800000 0 0x2400000>; + cont_splash_mem: memory@3401000 { + reg = <0 0x03401000 0 0x2200000>; no-map; }; From 9e398b4c4ed8f926fcbd9d7d8013d6620d9833ea Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:39 +0100 Subject: [PATCH 308/791] arm64: dts: qcom: msm8992-libra: Fix up the framebuffer Make sure the necessary clocks are kept on after clk_cleanup (until MDSS is properly handled by its own driver) and touch up the fb address to prevent some weird shifting. It's still not perfect, but at least the kernel log doesn't start a third deep into your screen.. Signed-off-by: Konrad Dybcio [bjorn: Folded in change of framebuffer base address, from Konrad] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-10-konrad.dybcio@somainline.org --- .../arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index e638fc489539..7748b745a5df 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -29,13 +29,25 @@ #size-cells = <2>; ranges; - framebuffer0: framebuffer@3404000 { + framebuffer0: framebuffer@3400000 { compatible = "simple-framebuffer"; - reg = <0 0x3404000 0 (1080 * 1920 * 3)>; + reg = <0 0x3400000 0 (1080 * 1920 * 3)>; width = <1080>; height = <1920>; stride = <(1080 * 3)>; format = "r8g8b8"; + /* + * That's a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet.. + */ + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + power-domains = <&mmcc MDSS_GDSC>; }; }; From 7d9379bf1ecfbf0a7b30a773137006b04a713dd4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:40 +0100 Subject: [PATCH 309/791] arm64: dts: qcom: msm8994-kitakami: Disable a mistakengly enabled I2C host I2C4 turns out not to be used on Kitakami after all and it only blocks a GPIO used by camera hardware. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-11-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index dde7ed159c4d..5e93ab0a649b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -108,13 +108,6 @@ /* NXP PN547 NFC */ }; -&blsp1_i2c4 { - status = "okay"; - clock-frequency = <355000>; - - /* Empty but active */ -}; - &blsp1_i2c6 { status = "okay"; clock-frequency = <355000>; From 410e1619d51720ee5efa7ef59e4784128ee9801a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:41 +0100 Subject: [PATCH 310/791] arm64: dts: qcom: msm8994-kitakami: Update regulator configuration Remove regulator-always-on property where not necessary and mark regulators that are not supposed to be voted active on boot with regulator-boot-on. While at it, reorder the load properties to make it look more decent. Reorder PMICs to fix a probe defer caused by messy dependencies and Linux's inability to handle them (at least for now). Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-12-konrad.dybcio@somainline.org --- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 82 ++++++++++--------- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 5e93ab0a649b..e5a45af0bd12 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -187,26 +187,38 @@ }; &rpm_requests { + /* PMI8994 should probe first, because pmi8994_bby supplies some of PM8994's regulators */ + pmi8994_regulators: pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + pmi8994_s1: s1 { + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + + /* S2 & S3 - VDD_GFX */ + + pmi8994_bby: boost-bypass { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3600000>; + }; + }; + pm8994_regulators: pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; vdd_s3-supply = <&vph_pwr>; vdd_s4-supply = <&vph_pwr>; vdd_s5-supply = <&vph_pwr>; vdd_s6-supply = <&vph_pwr>; vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; vdd_l1-supply = <&pmi8994_s1>; vdd_l2_l26_l28-supply = <&pm8994_s3>; vdd_l3_l11-supply = <&pm8994_s3>; vdd_l4_l27_l31-supply = <&pm8994_s3>; - vdd_l5_l7-supply = <&pm8994_s5>; vdd_l6_l12_l32-supply = <&pm8994_s5>; vdd_l8_l16_l30-supply = <&vph_pwr>; vdd_l9_l10_l18_l22-supply = <&pmi8994_bby>; @@ -227,9 +239,9 @@ pm8994_s4: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-system-load = <325000>; regulator-allow-set-load; regulator-always-on; - regulator-system-load = <325000>; }; pm8994_s5: s5 { @@ -255,13 +267,14 @@ pm8994_l2: l2 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <1250000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l3: l3 { regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; + regulator-boot-on; }; pm8994_l4: l4 { @@ -301,8 +314,8 @@ pm8994_l12: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l13: l13 { @@ -313,8 +326,9 @@ pm8994_l14: l14 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; + regulator-boot-on; }; pm8994_l15: l15 { @@ -330,44 +344,47 @@ pm8994_l17: l17 { regulator-min-microvolt = <2200000>; regulator-max-microvolt = <2200000>; + regulator-boot-on; }; pm8994_l18: l18 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; + regulator-boot-on; }; pm8994_l19: l19 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; + regulator-boot-on; }; pm8994_l20: l20 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; regulator-system-load = <570000>; + regulator-allow-set-load; }; pm8994_l21: l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-allow-set-load; regulator-system-load = <800000>; + regulator-allow-set-load; }; pm8994_l22: l22 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; + regulator-boot-on; }; pm8994_l23: l23 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; }; pm8994_l24: l24 { @@ -378,6 +395,7 @@ pm8994_l25: l25 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-boot-on; }; pm8994_l26: l26 { @@ -388,30 +406,33 @@ pm8994_l27: l27 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-boot-on; }; pm8994_l28: l28 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l29: l29 { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2700000>; + regulator-boot-on; }; pm8994_l30: l30 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; }; pm8994_l31: l31 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l32: l32 { @@ -419,26 +440,11 @@ regulator-max-microvolt = <1800000>; }; - pm8994_lvs1: lvs1 {}; - pm8994_lvs2: lvs2 {}; - }; - - pmi8994_regulators: pmi8994-regulators { - compatible = "qcom,rpm-pmi8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_bst_byp-supply = <&vph_pwr>; - - pmi8994_s1: s1 { - regulator-min-microvolt = <1025000>; - regulator-max-microvolt = <1025000>; + pm8994_lvs1: lvs1 { + regulator-boot-on; }; - - /* S2 & S3 - VDD_GFX */ - - pmi8994_bby: boost-bypass { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3600000>; + pm8994_lvs2: lvs2 { + regulator-boot-on; }; }; }; From 9d511d0a7926c86e259e5084ae1b25fd61a428f3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:42 +0100 Subject: [PATCH 311/791] arm64: dts: qcom: msm8994: Add OCMEM node Add OCMEM node to allow for GPU SRAM access. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-13-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/msm8994.dtsi | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 1de1d9c4643d..92c1f87d6bba 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -24,6 +24,14 @@ <800000000>; }; +&ocmem { + reg = <0xfdd00000 0x2000>, <0xfec00000 0x100000>; + + gmu-sram@0 { + reg = <0x0 0x80000>; + }; +}; + &rpmcc { compatible = "qcom,rpmcc-msm8992"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 18cf05535229..e4b212630509 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -1052,6 +1052,23 @@ <960000000>, <600000000>; }; + + ocmem: ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x200000>; + reg-names = "ctrl", "mem"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x180000>; + }; + }; }; timer: timer { From 1ae438d26b620979ed004d559c304d31c42173ae Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:43 +0100 Subject: [PATCH 312/791] arm64: dts: qcom: msm8994: Fix BLSP[12]_DMA channels count MSM8994 actually features 24 DMA channels for each BLSP, fix it! Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-14-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index e4b212630509..e9920b4c9399 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -500,7 +500,7 @@ #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; - num-channels = <18>; + num-channels = <24>; qcom,num-ees = <4>; }; @@ -636,7 +636,7 @@ #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; - num-channels = <18>; + num-channels = <24>; qcom,num-ees = <4>; }; From e0be93fb3818b1eb7fc04ebd6c03bb8ba2d67814 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:44 +0100 Subject: [PATCH 313/791] arm64: dts: qcom: msm8994: Add watchdog timer node Add and configure the watchdog node. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-15-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index e9920b4c9399..068dfe49ed82 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -356,6 +356,15 @@ #mbox-cells = <1>; }; + watchdog@f9017000 { + compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; + reg = <0xf9017000 0x1000>; + interrupts = , + ; + clocks = <&sleep_clk>; + timeout-sec = <10>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; From d8023f3a8e55907f5b463d571b9797feae59ead9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:45 +0100 Subject: [PATCH 314/791] arm64: dts: qcom: msm8994: Add mmc aliases Set the aliases for both SDHCI controllers. Signed-off-by: Konrad Dybcio Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-16-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 068dfe49ed82..e2a95d52d8f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -14,6 +14,11 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + mmc1 = &sdhc1; + mmc2 = &sdhc2; + }; + chosen { }; clocks { From 48cc9bb1d38d8bca1e1fcd98812c965ed13abc3e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Mar 2022 11:18:40 +0100 Subject: [PATCH 315/791] arm64: dts: qcom: sm6350: Add wifi node Add a node describing the wifi hardware found on sm6350. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325101841.172304-1-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index f6fb97d5ca92..6c6112427ef9 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1356,6 +1356,28 @@ }; }; + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_fw_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x20 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; label = "apps_rsc"; From 22437c436c3be0bb92cd44bd2aead00747394ce0 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Mar 2022 11:18:41 +0100 Subject: [PATCH 316/791] arm64: dts: qcom: sm7225-fairphone-fp4: Enable wifi Configure regulators used by the wifi hardware and enable it. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325101841.172304-2-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index f70174a342c6..61925216f5e3 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -406,3 +406,13 @@ vdda-phy-supply = <&vreg_l22a>; vdda-pll-supply = <&vreg_l16a>; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l4a>; + vdd-1.8-xo-supply = <&vreg_l7a>; + vdd-1.3-rfa-supply = <&vreg_l2e>; + vdd-3.3-ch0-supply = <&vreg_l10e>; + vdd-3.3-ch1-supply = <&vreg_l11e>; +}; From b3d26821d9394be7d17435168448db01bd8bc494 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:26 +0200 Subject: [PATCH 317/791] arm64: dts: qcom: msm8953: do not use underscore in node name Align RPM requests node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 2a70263a701d..006a561f5a9d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -321,7 +321,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests: rpm_requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8953"; qcom,smd-channels = "rpm_requests"; From 0e324e9f49220055a9a81b027443740d3fc5ca07 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:27 +0200 Subject: [PATCH 318/791] arm64: dts: qcom: msm8994: remove SMD qcom,local-pid property The Qualcomm SMD does not use qcom,local-pid property. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index e2a95d52d8f3..7317feb128fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -240,7 +240,6 @@ interrupts = ; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - qcom,local-pid = <0>; qcom,remote-pid = <6>; rpm_requests: rpm-requests { From 812b0b61ee6a281047f433b143b4e9127f1ad97c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:28 +0200 Subject: [PATCH 319/791] arm64: dts: qcom: add RPM clock controller fallback compatible The bindings require a fallback compatible to RPM clock controller. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8992.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0f72349d4067..05472510e29d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -299,7 +299,7 @@ qcom,smd-channels = "rpm_requests"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916"; + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 006a561f5a9d..49903a6e9dfd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -326,7 +326,7 @@ qcom,smd-channels = "rpm_requests"; rpmcc: rpmcc { - compatible = "qcom,rpmcc-msm8953"; + compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; clocks = <&xo_board>; clock-names = "xo"; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 92c1f87d6bba..750643763a76 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -33,7 +33,7 @@ }; &rpmcc { - compatible = "qcom,rpmcc-msm8992"; + compatible = "qcom,rpmcc-msm8992", "qcom,rpmcc"; }; &tcsr_mutex { diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 7317feb128fa..367ed913902c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -247,7 +247,7 @@ qcom,smd-channels = "rpm_requests"; rpmcc: rpmcc { - compatible = "qcom,rpmcc-msm8994"; + compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 67d2253e2c35..9d993f25046a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -461,7 +461,7 @@ qcom,glink-channels = "rpm_requests"; rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msm8996"; + compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index acf120f91b42..bc446c6002d0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -226,7 +226,7 @@ qcom,glink-channels = "rpm_requests"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcs404"; + compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; #clock-cells = <1>; }; From 73de2adfb2cd56299c869d5f9b0b9d6af893b66e Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:47:26 +0530 Subject: [PATCH 320/791] ARM: dts: qcom: Add PMIC pmx65 dts Add DTS for PMIC PMX65 found in Qualcomm platforms. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647411447-25249-6-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-pmx65.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-pmx65.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi new file mode 100644 index 000000000000..5411b833d26e --- /dev/null +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + pmic@1 { + compatible = "qcom,pmx65", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx65_temp: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx65_gpios: pinctrl@8800 { + compatible = "qcom,pmx65-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From 1ebc5adc2612679fae6678251dd50b63f9bac6af Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:47:24 +0530 Subject: [PATCH 321/791] ARM: dts: qcom: sdx65-mtp: Add pmx65 pmic SDX65-mtp features PMX65 pmic, so include the dts as well. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647411447-25249-4-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 9fa251aaaa45..408d30e3ba08 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -7,6 +7,7 @@ #include "qcom-sdx65.dtsi" #include #include +#include "qcom-pmx65.dtsi" / { model = "Qualcomm Technologies, Inc. SDX65 MTP"; From 52fedb2f324d9be967cf760dcdc894b37f5a95d9 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:47:25 +0530 Subject: [PATCH 322/791] ARM: dts: qcom: sdx65: Add rpmpd node Add rpmpd node and opps for this node to the SDX65 dts. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647411447-25249-5-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 51 +++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index ba7b6c5c1562..7e2697f1e665 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -244,6 +245,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx65-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; }; From dc39466a735b9a926e3101560ce094afdfeff9d3 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:47:27 +0530 Subject: [PATCH 323/791] ARM: dts: qcom: sdx65-mtp: Add regulator nodes Add the regulators found on SDX65 MTP. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647411447-25249-7-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 197 +++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 408d30e3ba08..ad99f561731d 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "qcom-sdx65.dtsi" +#include #include #include #include "qcom-pmx65.dtsi" @@ -21,8 +22,204 @@ chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx65_bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; }; &blsp1_uart3 { status = "ok"; }; + +&apps_rsc { + pmx65-rpmh-regulators { + compatible = "qcom,pmx65-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-supply = <&vreg_s2b_1p224>; + vdd-l2-l18-supply = <&vreg_s2b_1p224>; + vdd-l3-supply = <&vreg_s8b_0p824>; + vdd-l4-supply = <&vreg_s7b_0p936>; + vdd-l5-l6-l16-supply = <&vreg_s4b_1p824>; + vdd-l7-supply = <&vreg_s3b_0p776>; + vdd-l8-l9-supply = <&vreg_s8b_0p824>; + vdd-l10-supply = <&vreg_bob_3p3>; + vdd-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l12-supply = <&vreg_s2b_1p224>; + vdd-l14-supply = <&vreg_s3b_0p776>; + vdd-l15-supply = <&vreg_s2b_1p224>; + vdd-l17-supply = <&vreg_s8b_0p824>; + vdd-l19-supply = <&vreg_s3b_0p776>; + vdd-l20-supply = <&vreg_s7b_0p936>; + vdd-l21-supply = <&vreg_s7b_0p936>; + + vreg_s2b_1p224: smps2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3b_0p776: smps3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s4b_1p824: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s7b_0p936: smps7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s8b_0p824: smps8 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1300000>; + }; + + ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + ldo3 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + ldo4 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo7 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + ldo8 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo16 { + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + regulator-initial-mode = ; + }; + + ldo17 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + ldo19 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + ldo20 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + ldo21 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; +}; From d3eff0e174e5feecb8f45cf630a30f47f02f921c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:29 +0200 Subject: [PATCH 324/791] ARM: dts: qcom: msm8974-lge-nexus5: move gpio-keys out of soc The GPIO keys are not part of SoC and they should be defined inside of the root node. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-5-krzysztof.kozlowski@linaro.org --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 069136170198..6d5fb60e798f 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -19,6 +19,27 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + }; + smd { rpm { rpm_requests { @@ -448,27 +469,6 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - serial@f9960000 { status = "okay"; From c19865df6b142276ec4371ad534a1eb6fef5782d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:30 +0200 Subject: [PATCH 325/791] ARM: dts: qcom: msm8974-samsung-klte: move gpio-keys out of soc The GPIO keys are not part of SoC and they should be defined inside of the root node. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-6-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 64 +++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 96e1c978b878..6e036a440532 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -20,6 +20,38 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-down { + label = "volume_down"; + gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + home-key { + label = "home_key"; + gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + }; + smd { rpm { rpm_requests { @@ -347,38 +379,6 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - - home-key { - label = "home_key"; - gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - volume-up { - label = "volume_up"; - gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - }; - pinctrl@fd510000 { blsp2_uart8_pins_active: blsp2-uart8-pins-active { pins = "gpio45", "gpio46", "gpio47", "gpio48"; From 43cdc159d203eb6d02b312409e634a3fa06632ac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:32 +0200 Subject: [PATCH 326/791] ARM: dts: qcom: do not use underscore in node name Align RPM requests node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski [bjorn: Fixed up qcom-{apq8074,msm8974}-*.dts to match the qcom-msm8974.dtsi] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-8-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 2 +- arch/arm/boot/dts/qcom-apq8084.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 2 +- arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 2 +- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 2 +- arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts | 2 +- arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts | 2 +- arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts | 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 10 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 91e5a40de6f8..34c0ba7fa358 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -227,7 +227,7 @@ smd { compatible = "qcom,smd"; - modem@0 { + modem-edge { interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 3>; @@ -236,7 +236,7 @@ status = "disabled"; }; - q6@1 { + q6-edge { interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 15>; @@ -245,7 +245,7 @@ status = "disabled"; }; - dsps@3 { + dsps-edge { interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&sps_sic_non_secure 0x4080 0>; @@ -254,7 +254,7 @@ status = "disabled"; }; - riva@6 { + riva-edge { interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 25>; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 83793b835d40..e2b4e4fc6377 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -147,7 +147,7 @@ smd { rpm { - rpm_requests { + rpm-requests { pm8841-regulators { s1 { regulator-min-microvolt = <675000>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 52240fc7a1a6..da50a1a0197f 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -470,7 +470,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests { + rpm-requests { compatible = "qcom,rpm-apq8084"; qcom,smd-channels = "rpm_requests"; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 6d77e0f8ca4d..9dbfc9f8646a 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -57,7 +57,7 @@ smd { rpm { - rpm_requests { + rpm-requests { pm8841-regulators { s1 { regulator-min-microvolt = <675000>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 6d5fb60e798f..5fbdba73c07f 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -42,7 +42,7 @@ smd { rpm { - rpm_requests { + rpm-requests { pm8841-regulators { s1 { regulator-min-microvolt = <675000>; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 6e036a440532..1f630120c01f 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -54,7 +54,7 @@ smd { rpm { - rpm_requests { + rpm-requests { pma8084-regulators { compatible = "qcom,rpm-pma8084-regulators"; status = "okay"; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts index 79e2cfbbb1ba..8cace789fb26 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts @@ -60,7 +60,7 @@ smd { rpm { - rpm_requests { + rpm-requests { pm8841-regulators { s1 { regulator-min-microvolt = <675000>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts index e66937e3f7dd..3c4a7d760ba9 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts @@ -55,7 +55,7 @@ smd { rpm { - rpm_requests { + rpm-requests { pm8941-regulators { vdd_l1_l3-supply = <&pm8941_s1>; vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index a62e5c25b23c..f4a2e2560777 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -60,7 +60,7 @@ smd { rpm { - rpm_requests { + rpm-requests { pm8841-regulators { s1 { regulator-min-microvolt = <675000>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 4a1f3768d75c..c8ff4c21d852 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1614,7 +1614,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests { + rpm-requests { compatible = "qcom,rpm-msm8974"; qcom,smd-channels = "rpm_requests"; From a30be44449c8847280c775b88c7904f52621791b Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 11 Apr 2022 15:20:09 +0530 Subject: [PATCH 327/791] ARM: dts: qcom: sdx65: Add reserved memory nodes Add reserved memory nodes to the SDX65 dtsi as defined by the memory map. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649670615-21268-2-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 +++++++++++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 45 ++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index ad99f561731d..79dc31aa7cd1 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -23,6 +23,27 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_dsm: memory@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg = <0x90800000 0x10000000>; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7e2697f1e665..dcc94c29eecf 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -61,11 +61,56 @@ #size-cells = <1>; ranges; + tz_heap_mem: memory@8fcad000 { + no-map; + reg = <0x8fcad000 0x40000>; + }; + + secdata_mem: memory@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + hyp_mem: memory@8fd00000 { + no-map; + reg = <0x8fd00000 0x80000>; + }; + + access_control_mem: memory@8fd80000 { + no-map; + reg = <0x8fd80000 0x80000>; + }; + + aop_mem: memory@8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + smem_mem: memory@8fe20000 { + no-map; + reg = <0x8fe20000 0xc0000>; + }; + cmd_db: reserved-memory@8fee0000 { compatible = "qcom,cmd-db"; reg = <0x8fee0000 0x20000>; no-map; }; + + tz_mem: memory@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + }; + + tz_apps_mem: memory@90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + + llcc_tcm_mem: memory@15800000 { + no-map; + reg = <0x15800000 0x800000>; + }; }; soc: soc { From dc1a380fcb6736c78804174566fe64800b0175d4 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 11 Apr 2022 15:20:11 +0530 Subject: [PATCH 328/791] ARM: dts: qcom: sdx65: Add support for SDHCI controller Add devicetree support for SDHCI controller found in Qualcomm SDX65 platform. The SDHCI controller is based on the MSM SDHCI v5 IP. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649670615-21268-4-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index dcc94c29eecf..77bca58d88c1 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -137,6 +137,19 @@ status = "disabled"; }; + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, From 98187f7b74bf52ff8f7d28e6b987b6c260b68810 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 11 Apr 2022 15:20:13 +0530 Subject: [PATCH 329/791] ARM: dts: qcom: sdx65: Enable ARM SMMU Add a node for the ARM SMMU found in the SDX65. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649670615-21268-6-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 77bca58d88c1..f50a8a404ce0 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -190,6 +190,46 @@ interrupt-controller; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17800000 { compatible = "qcom,msm-qgic2"; interrupt-controller; From 78254f3b7d7c07e1feced158f909e00109c94bd2 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 11 Apr 2022 15:20:14 +0530 Subject: [PATCH 330/791] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX65 platform. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649670615-21268-7-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index f50a8a404ce0..210e55c0fb5f 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -137,6 +137,12 @@ status = "disabled"; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; From 05d39fc06cee5b11b195d0d5fec55d01da2781cb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:32:34 +0100 Subject: [PATCH 331/791] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SMARC EVK Document the Renesas SMARC EVK board which is based on the Renesas RZ/G2UL Type-1 (R9A07G043U11) SoC. The SMARC EVK consists of an RZ/G2UL Type-1 SoM module and a SMARC carrier board. The SoM module sits on top of the carrier board. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220402073234.24625-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index fa435d6fda77..f61807103867 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -405,6 +405,8 @@ properties: - description: RZ/G2UL (R9A07G043) items: + - enum: + - renesas,smarc-evk # SMARC EVK - enum: - renesas,r9a07g043u11 # RZ/G2UL Type-1 - renesas,r9a07g043u12 # RZ/G2UL Type-2 From eb2789785428e2dbc3d5f413b16c67ff90d828c1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:30:34 +0100 Subject: [PATCH 332/791] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev. 0.51, Nov. 2021). Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220402073037.23947-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a07g043-cpg.h | 184 ++++++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 include/dt-bindings/clock/r9a07g043-cpg.h diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h new file mode 100644 index 000000000000..27e232733096 --- /dev/null +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ + +#include + +/* R9A07G043 CPG Core Clocks */ +#define R9A07G043_CLK_I 0 +#define R9A07G043_CLK_I2 1 +#define R9A07G043_CLK_S0 2 +#define R9A07G043_CLK_SPI0 3 +#define R9A07G043_CLK_SPI1 4 +#define R9A07G043_CLK_SD0 5 +#define R9A07G043_CLK_SD1 6 +#define R9A07G043_CLK_M0 7 +#define R9A07G043_CLK_M2 8 +#define R9A07G043_CLK_M3 9 +#define R9A07G043_CLK_HP 10 +#define R9A07G043_CLK_TSU 11 +#define R9A07G043_CLK_ZT 12 +#define R9A07G043_CLK_P0 13 +#define R9A07G043_CLK_P1 14 +#define R9A07G043_CLK_P2 15 +#define R9A07G043_CLK_AT 16 +#define R9A07G043_OSCCLK 17 +#define R9A07G043_CLK_P0_DIV2 18 + +/* R9A07G043 Module Clocks */ +#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */ +#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */ +#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */ +#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */ +#define R9A07G043_SYC_CNT_CLK 11 +#define R9A07G043_DMAC_ACLK 12 +#define R9A07G043_DMAC_PCLK 13 +#define R9A07G043_OSTM0_PCLK 14 +#define R9A07G043_OSTM1_PCLK 15 +#define R9A07G043_OSTM2_PCLK 16 +#define R9A07G043_MTU_X_MCK_MTU3 17 +#define R9A07G043_POE3_CLKM_POE 18 +#define R9A07G043_WDT0_PCLK 19 +#define R9A07G043_WDT0_CLK 20 +#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */ +#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */ +#define R9A07G043_SPI_CLK2 23 +#define R9A07G043_SPI_CLK 24 +#define R9A07G043_SDHI0_IMCLK 25 +#define R9A07G043_SDHI0_IMCLK2 26 +#define R9A07G043_SDHI0_CLK_HS 27 +#define R9A07G043_SDHI0_ACLK 28 +#define R9A07G043_SDHI1_IMCLK 29 +#define R9A07G043_SDHI1_IMCLK2 30 +#define R9A07G043_SDHI1_CLK_HS 31 +#define R9A07G043_SDHI1_ACLK 32 +#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */ +#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */ +#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_PCLK2 42 +#define R9A07G043_SSI0_PCLK_SFR 43 +#define R9A07G043_SSI1_PCLK2 44 +#define R9A07G043_SSI1_PCLK_SFR 45 +#define R9A07G043_SSI2_PCLK2 46 +#define R9A07G043_SSI2_PCLK_SFR 47 +#define R9A07G043_SSI3_PCLK2 48 +#define R9A07G043_SSI3_PCLK_SFR 49 +#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HCLK 51 +#define R9A07G043_USB_U2H1_HCLK 52 +#define R9A07G043_USB_U2P_EXR_CPUCLK 53 +#define R9A07G043_USB_PCLK 54 +#define R9A07G043_ETH0_CLK_AXI 55 +#define R9A07G043_ETH0_CLK_CHI 56 +#define R9A07G043_ETH1_CLK_AXI 57 +#define R9A07G043_ETH1_CLK_CHI 58 +#define R9A07G043_I2C0_PCLK 59 +#define R9A07G043_I2C1_PCLK 60 +#define R9A07G043_I2C2_PCLK 61 +#define R9A07G043_I2C3_PCLK 62 +#define R9A07G043_SCIF0_CLK_PCK 63 +#define R9A07G043_SCIF1_CLK_PCK 64 +#define R9A07G043_SCIF2_CLK_PCK 65 +#define R9A07G043_SCIF3_CLK_PCK 66 +#define R9A07G043_SCIF4_CLK_PCK 67 +#define R9A07G043_SCI0_CLKP 68 +#define R9A07G043_SCI1_CLKP 69 +#define R9A07G043_IRDA_CLKP 70 +#define R9A07G043_RSPI0_CLKB 71 +#define R9A07G043_RSPI1_CLKB 72 +#define R9A07G043_RSPI2_CLKB 73 +#define R9A07G043_CANFD_PCLK 74 +#define R9A07G043_GPIO_HCLK 75 +#define R9A07G043_ADC_ADCLK 76 +#define R9A07G043_ADC_PCLK 77 +#define R9A07G043_TSU_PCLK 78 + +/* R9A07G043 Resets */ +#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */ +#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */ +#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */ +#define R9A07G043_DMAC_ARESETN 17 +#define R9A07G043_DMAC_RST_ASYNC 18 +#define R9A07G043_SYC_RESETN 19 +#define R9A07G043_OSTM0_PRESETZ 20 +#define R9A07G043_OSTM1_PRESETZ 21 +#define R9A07G043_OSTM2_PRESETZ 22 +#define R9A07G043_MTU_X_PRESET_MTU3 23 +#define R9A07G043_POE3_RST_M_REG 24 +#define R9A07G043_WDT0_PRESETN 25 +#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */ +#define R9A07G043_SPI_RST 27 +#define R9A07G043_SDHI0_IXRST 28 +#define R9A07G043_SDHI1_IXRST 29 +#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */ +#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_RST_M2_REG 36 +#define R9A07G043_SSI1_RST_M2_REG 37 +#define R9A07G043_SSI2_RST_M2_REG 38 +#define R9A07G043_SSI3_RST_M2_REG 39 +#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HRESETN 41 +#define R9A07G043_USB_U2H1_HRESETN 42 +#define R9A07G043_USB_U2P_EXL_SYSRST 43 +#define R9A07G043_USB_PRESETN 44 +#define R9A07G043_ETH0_RST_HW_N 45 +#define R9A07G043_ETH1_RST_HW_N 46 +#define R9A07G043_I2C0_MRST 47 +#define R9A07G043_I2C1_MRST 48 +#define R9A07G043_I2C2_MRST 49 +#define R9A07G043_I2C3_MRST 50 +#define R9A07G043_SCIF0_RST_SYSTEM_N 51 +#define R9A07G043_SCIF1_RST_SYSTEM_N 52 +#define R9A07G043_SCIF2_RST_SYSTEM_N 53 +#define R9A07G043_SCIF3_RST_SYSTEM_N 54 +#define R9A07G043_SCIF4_RST_SYSTEM_N 55 +#define R9A07G043_SCI0_RST 56 +#define R9A07G043_SCI1_RST 57 +#define R9A07G043_IRDA_RST 58 +#define R9A07G043_RSPI0_RST 59 +#define R9A07G043_RSPI1_RST 60 +#define R9A07G043_RSPI2_RST 61 +#define R9A07G043_CANFD_RSTP_N 62 +#define R9A07G043_CANFD_RSTC_N 63 +#define R9A07G043_GPIO_RSTN 64 +#define R9A07G043_GPIO_PORT_RESETN 65 +#define R9A07G043_GPIO_SPARE_RESETN 66 +#define R9A07G043_ADC_PRESETN 67 +#define R9A07G043_ADC_ADRST_N 68 +#define R9A07G043_TSU_PRESETN 69 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ From 2e4d5fd6f58af8319273a8a7253e0dff2a3e17c1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:08 +0100 Subject: [PATCH 333/791] ARM: dts: rcar-gen2: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 1 + arch/arm/boot/dts/r8a7791.dtsi | 1 + arch/arm/boot/dts/r8a7792.dtsi | 1 + arch/arm/boot/dts/r8a7793.dtsi | 1 + arch/arm/boot/dts/r8a7794.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ed6dd4fcc503..a640488d513b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -274,6 +274,7 @@ compatible = "renesas,r8a7790-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0ccc162d3c2c..542ed0a71872 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -161,6 +161,7 @@ compatible = "renesas,r8a7791-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 9cdb73894ac2..a6d9367f8fa0 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -111,6 +111,7 @@ compatible = "renesas,r8a7792-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index dea4b1e108af..9ebe7bfaf0ed 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -146,6 +146,7 @@ compatible = "renesas,r8a7793-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index eac9ed8df0be..b601ee6f7580 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -128,6 +128,7 @@ compatible = "renesas,r8a7794-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 402>; From cb97d4855589ec097fd385a4068f21ba92373a88 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:09 +0100 Subject: [PATCH 334/791] ARM: dts: rzg1: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7743.dtsi | 1 + arch/arm/boot/dts/r8a7744.dtsi | 1 + arch/arm/boot/dts/r8a7745.dtsi | 1 + arch/arm/boot/dts/r8a77470.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 3502b5dcc04f..c0c145a5fe8d 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -140,6 +140,7 @@ compatible = "renesas,r8a7743-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index f5d4b8b85b6d..3f4fb53dd6df 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -140,6 +140,7 @@ compatible = "renesas,r8a7744-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index f877c51f769c..fe8e98a66d93 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -270,6 +270,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a7745-wdt", "renesas,rcar-gen2-wdt"; + interrupts = ; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 13ef1e9bf4d5..c90f2a270214 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -91,6 +91,7 @@ compatible = "renesas,r8a77470-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; resets = <&cpg 402>; From 2bc0aa18ee9f34613876f6ac7bf944ad65d63e17 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:10 +0100 Subject: [PATCH 335/791] arm64: dts: renesas: rcar-gen3: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + 8 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 4e87e8776a2b..742834fa7097 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -369,6 +369,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 6f79da8cc8c0..0f2635af7b58 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -334,6 +334,7 @@ compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 7d522ea5fca2..d4fe1d7f3c62 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -323,6 +323,7 @@ compatible = "renesas,r8a77961-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 9f858af8b762..bba07944228b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -205,6 +205,7 @@ compatible = "renesas,r8a77965-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 517892cf6294..79718234d85f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -108,6 +108,7 @@ compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 347c068ff2c5..148983130adf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -138,6 +138,7 @@ compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 7e0f1aab2135..af61c67b093d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -171,6 +171,7 @@ compatible = "renesas,r8a77990-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cac1f9467ffa..00254cf0aa92 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -94,6 +94,7 @@ compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 402>; From 7ac8afba2257f08e95ef7d0e3ed2ac47cad9195b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:11 +0100 Subject: [PATCH 336/791] arm64: dts: renesas: rzg2: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 12846125a4c9..faf5bbbb3710 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -283,6 +283,7 @@ compatible = "renesas,r8a774a1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index a4b406a346f9..be998bc40412 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -156,6 +156,7 @@ compatible = "renesas,r8a774b1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index e123c8d1bab9..4f69f90d88cb 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -145,6 +145,7 @@ compatible = "renesas,r8a774c0-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 402>; From ccc0dd722e66daac9d31d7c584f6c2ceabf6c493 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:12 +0100 Subject: [PATCH 337/791] arm64: dts: renesas: rcar-gen4: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index c80f4584035e..57d49d27cdca 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -88,6 +88,7 @@ compatible = "renesas,r8a779a0-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 907>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index ab0856b7a2bd..eaea28cc5ffb 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -63,6 +63,7 @@ compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 907>; From f191fba76916dc18c41cf6183d71dbf9a1d821c8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:01 +0200 Subject: [PATCH 338/791] arm64: dts: renesas: rcar-gen3: Add RPC device nodes Add device nodes for the SPI Multi I/O Bus Controllers (RPC-IF) on the various R-Car Gen3 SoCs that do not have support for them yet in their device trees (R-Car H3, M3-W, M3-W+, M3-N, E3, and D3). Based on patches in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/3231749c7b63df1a2134daabe66446a3e0e5515b.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 16 ++++++++++++++++ 6 files changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 742834fa7097..884210544ba0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2732,6 +2732,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7795-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a7795", "renesas,rcar-gen3-sata"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 0f2635af7b58..0d96b5bb9584 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2532,6 +2532,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7796-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index d4fe1d7f3c62..58e161e5dae0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2401,6 +2401,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77961-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index bba07944228b..ecca9582edf6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2379,6 +2379,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77965-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a77965", "renesas,rcar-gen3-sata"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index af61c67b093d..5d41e46d06f5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1838,6 +1838,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77990-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 00254cf0aa92..0eccf81db374 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1238,6 +1238,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77995-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From a1de91f0ac71cfd3ff3dd630ab560238db05bef6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:02 +0200 Subject: [PATCH 339/791] arm64: dts: renesas: draak: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common Draak board DTS file. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/0f3d3018ecfcdce1bce67708708a6d3a98368b10.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/draak.dtsi | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index eb0327c0df48..2a784ee6da49 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -541,6 +541,12 @@ function = "pwm1"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data"; function = "scif2"; @@ -630,6 +636,58 @@ }; }; +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; From 5f300a7f3953aea5b2ce996a0bdec31ffd108999 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:03 +0200 Subject: [PATCH 340/791] arm64: dts: renesas: ebisu: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common Ebisu board DTS file. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b14c769f62211b67d90dbd2f127357756e6cb4fa.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 67231c8576c5..ae688707f8c6 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -600,6 +600,12 @@ function = "pwm5"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -711,6 +717,58 @@ }; +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; From 1ee6674bbe1cd6bd38216be3b7693ef1e5e2eabf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:04 +0200 Subject: [PATCH 341/791] arm64: dts: renesas: salvator-common: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common Salvator-X(S) board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/cfc6af8a4c42febcc405b7356c38448eec8e29b0.1648548339.git.geert+renesas@glider.be --- .../boot/dts/renesas/salvator-common.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 6092dc4531ad..7ad72f377a35 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -866,6 +866,55 @@ }; }; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; From 79e903fbf43b734badb33723525a84d2ffeb9c8d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:05 +0200 Subject: [PATCH 342/791] arm64: dts: renesas: ulcb: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common ULCB board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/61a63e819d4296760ca7ae83ef5226a2c4d7bd93.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 49 +++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index b4bdb2d7e4ba..90a4c0629d24 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -426,6 +426,55 @@ }; }; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; From 061ba41c7449a9cf4bbf2b6930eb0ded69e5eead Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 1 Apr 2022 15:57:02 +0100 Subject: [PATCH 343/791] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file and drops deleting pinctl* properties from DTS file. RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220401145702.17954-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 8 ++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 74a2f2bade10..fc34058002e2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -13,9 +13,3 @@ model = "Renesas SMARC EVK based on r9a07g044c2"; compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; - -&spi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index d275a55333e3..a78a8def363e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -106,6 +106,13 @@ input-enable; }; + spi1_pins: spi1 { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; + ssi0_pins: ssi0 { pinmux = , /* BCK */ , /* RCK */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index f73b4acb8f9e..856c949796ff 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -90,3 +90,11 @@ status = "okay"; }; #endif + +#if (SW_RSPI_CAN) +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif From f40846e7c9f50bfbba96d566c63cbdb57b817249 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 1 Apr 2022 18:54:27 +0100 Subject: [PATCH 344/791] arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi On RZ/G2{L,LC} SoM module, gpio for power selection is connected to P39_1 whereas on RZ/G2UL it is connected to P6_1. So move gpios property of vccq_sdhi1 regulator from common dtsi to soc specific dtsi. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220401175427.19078-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 1 - arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 4 ++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 8dd1c69a6749..0e61b85efb43 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -74,7 +74,6 @@ regulator-name = "SDHI1 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index c934cd3633a4..aadc41515093 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -48,3 +48,7 @@ status = "okay"; }; #endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 856c949796ff..74a844ea7537 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -98,3 +98,7 @@ status = "disabled"; }; #endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; From cf40c9689e5109bf5e4c29038c9f450223aaad2b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 12 Apr 2022 17:13:13 +0100 Subject: [PATCH 345/791] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC Add initial DTSI for RZ/G2UL SoC. Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share the common dtsi (rz-smarc.dtsi) file. Place holders are added in device nodes to avoid compilation errors for the devices which have not been enabled yet on RZ/G2UL SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 413 +++++++++++++++++++++ 1 file changed, 413 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi new file mode 100644 index 000000000000..aed9ab4f9ba4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a07g043"; + #address-cells = <2>; + #size-cells = <2>; + + audio_clk1: audio-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio-clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssi0: ssi@10049c00 { + reg = <0 0x10049c00 0 0x400>; + #sound-dai-cells = <0>; + /* place holder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI1_RST>; + status = "disabled"; + }; + + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + /* place holder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + /* place holder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + /* place holder */ + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058c00 0 0x400>; + /* place holder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + /* place holder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + /* place holder */ + }; + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g043-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_DMAC_ARESETN>, + <&cpg R9A07G043_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = ; + }; + + sdhi0: mmc@11c00000 { + reg = <0x0 0x11c00000 0 0x10000>; + /* place holder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + /* place holder */ + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + /* place holder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + /* place holder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + /* place holder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + /* place holder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + /* place holder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + /* place holder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + /* place holder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + /* place holder */ + }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + /* place holder */ + }; + + wdt2: watchdog@12800400 { + reg = <0 0x12800400 0 0x400>; + /* place holder */ + }; + + ostm0: timer@12801000 { + reg = <0x0 0x12801000 0x0 0x400>; + /* place holder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + /* place holder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + /* place holder */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; From 895199bc4e5261b67b688a915c592dd4c3af113c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 12 Apr 2022 17:13:14 +0100 Subject: [PATCH 346/791] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11): - memory - External input clock - CPG - DMA - SCIF It shares the same carrier board with RZ/G2L, but the pin mapping is different. Disable the device nodes which are not tested and delete the corresponding pinctrl definitions. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r9a07g043u11-smarc.dts | 111 ++++++++++++++++++ .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 25 ++++ 3 files changed, 138 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d000f6b131dc..fa9811251fd7 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -75,6 +75,8 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb + dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts new file mode 100644 index 000000000000..aaa29f83e84c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g043.dtsi" +#include "rzg2ul-smarc-som.dtsi" +#include "rz-smarc-common.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043u11"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; +}; + +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&hsusb { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +&ohci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&scif0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +&sdhi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-names; + /delete-property/ vmmc-supply; + status = "disabled"; +}; + +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ssi0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi new file mode 100644 index 000000000000..3bbb8fcd604c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC SOM common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + chosen { + bootargs = "ignore_loglevel"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; From 2d10555298576a95b637a5087751d0aad570964d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:22 +0100 Subject: [PATCH 347/791] arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index aed9ab4f9ba4..f24756d89bc2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -275,10 +275,16 @@ }; pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - /* place holder */ + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; }; dmac: dma-controller@11820000 { From 4e44055440e1fef93e830bd06111bbbb0a89fa44 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:23 +0100 Subject: [PATCH 348/791] arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting the pinctrl-0 and pinctrl-names properties for scif0 node so that we now actually make use of these properties for scif0. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a07g043u11-smarc.dts | 6 +---- .../dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index aaa29f83e84c..64370faf8f6d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r9a07g043.dtsi" #include "rzg2ul-smarc-som.dtsi" +#include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" / { @@ -73,11 +74,6 @@ status = "disabled"; }; -&scif0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; -}; - &sdhi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-1; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..2db9c92cf01f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC pincontrol parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; +}; From 20e63d3948985672b9e8efa98ff3643d91378e84 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:24 +0100 Subject: [PATCH 349/791] arm64: dts: renesas: r9a07g043: Add SDHI nodes Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 26 ++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index f24756d89bc2..c013d4fbe9f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -334,13 +334,35 @@ }; sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; phyrst: usbphy-ctrl@11c40000 { From 13ea8b3584c09f0ab94d5447ff2965d255329a88 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:25 +0100 Subject: [PATCH 350/791] arm64: dts: renesas: r9a07g043: Add GbEthernet nodes Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c013d4fbe9f7..c8aadbe55278 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -365,6 +365,46 @@ status = "disabled"; }; + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + phyrst: usbphy-ctrl@11c40000 { reg = <0 0x11c40000 0 0x10000>; /* place holder */ From a74a0bf3f329415008c1a374118d27023a3d4735 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:26 +0100 Subject: [PATCH 351/791] arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform Enable the microSD card slot connected to SDHI1 on the RZ/G2UL SMARC platform by removing the sdhi1 override which disabled it, and by adding the necessary pinmux required for SDHI1. This patch also adds gpios property to vccq_sdhi1 regulator. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a07g043u11-smarc.dts | 12 +----- .../dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 39 +++++++++++++++++++ .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 9 +++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 14 +++++++ 4 files changed, 63 insertions(+), 11 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 64370faf8f6d..08a0404c6f0b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -7,9 +7,7 @@ /dts-v1/; #include "r9a07g043.dtsi" -#include "rzg2ul-smarc-som.dtsi" -#include "rzg2ul-smarc-pinfunction.dtsi" -#include "rz-smarc-common.dtsi" +#include "rzg2ul-smarc.dtsi" / { model = "Renesas SMARC EVK based on r9a07g043u11"; @@ -74,14 +72,6 @@ status = "disabled"; }; -&sdhi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-1; - /delete-property/ pinctrl-names; - /delete-property/ vmmc-supply; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 2db9c92cf01f..b515748e6a9a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -17,6 +17,45 @@ ; /* RxD */ }; + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = ; /* SD1_CD */ + }; + }; + sound_clk_pins: sound_clk { pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 3bbb8fcd604c..8ecc650099a7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -18,6 +18,15 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi new file mode 100644 index 000000000000..f47b4e2e0feb --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "rzg2ul-smarc-som.dtsi" +#include "rzg2ul-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; +}; From ed8efe50b76e751791a9aa4ce1f95fe3d9d794ac Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:27 +0100 Subject: [PATCH 352/791] arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platform RZ/G2UL SoM has both 64GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on SW1[2] on SoM module. Set SW1[2] to position OFF for selecting eMMC Set SW1[2] to position ON for selecting microSD This patch enables eMMC on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 104 ++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 8 ++ 2 files changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 8ecc650099a7..0d6fc0d84783 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -19,6 +19,15 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator1 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; @@ -27,8 +36,103 @@ regulator-boot-on; regulator-always-on; }; + +#if !(SW_SW0_DEV_SEL) + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; +#endif }; &extal_clk { clock-frequency = <24000000>; }; + +&pinctrl { + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = ; /* SD0_CD */ + }; + }; +}; + +#if (SW_SW0_DEV_SEL) +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#else +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index f47b4e2e0feb..f8c90ff676fe 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -5,6 +5,14 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * Please change below macros according to SW1 setting + */ +#define SW_SW0_DEV_SEL 1 + #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" From 6494e4f90503cb4027632dfcedcb7a683d829db0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:28 +0100 Subject: [PATCH 353/791] arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0 device selection is based on the SW1[3] switch position. Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. Set SW1[3] to position ON for selecting Ethernet0. This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 97 ++++++++++++++++++- arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 2 + 2 files changed, 98 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 0d6fc0d84783..b0822679a55b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -9,8 +9,13 @@ #include / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; }; memory@48000000 { @@ -52,11 +57,101 @@ #endif }; +#if (!SW_ET0_EN_N) +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + &extal_clk { clock-frequency = <24000000>; }; &pinctrl { + eth0_pins: eth0 { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = , /* ET1_LINKSTA */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TXC */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + ; /* ET1_RXD3 */ + }; + sdhi0_emmc_pins: sd0emmc { sd0_emmc_data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index f8c90ff676fe..056a77369c8d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -9,9 +9,11 @@ * DIP-Switch SW1 setting * 1 : High; 0: Low * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) * Please change below macros according to SW1 setting */ #define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" From 8dd3cdeaf3032728e30a7ec5e79ca780fc86cf7a Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 13 Apr 2022 10:35:47 +0100 Subject: [PATCH 354/791] arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnel The SCMI power domain ID for all the coresight components is 8 while the previous/older SCPI domain was 0. When adding SCMI variant, couple of instances retained SCPI domain ID by mistake. Fix the same by using the correct SCMI power domain ID of 8. Link: https://lore.kernel.org/r/20220413093547.1699535-1-sudeep.holla@arm.com Fixes: 96bb0954860a ("arm64: dts: juno: Add separate SCMI variants") Cc: Robin Murphy Reported-by: Mike Leach Acked-by: Robin Murphy Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-r1-scmi.dts | 4 ++-- arch/arm64/boot/dts/arm/juno-r2-scmi.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts index 190a0fba4ad6..fd1f0d26d751 100644 --- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -7,11 +7,11 @@ }; etf@20140000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; funnel@20150000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts index dbf13770084f..35e6d4762c46 100644 --- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -7,11 +7,11 @@ }; etf@20140000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; funnel@20150000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; }; From e7676a00bc52b994960f89b118b0d548e4542372 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Wed, 13 Apr 2022 22:49:25 +0100 Subject: [PATCH 355/791] arm64: dts: juno: add CTI entries to device tree Add Coresight Cross Trigger Interface(CTI) entries to the device tree for all the Juno variants. Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org Reviewed-by: Mathieu Poirier Signed-off-by: Mike Leach Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 162 +++++++++++++++++++++- arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 37 ++++- arch/arm64/boot/dts/arm/juno-r1-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r1.dts | 25 ++++ arch/arm64/boot/dts/arm/juno-r2-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r2.dts | 25 ++++ arch/arm64/boot/dts/arm/juno-scmi.dtsi | 25 ++++ arch/arm64/boot/dts/arm/juno.dts | 25 ++++ 8 files changed, 302 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 446c8f476eec..4f40a5c8f565 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -117,7 +117,7 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { /* etf0 */ + etf_sys0: etf@20010000 { /* etf0 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; @@ -141,7 +141,7 @@ }; }; - tpiu@20030000 { + tpiu_sys: tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>; @@ -194,7 +194,7 @@ }; }; - etr@20070000 { + etr_sys: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20070000 0 0x1000>; iommus = <&smmu_etr 0>; @@ -212,7 +212,7 @@ }; }; - stm@20100000 { + stm_sys: stm@20100000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x1000000>; @@ -289,6 +289,18 @@ }; }; + cti0: cti@22020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm0>; + }; + funnel@220c0000 { /* cluster0 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x220c0000 0 0x1000>; @@ -349,6 +361,18 @@ }; }; + cti1: cti@22120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm1>; + }; + cpu_debug2: cpu-debug@23010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23010000 0x0 0x1000>; @@ -374,6 +398,18 @@ }; }; + cti2: cti@23020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm2>; + }; + funnel@230c0000 { /* cluster1 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x230c0000 0 0x1000>; @@ -446,6 +482,18 @@ }; }; + cti3: cti@23120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm3>; + }; + cpu_debug4: cpu-debug@23210000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23210000 0x0 0x1000>; @@ -471,6 +519,18 @@ }; }; + cti4: cti@23220000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23220000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm4>; + }; + cpu_debug5: cpu-debug@23310000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23310000 0x0 0x1000>; @@ -496,6 +556,100 @@ }; }; + cti5: cti@23320000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23320000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm5>; + }; + + cti_sys0: cti@20020000 { /* sys_cti_0 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<2 3>; + arm,trig-in-types=; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&etr_sys>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=; + arm,trig-out-sigs=<7 6>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&etf_sys0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<4 5 6 7>; + arm,trig-in-types=; + arm,trig-out-sigs=<4 5>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&stm_sys>; + }; + + trig-conns@3 { + reg = <3>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&tpiu_sys>; + }; + }; + + cti_sys1: cti@20110000 { /* sys_cti_1 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0>; + arm,trig-in-types=; + arm,trig-out-sigs=<0>; + arm,trig-out-types=; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-out-sigs=<1 6>; + arm,trig-out-types=; + arm,trig-conn-name = "g_counter"; + }; + }; + gpu: gpu@2d000000 { compatible = "arm,juno-mali", "arm,mali-t624"; reg = <0 0x2d000000 0 0x10000>; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index eda3d9e18af6..2e43f4531308 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -23,7 +23,7 @@ }; }; - etf@20140000 { /* etf1 */ + etf_sys1: etf@20140000 { /* etf1 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20140000 0 0x1000>; @@ -82,4 +82,39 @@ }; }; + + cti_sys2: cti@20160000 { /* sys_cti_2 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20160000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&etf_sys1>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<2 3 4>; + arm,trig-in-types=; + arm,trig-conn-name = "ela_clus_0"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<5 6 7>; + arm,trig-in-types=; + arm,trig-conn-name = "ela_clus_1"; + }; + }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts index fd1f0d26d751..dd9ea69f086f 100644 --- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -15,6 +15,10 @@ }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A57_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 0e24e29eb9b1..f099fb611d4e 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -9,6 +9,7 @@ /dts-v1/; #include +#include #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -313,3 +314,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts index 35e6d4762c46..de2cbac1d1c3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -15,6 +15,10 @@ }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A72_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index e609420ce3e4..709389582ae3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -9,6 +9,7 @@ /dts-v1/; #include +#include #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -319,3 +320,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A72_0>; +}; + +&cti1 { + cpu = <&A72_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi index d72dcff9bf06..4135d62e44a2 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -154,6 +154,31 @@ power-domains = <&scmi_devpd 8>; }; +&cti0 { + power-domains = <&scmi_devpd 8>; +}; +&cti1 { + power-domains = <&scmi_devpd 8>; +}; +&cti2 { + power-domains = <&scmi_devpd 8>; +}; +&cti3 { + power-domains = <&scmi_devpd 8>; +}; +&cti4 { + power-domains = <&scmi_devpd 8>; +}; +&cti5 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys0 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys1 { + power-domains = <&scmi_devpd 8>; +}; + &gpu { clocks = <&scmi_dvfs 2>; power-domains = <&scmi_devpd 9>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index f00cffbd032c..dbc22e70b62c 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -9,6 +9,7 @@ /dts-v1/; #include +#include #include "juno-base.dtsi" / { @@ -295,3 +296,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; From 3c3b352863ec4f88cc3ca8fcb4dff4d6f18483f0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Apr 2022 20:46:33 +0200 Subject: [PATCH 356/791] ARM: dts: ux500: Add NFC to the Codina This adds the PN544 NFC chip mounted on some of the Codina models numbered GT-I8160P. The "P" at the end of the product number indicates that an NFC chip is mounted. Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-codina.dts | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index acbe43269c38..0b7bb54aa24d 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -307,7 +307,22 @@ #address-cells = <1>; #size-cells = <0>; - /* TODO: add the NFC chip here */ + nfc@2b { + /* NXP NFC circuit PN544 C1 marked NXP 44501 */ + compatible = "nxp,pn544-i2c"; + /* IF0, IF1 high, gives I2C address 0x2B */ + reg = <0x2b>; + clock-frequency = <400000>; + /* NFC IRQ on GPIO32 */ + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + /* GPIO 31 */ + firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + /* GPIO88 */ + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pn544_codina_default>; + }; }; spi-gpio-0 { @@ -854,6 +869,20 @@ }; }; }; + nfc { + pn544_codina_default: pn544_codina { + /* Interrupt line */ + codina_cfg1 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_nopull>; + }; + /* Enable and firmware GPIOs */ + codina_cfg2 { + pins = "GPIO31_V3", "GPIO88_C4"; + ste,config = <&gpio_out_lo>; + }; + }; + }; vibrator { vibrator_default: vibrator_default { codina_cfg1 { From b9cff8783439ff1803709128af3a0e04c5f5f047 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sun, 10 Apr 2022 12:44:55 +0300 Subject: [PATCH 357/791] ARM: dts: BCM5301X: Disable gmac0 and enable port@8 on Asus RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Disable gmac0 which is not connected to any switch MAC. Enable port@8 of the Broadcom switch which is connected to gmac2. Signed-off-by: Arınç ÜNAL Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 2f944d1c0330..d8503758342b 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -232,7 +232,6 @@ reg = <8>; ethernet = <&gmac2>; label = "cpu"; - status = "disabled"; fixed-link { speed = <1000>; @@ -242,6 +241,10 @@ }; }; +&gmac0 { + status = "disabled"; +}; + &gmac1 { nvmem-cells = <&et1macaddr>; nvmem-cell-names = "mac-address"; From 472f20b4f2534236fb90cdf93b42a071eb77bc5e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Apr 2022 14:35:42 -0500 Subject: [PATCH 358/791] arm64: dts: imx8mn: Enable HS400-ES The SDHC controller in the imx8mn has the same controller as the imx8mm which supports HS400-ES. Change the compatible fallback to imx8mm to enable it, but keep the imx7d-usdhc to prevent breaking backwards compatibility. Signed-off-by: Adam Ford Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 99f0f5026674..13c51363cc06 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -933,7 +933,7 @@ }; usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -947,7 +947,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -961,7 +961,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, From 746a72411cddb87d3c09dc42f901e6e69467744f Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Apr 2022 14:35:43 -0500 Subject: [PATCH 359/791] arm64: dts: imx8mp: Enable HS400-ES The SDHC controller in the imx8mp has the same controller as the imx8mm which supports HS400-ES. Change the compatible fallback to imx8mm to enable it, but keep the imx7d-usdhc to prevent breaking backwards compatibility. Signed-off-by: Adam Ford Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c42d25bd16ed..7ad824e6b820 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -847,7 +847,7 @@ }; usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_DUMMY>, @@ -861,7 +861,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_DUMMY>, @@ -875,7 +875,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_DUMMY>, From 0d9968d98467d75cfdcb903f6c202884f2299521 Mon Sep 17 00:00:00 2001 From: Ming Qian Date: Mon, 11 Apr 2022 14:50:49 +0800 Subject: [PATCH 360/791] arm64: dts: freescale: imx8q: add imx vpu codec entries Add the Video Processing Unit node for IMX8Q SoC. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 74 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 25 +++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 24 ++++++ 3 files changed, 123 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100644 index 000000000000..c6540768bdb9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Dong Aisheng + */ + +vpu: vpu@2c000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + reg = <0 0x2c000000 0 0x1000000>; + power-domains = <&pd IMX_SC_R_VPU>; + status = "disabled"; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + status = "disabled"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + status = "disabled"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + status = "disabled"; + }; + + vpu_core0: vpu-core@2d080000 { + reg = <0x2d080000 0x10000>; + compatible = "nxp,imx8q-vpu-decoder"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + status = "disabled"; + }; + + vpu_core1: vpu-core@2d090000 { + reg = <0x2d090000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + status = "disabled"; + }; + + vpu_core2: vpu-core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 863232a47004..07d8dd8160f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -135,6 +135,14 @@ status = "okay"; }; +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + &scu_key { status = "okay"; }; @@ -196,6 +204,23 @@ status = "okay"; }; +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index dbec7c106e0b..a79ae33cbad2 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -46,6 +46,9 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; cpus { @@ -162,10 +165,30 @@ #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; + + encoder_rpc: encoder-rpc@94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; }; pmu { @@ -287,6 +310,7 @@ /* sorted in register address */ #include "imx8-ss-img.dtsi" + #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" From 91dbd54ec55d3521f32beefddb64e81dc49e4abb Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:23 +0200 Subject: [PATCH 361/791] ARM: dts: imx6dl-colibri: Drop dedicated v1.1 device tree Drop Colibri V1.1 device tree, this is just a duplicate of Colibri V1.0 with the possibility to use SD cards in UHS mode if the carrier board does not have 3.3V pull up resistor. The dedicated device tree kept the feature switched of by setting the no-1-8-v property and thus does not offer anything different than what the regular device tree does. Thus drop the dedicated device tree and merge the preparation to allow enabling the feature should a carrier without pull ups be used into the regular device tree. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 - .../boot/dts/imx6dl-colibri-v1_1-eval-v3.dts | 31 ------------- .../boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi | 44 ------------------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 29 +++++++++++- 4 files changed, 27 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts delete mode 100644 arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 252353fb4e3b..ae3cac8e653b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -459,7 +459,6 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ - imx6dl-colibri-v1_1-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts deleted file mode 100644 index 223275f028f1..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -/dts-v1/; - -#include "imx6dl-colibri-eval-v3.dts" -#include "imx6qdl-colibri-v1_1-uhs.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; - compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", - "toradex,colibri_imx6dl-v1_1", - "toradex,colibri_imx6dl-eval-v3", - "toradex,colibri_imx6dl", - "fsl,imx6dl"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; - /* - * Please make sure your carrier board does not pull-up any of - * the MMC/SD signals to 3.3 volt before attempting to activate - * UHS-I support. - * To let signaling voltage be changed to 1.8V, please - * delete no-1-8-v property (example below): - * /delete-property/no-1-8-v; - */ -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi deleted file mode 100644 index 7672fbfc29be..000000000000 --- a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -&iomuxc { - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 - >; - }; -}; - -/* Colibri MMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <&vgen3_reg>; - wakeup-source; - keep-power-in-suspend; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 4e2a309c93fa..16d38bc78b2a 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -370,11 +370,14 @@ /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ disable-wp; - vqmmc-supply = <®_module_3v3>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; bus-width = <4>; no-1-8-v; status = "disabled"; @@ -692,6 +695,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 From d9a9a7cf32c93c4c66b437438857f9fb7eb54d91 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 11 Apr 2022 12:46:38 -0700 Subject: [PATCH 362/791] arm64: dts: imx8m{m,n}-venice-*: add missing uart-has-rtscts property to UARTs Add the missing 'uart-has-rtscts' property to UART's that have hardware flow control capability. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 1 + 4 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 426483ec1f88..7a5d45e80982 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -221,6 +221,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; bluetooth { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 7e7231046215..70b2ae55e906 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -716,6 +716,7 @@ dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -731,6 +732,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -739,6 +741,7 @@ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index edf0c7aaaef0..1b03aa154688 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -644,6 +644,7 @@ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -660,6 +661,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; bluetooth { @@ -677,6 +679,7 @@ dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 3c0e63d2e82d..2c1f591335ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -625,6 +625,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; bluetooth { From e7fc48e6c7a8c3b37855703925d9320680041675 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 12 Apr 2022 16:32:38 +0200 Subject: [PATCH 363/791] arm64: dts: imx8mn: add 8MNANOD3L-EVK device tree Add a device tree for the 8MNANOD3L-EVK eval board which features an IMX8MN SoC. It is similar to the 8MNANODLPD4-EVK eval board except it has an IMX8MN UltraLite SoC and DDR3L memory. It esp. differs in the PMIC configuration because the SoC has a smaller package and thus the ARM core voltage is combined with the SoC voltage and the DDR voltage is 1.35V for the DDR3L memory. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-ddr3l-evk.dts | 114 ++++++++++++++++++ 2 files changed, 115 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 85c2c9ba5110..bdb76e67ccfe 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts new file mode 100644 index 000000000000..000e2c0596df --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include + +/ { + model = "NXP i.MX8MNano DDR3L EVK board"; + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; +}; + +&A53_0 { + cpu-supply = <&buck1>; +}; + +&A53_1 { + cpu-supply = <&buck1>; +}; + +&A53_2 { + cpu-supply = <&buck1>; +}; + +&A53_3 { + cpu-supply = <&buck1>; +}; + +&i2c1 { + pmic: pmic@25 { + compatible = "nxp,pca9450b"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC_0V9"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "NVCC_DRAM_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "VDD_SNVS_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_PHY_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; From b5f955c099cd9bccbf44681e8ee14c3d786ea25a Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Wed, 13 Apr 2022 23:33:11 +0200 Subject: [PATCH 364/791] arm64: dts: imx8mm-evk: add pwm1/backlight support Add pwm1/backlight support nodes for imx8mm_evk board. Align with u-boot dts References: - https://patchwork.ozlabs.org/project/uboot/patch/20220326111911.13720-9-tommaso.merciai@amarulasolutions.com/ Signed-off-by: Tommaso Merciai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6d67df7692f1..6a209395452a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -59,6 +59,14 @@ enable-active-high; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <250>; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; @@ -395,6 +403,12 @@ status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < @@ -549,4 +563,10 @@ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; }; From 7899eb6cb15d54a907adc73efacb4a373c697598 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 14 Apr 2022 09:15:05 -0700 Subject: [PATCH 365/791] arm64: dts: imx: Add i.MX8M Plus Gateworks gw7400 dts support The Gateworks GW7400 is an ARM based single board computer (SBC) featuring: - i.MX8M Plus SoC - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller (GSC) - QOS GbE - Microchip GbE Switch - Multiple multi-protocol RS232/RS485/RS422 Serial ports - USB 3.0 Front panel connector - onboard 802.11ac WiFi / BT - 3x miniPCIe socket with PCIe and USB 2.0 - 1x M.2 B/A-E socket with PCIe, USB 3.0 and dual nano-SIM sockets - off-board connectors for: MIPI DSI, MIPI CSI, SPI, GPIO, I2C - Wide range DC power input - Passive PoE - 802.3at PoE Signed-off-by: Tim Harvey Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-venice-gw74xx.dts | 896 ++++++++++++++++++ 2 files changed, 897 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index bdb76e67ccfe..851e6faf8c05 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts new file mode 100644 index 000000000000..101d31147603 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -0,0 +1,896 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + */ + +/dts-v1/; + +#include +#include +#include + +#include "imx8mp.dtsi" + +/ { + model = "Gateworks Venice GW74xx i.MX8MP board"; + compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + ethernet2 = &lan1; + ethernet3 = &lan2; + ethernet4 = &lan3; + ethernet5 = &lan4; + ethernet6 = &lan5; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-1 { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-2 { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-3 { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-4 { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + key-5 { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2>; + compatible = "regulator-fixed"; + regulator-name = "usb_usb2_vbus"; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can>; + regulator-name = "can2_stby"; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wifi_en: regulator-wifi-en { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wifi>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "dio0", "", "dio1", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "m2_gdis#", "", "", "", "", "", "", "m2_rst#", + "", "", "", "", "", "", "", "", + "m2_off#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "m2_wdis#", "", "", "", + "", "", "", "", "", "", "", "uart_rs485"; +}; + +&gpio5 { + gpio-line-names = + "uart_half", "uart_term", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_arm"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p2"; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lis2de12"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; + + switch: switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + pinctrl-0 = <&pinctrl_ksz>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + label = "lan1"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan2: port@1 { + reg = <1>; + label = "lan2"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan3: port@2 { + reg = <2>; + label = "lan3"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan4: port@3 { + reg = <3>; + label = "lan4"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan5: port@4 { + reg = <4>; + label = "lan5"; + local-mac-address = [00 00 00 00 00 00]; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* off-board header */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +/* GPS / off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* RS232 console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - Type C front panel */ +&usb3_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */ + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ + MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ + MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141 + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_ksz: kszgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */ + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19 + MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141 + >; + }; + + pinctrl_reg_can: regcangrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141 + >; + }; + + pinctrl_reg_wifi: regwifigrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 + >; + }; + + pinctrl_uart3_gpio: uart3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; From 5f5c579a34a87117c20b411df583ae816c1ec84f Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:24 +0200 Subject: [PATCH 366/791] ARM: dts: imx6dl-colibri: Fix I2C pinmuxing Fix names of extra pingroup node and property for gpio bus recovery. Without the change i2c2 is not functional. Fixes: 56f0df6b6b58 ("ARM: dts: imx*(colibri|apalis): add missing recovery modes to i2c") Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 16d38bc78b2a..c6112b1bffd4 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -132,7 +132,7 @@ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-0 = <&pinctrl_i2c2_gpio>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; @@ -491,7 +491,7 @@ >; }; - pinctrl_i2c2_gpio: i2c2grp { + pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 From 96a34c46e9dba69e4fe4b3edaaf278190f4c53be Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Mon, 11 Apr 2022 17:22:25 +0200 Subject: [PATCH 367/791] ARM: dts: imx6dl-colibri: Add gpio-line-names Add GPIO line names on module level. Those are all GPIOs which a user might use on his custom carrier board. If more meaningful names are available on the carrier board, the user can overwrite the line names in the carrier board level device tree. Signed-off-by: Oleksandr Suvorov Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 218 +++++++++++++++++++++++++ 1 file changed, 218 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index c6112b1bffd4..c92887f6af61 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -118,6 +118,224 @@ }; }; +&gpio1 { + gpio-line-names = "", + "SODIMM_67", + "SODIMM_180", + "SODIMM_196", + "SODIMM_174", + "SODIMM_176", + "SODIMM_194", + "SODIMM_55", + "SODIMM_63", + "SODIMM_28", + "SODIMM_93", + "SODIMM_69", + "SODIMM_99", + "SODIMM_130", + "SODIMM_106", + "SODIMM_98", + "SODIMM_192", + "SODIMM_49", + "SODIMM_190", + "SODIMM_51", + "SODIMM_47", + "SODIMM_53", + "", + "SODIMM_22"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_132", + "SODIMM_134", + "SODIMM_135", + "SODIMM_133", + "SODIMM_102", + "SODIMM_43", + "SODIMM_127", + "SODIMM_37", + "SODIMM_104", + "SODIMM_59", + "SODIMM_30", + "SODIMM_100", + "SODIMM_38", + "SODIMM_34", + "SODIMM_32", + "SODIMM_36", + "SODIMM_59", + "SODIMM_67", + "SODIMM_97", + "SODIMM_79", + "SODIMM_103", + "SODIMM_101", + "SODIMM_45", + "SODIMM_105", + "SODIMM_107", + "SODIMM_91", + "SODIMM_89", + "SODIMM_150", + "SODIMM_126", + "SODIMM_128", + "", + "SODIMM_94"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_111", + "SODIMM_113", + "SODIMM_115", + "SODIMM_117", + "SODIMM_119", + "SODIMM_121", + "SODIMM_123", + "SODIMM_125", + "SODIMM_110", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_118", + "SODIMM_120", + "SODIMM_122", + "SODIMM_124", + "", + "SODIMM_96", + "SODIMM_77", + "SODIMM_25", + "SODIMM_27", + "SODIMM_88", + "SODIMM_90", + "SODIMM_31", + "SODIMM_23", + "SODIMM_29", + "SODIMM_71", + "SODIMM_73", + "SODIMM_92", + "SODIMM_81", + "SODIMM_131", + "SODIMM_129"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "SODIMM_168", + "", + "", + "", + "", + "SODIMM_184", + "SODIMM_186", + "HDMI_15", + "HDMI_16", + "SODIMM_178", + "SODIMM_188", + "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "SODIMM_24", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_95", + "", + "SODIMM_86", + "", + "SODIMM_65", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_136", + "SODIMM_138", + "SODIMM_140", + "SODIMM_142", + "SODIMM_144", + "SODIMM_146", + "SODIMM_172", + "SODIMM_170", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_155", + "SODIMM_157", + "SODIMM_159", + "SODIMM_161", + "SODIMM_163", + "SODIMM_33", + "SODIMM_35", + "SODIMM_165", + "SODIMM_167"; +}; + +&gpio6 { + gpio-line-names = "SODIMM_169", + "SODIMM_171", + "SODIMM_173", + "SODIMM_175", + "SODIMM_177", + "SODIMM_179", + "SODIMM_85", + "SODIMM_166", + "SODIMM_160", + "SODIMM_162", + "SODIMM_158", + "SODIMM_164", + "", + "", + "SODIMM_156", + "SODIMM_75", + "SODIMM_154", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_152"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_19", + "SODIMM_21", + "", + "SODIMM_137"; +}; + &hdmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_ddc>; From 5ab9c76a82670f369969a08677c0afba22a8da15 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:26 +0200 Subject: [PATCH 368/791] ARM: dts: imx6dl-colibri: Disable add-on accessories The Toradex Colibri family is composed of SoM that can be plugged in various carrier board, with carrier boards allowing multiple optional add-on (e.g. display, camera, ...). Keep all the SoM specific part into the module .dtsi, disabling everything that is not self-contained on the board. The carrier board dts can reuse/enable anything that is defined in the module dtsi. Additional device tree overlays can be used for any accessories that are plugged in the carrier board. Disable parallel RGB: The parallel RGB interface (lcd_display) and all related nodes can be enabled in an overlay if used. Keep all nodes disabled in the module-level device tree. Rename display interface node to match imx6qdl-apalis to make it easier to use overlays. The pwm-backlight binding now requires the power-supply property, add it. Disable stmpe touchscreen: The touchscreen can be enabled in an overlay if used. Add labels to the stmpe sub nodes. Disable hdmi interface: HDMI can be enabled in an overlay if used. Update SPDX-License spelling to latest convention. Update Copyright year. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 59 +------------------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 57 ++++++++++++++++++- 2 files changed, 56 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 7da74e6f46d9..535b5c156229 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -58,53 +58,6 @@ wakeup-source; }; }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; }; /* Colibri SSP */ @@ -122,10 +75,6 @@ }; }; -&hdmi { - status = "okay"; -}; - /* * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ @@ -178,10 +127,6 @@ }; }; -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index c92887f6af61..f6243762e918 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -13,13 +13,59 @@ backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 127 191 223 239 247 251 255>; + default-brightness-level = <1>; + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; + power-supply = <®_module_3v3>; pwms = <&pwm3 0 5000000>; - enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ status = "disabled"; }; + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel_dpi: panel-dpi { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; @@ -476,7 +522,7 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; - stmpe_touchscreen { + stmpe_ts: stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; @@ -491,9 +537,10 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; + status = "disabled"; }; - stmpe_adc { + stmpe_adc: stmpe_adc { compatible = "st,stmpe-adc"; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; @@ -514,6 +561,10 @@ status = "disabled"; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + /* Colibri PWM */ &pwm1 { pinctrl-names = "default"; From 4e0483652664750dc0c50d3634478fac661bfd7f Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:27 +0200 Subject: [PATCH 369/791] ARM: dts: imx6dl-colibri: Command pmic to standby for poweroff The Colibri iMX6 HW doesn't allow to use the PWR_ON_REQ signal for poweroff. Use the fsl,pmic-stby-poweroff property to command the PMIC into a low power mode in poweroff. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index f6243762e918..da52a71bb6e7 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -138,6 +138,10 @@ status = "disabled"; }; +&clks { + fsl,pmic-stby-poweroff; +}; + /* Colibri SSP */ &ecspi4 { cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; @@ -403,6 +407,7 @@ pmic: pfuze100@8 { compatible = "fsl,pfuze100"; + fsl,pmic-stby-poweroff; reg = <0x08>; regulators { From bccf73ecd098570e98177e654371542667e32cd8 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:28 +0200 Subject: [PATCH 370/791] ARM: dts: imx6dl-colibri: Add additional pingroups The Toradex board Iris V2 has an LVDS transceiver which is configured with 4 signals. Add corresponding pins into the separate pingroup to be able to manage the transceiver. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 52 ++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index da52a71bb6e7..3459bfb5c60b 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -700,6 +700,30 @@ >; }; + /* CSI pins used as GPIOs */ + pinctrl_csi_gpio_1: csigpio1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_csi_gpio_2: csigpio2grp { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + >; + }; + pinctrl_ecspi4: ecspi4grp { fsl,pins = < MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 @@ -739,6 +763,25 @@ >; }; + pinctrl_gpio_1: gpio1grp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; + pinctrl_gpio_2: gpio2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + pinctrl_gpio_bl_on: gpioblon { fsl,pins = < MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 @@ -832,6 +875,15 @@ >; }; + pinctrl_lvds_transceiver: lvdstxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ + >; + }; + pinctrl_mic_gnd: gpiomicgnd { fsl,pins = < /* Controls Mic GND, PU or '1' pull Mic GND to GND */ From 1524b27c94a63713fabb53542cca2e23384f79c3 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:29 +0200 Subject: [PATCH 371/791] ARM: dts: imx6dl-colibri: Move common nodes to SoM dtsi The following two nodes define module level functionality, move them from the carrier board dts file to the SoM file. While at it, reorder the properties in the gpio-keys node alphabetical. - gpio-keys defining the wakeup pin - memory node The atmel touchscreen node can be used on any carrier board. Move it from the carrier board to the module-level device tree and keep it disabled. Set the default pinmuxing to the dedicated connector available on newer carrier boards and rename the pinctrl labels specifying the INT/Reset signal to a common pattern. pinctrl_atmel_conn - uses 107/106 pins as used on dedicated connector pinctrl_atmel_adap - uses 28/30 pins as used with jumper wires Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 49 ------------------ arch/arm/boot/dts/imx6qdl-colibri.dtsi | 53 ++++++++++++++++++++ 2 files changed, 53 insertions(+), 49 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 535b5c156229..dff2d35e693b 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -17,12 +17,6 @@ compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", "fsl,imx6dl"; - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - aliases { i2c0 = &i2c2; i2c1 = &i2c3; @@ -44,20 +38,6 @@ clock-frequency = <16000000>; clock-output-names = "clk16m"; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; }; /* Colibri SSP */ @@ -81,21 +61,6 @@ &i2c3 { status = "okay"; - /* - * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcap_1>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ - status = "disabled"; - }; - /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { compatible = "st,m41t0"; @@ -111,20 +76,6 @@ &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 >; - - pinctrl_pcap_1: pcap1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ - >; - }; - - pinctrl_mxt_ts: mxttsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ - >; - }; }; &pwm1 { diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 3459bfb5c60b..1c49fd3e6286 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -23,6 +23,20 @@ status = "disabled"; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; @@ -50,6 +64,12 @@ }; }; + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + panel_dpi: panel-dpi { /* * edt,et057090dhu: EDT 5.7" LCD TFT @@ -564,6 +584,17 @@ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; + + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; }; &ipu1_di0_disp0 { @@ -682,6 +713,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh_oc_1>; + /* Atmel MXT touchsceen + Capacitive Touch Adapter */ + /* NOTE: This pin group conflicts with pin groups + * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. + */ + pinctrl_atmel_adap: atmeladaptergrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ + >; + }; + + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and + * pinctrl_weim_cs2. Don't use them simultaneously. + */ + pinctrl_atmel_conn: atmelconnectorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 From 965f2ca42cbd59053f93d67587c4055e994680c4 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:30 +0200 Subject: [PATCH 372/791] ARM: dts: imx6dl-colibri: Cleanup - Sort pinctrl nodes alphabetically - End all pinctrl node names in grp and avoid using dashes - Change pinctrl_usbc_id_1's node name to not use underscores - Change the pmic's node name to pmic@8 per binding requirement - Add sound-dai-cells to the codec node per binding requirement Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 384 ++++++++++--------- 2 files changed, 194 insertions(+), 192 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index dff2d35e693b..7272edd85a49 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -46,10 +46,10 @@ mcp251x0: mcp251x@0 { compatible = "microchip,mcp2515"; - reg = <0>; clocks = <&clk16m>; interrupt-parent = <&gpio3>; interrupts = <27 0x2>; + reg = <0>; spi-max-frequency = <10000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 1c49fd3e6286..1c3c34bbfe98 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -104,36 +104,36 @@ reg_usb_host_vbus: regulator-usb-host-vbus { compatible = "regulator-fixed"; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus"; status = "disabled"; }; sound { compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6dl-colibri-sgtl5000"; - ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HP_OUT", "LINE_IN", "Line In Jack", "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias"; + model = "imx6dl-colibri-sgtl5000"; mux-int-port = <1>; mux-ext-port = <5>; + ssi-controller = <&ssi1>; }; /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ sound_spdif: sound-spdif { compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; spdif-out; + model = "imx-spdif"; status = "disabled"; }; }; @@ -171,10 +171,10 @@ }; &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; phy-handle = <ðphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; status = "okay"; mdio { @@ -425,61 +425,61 @@ sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; fsl,pmic-stby-poweroff; reg = <0x08>; regulators { sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <400000>; }; swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5150000>; + regulator-min-microvolt = <5000000>; }; snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1000000>; }; vref_reg: vrefddr { - regulator-boot-on; regulator-always-on; + regulator-boot-on; }; /* vgen1: unused */ vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; }; /* @@ -487,57 +487,58 @@ * the i.MX 6 NVCC_SD1. */ vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; }; vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; }; }; codec: sgtl5000@a { compatible = "fsl,sgtl5000"; - reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; + lrclk-strength = <3>; + reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; VDDD-supply = <&vgen4_reg>; - lrclk-strength = <3>; }; /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; + blocks = <0x5>; interrupts = <20 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio6>; interrupt-controller; id = <0>; - blocks = <0x5>; irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + reg = <0x41>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 12-bit ADC */ @@ -643,27 +644,27 @@ /* Colibri UART_A */ &uart1 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; /* Colibri UART_B */ &uart2 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; /* Colibri UART_C */ &uart3 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_dte>; - fsl,dte-mode; status = "disabled"; }; @@ -675,27 +676,27 @@ /* Colibri MMC */ &usdhc1 { + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + bus-width = <4>; + no-1-8-v; + disable-wp; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ - disable-wp; vmmc-supply = <®_module_3v3>; vqmmc-supply = <&vgen3_reg>; - bus-width = <4>; - no-1-8-v; status = "disabled"; }; /* eMMC */ &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; status = "okay"; }; @@ -737,12 +738,12 @@ pinctrl_audmux: audmuxgrp { fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 >; }; @@ -779,26 +780,26 @@ pinctrl_ecspi4: ecspi4grp { fsl,pins = < + /* SPI CS */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - /* SPI CS */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 >; }; pinctrl_enet: enetgrp { fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) >; }; @@ -835,13 +836,13 @@ >; }; - pinctrl_gpio_bl_on: gpioblon { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 >; }; - pinctrl_gpio_keys: gpiokeys { + pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = < MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 >; @@ -856,15 +857,15 @@ pinctrl_i2c2: i2c2grp { fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 >; }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 >; }; @@ -896,8 +897,8 @@ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 /* Disable PWM pins on camera interface */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 >; }; @@ -937,14 +938,14 @@ >; }; - pinctrl_mic_gnd: gpiomicgnd { + pinctrl_mic_gnd: micgndgrp { fsl,pins = < /* Controls Mic GND, PU or '1' pull Mic GND to GND */ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 >; }; - pinctrl_mmc_cd: gpiommccd { + pinctrl_mmc_cd: mmccdgrp { fsl,pins = < MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; @@ -958,15 +959,15 @@ pinctrl_pwm2: pwm2grp { fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 >; }; pinctrl_pwm3: pwm3grp { fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 >; }; @@ -983,13 +984,6 @@ >; }; - pinctrl_usbh_oc_1: usbhoc1grp { - fsl,pins = < - /* USBH_OC */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 - >; - }; - pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 @@ -1032,9 +1026,9 @@ pinctrl_uart2_dte: uart2dtegrp { fsl,pins = < MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 >; }; @@ -1049,20 +1043,27 @@ fsl,pins = < /* USBC_DET */ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* USBC_DET_EN */ - MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 /* USBC_DET_OVERWRITE */ MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 + /* USBC_DET_EN */ + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 >; }; - pinctrl_usbc_id_1: usbc_id-1 { + pinctrl_usbc_id_1: usbcid1grp { fsl,pins = < /* USBC_ID */ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 >; }; + pinctrl_usbh_oc_1: usbhoc1grp { + fsl,pins = < + /* USBH_OC */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 @@ -1074,7 +1075,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 @@ -1085,7 +1086,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 @@ -1134,13 +1135,93 @@ >; }; + /* ADDRESS[16:18] [25] used as GPIO */ + pinctrl_weim_gpio_1: weimgpio1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* ADDRESS[19:24] used as GPIO */ + pinctrl_weim_gpio_2: weimgpio2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* DATA[16:31] used as GPIO */ + pinctrl_weim_gpio_3: weimgpio3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + >; + }; + + /* DQM[0:3] used as GPIO */ + pinctrl_weim_gpio_4: weimgpio4grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + >; + }; + + /* RDY used as GPIO */ + pinctrl_weim_gpio_5: weimgpio5grp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + /* ADDRESS[16] DATA[30] used as GPIO */ + pinctrl_weim_gpio_6: weimgpio6grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_weim_npwe: weimnpwegrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 + >; + }; + pinctrl_weim_sram: weimsramgrp { fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 /* Data */ - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 @@ -1155,114 +1236,35 @@ MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 /* Address */ - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + /* Ctrl */ + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 >; }; - pinctrl_weim_rdnwr: weimrdnwr { + pinctrl_weim_rdnwr: weimrdnwrgrp { fsl,pins = < - MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 - >; - }; - - pinctrl_weim_npwe: weimnpwe { - fsl,pins = < - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 - MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 - >; - }; - - /* ADDRESS[16:18] [25] used as GPIO */ - pinctrl_weim_gpio_1: weimgpio-1 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* ADDRESS[19:24] used as GPIO */ - pinctrl_weim_gpio_2: weimgpio-2 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* DATA[16:31] used as GPIO */ - pinctrl_weim_gpio_3: weimgpio-3 { - fsl,pins = < - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - /* DQM[0:3] used as GPIO */ - pinctrl_weim_gpio_4: weimgpio-4 { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - >; - }; - - /* RDY used as GPIO */ - pinctrl_weim_gpio_5: weimgpio-5 { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 - >; - }; - - /* ADDRESS[16] DATA[30] used as GPIO */ - pinctrl_weim_gpio_6: weimgpio-6 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 >; }; }; From 6cc75a081d757857a4803c1139c08837ef535c67 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:31 +0200 Subject: [PATCH 373/791] ARM: dts: imx6dl-colibri: Add usdhc1 sleep pin configuration The Toradex board Iris V2 has a SD-card slot with switchable power. Add a pinctrl sleep used when the card power is off to avoid backfeeding to the card and add the "sleep" pinctrl to the usdhc1 controller. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 1c3c34bbfe98..c383e0e4110c 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -680,10 +680,11 @@ bus-width = <4>; no-1-8-v; disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; vmmc-supply = <®_module_3v3>; vqmmc-supply = <&vgen3_reg>; status = "disabled"; @@ -951,6 +952,12 @@ >; }; + pinctrl_mmc_cd_sleep: mmccdslpgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 @@ -1097,6 +1104,18 @@ >; }; + /* avoid backfeeding with removed card power */ + pinctrl_usdhc1_sleep: usdhc1sleepgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 From 1b6e37fe919fe5174ed0f49b4bd51dd2c663a025 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:32 +0200 Subject: [PATCH 374/791] ARM: dts: imx6dl-colibri: Add support for Toradex Iris carrier boards Add support for Toradex Iris, small form-factor Pico-ITX Colibri Arm Computer Module family Carrier Board. Additional details available at https://www.toradex.com/products/carrier-board/iris-carrier-board Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts | 46 ++++++ arch/arm/boot/dts/imx6dl-colibri-iris.dts | 152 +++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6dl-colibri-iris.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ae3cac8e653b..cb4cf5453a9f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -459,6 +459,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts new file mode 100644 index 000000000000..3a6d3889760d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>; + + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + cap-power-off-card; + /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */ + /* /delete-property/ no-1-8-v; */ + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts new file mode 100644 index 000000000000..cf77d894f6d7 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris Board"; + compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>; + + /* + * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one + * wants to turn the transceiver off, that property has to be deleted + * and the gpio handled in userspace. + * The same applies to uart-b-c-on-x14-enable where the UART_B and + * UART_C transceiver is turned on. + */ + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; + + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_gpio_iris + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + >; + + pinctrl_gpio_iris: gpioirisgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1_forceoff: uart1forceoffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_uart23_forceoff: uart23forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; From e66f62acc42d8f7a938b6f92e1feb065f2bb63cb Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:33 +0200 Subject: [PATCH 375/791] ARM: dts: imx6dl-colibri: Add support for Toradex Aster carrier board Add support for Toradex Aster, small form-factor with header compatible with Arduino Uno and Raspberry Pi (RPi) maker boards. Additional detail available at https://www.toradex.com/products/carrier-boards/aster-carrier-board Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-colibri-aster.dts | 113 +++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-colibri-aster.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cb4cf5453a9f..f0e5fc7e5274 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -458,6 +458,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ imx6dl-colibri-eval-v3.dtb \ imx6dl-colibri-iris.dtb \ imx6dl-colibri-iris-v2.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts new file mode 100644 index 000000000000..74e8a6cd8bed --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Aster Board"; + compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + cs-gpios = < + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 4 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>; + status = "okay"; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_csi_gpio_1 + &pinctrl_gpio_2 + &pinctrl_gpio_aster + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + &pinctrl_weim_gpio_5 + >; + + pinctrl_gpio_aster: gpioaster { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; From 8ba8560d4ff1b1b2000aaed5500c56bfd3dfd69c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 4 Apr 2022 17:35:32 +0200 Subject: [PATCH 376/791] arm64: dts: renesas: r8a779f0: Add GPIO nodes Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that GPIO blocks 4-7 are not added, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index eaea28cc5ffb..df46fb87cffc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -76,6 +76,66 @@ <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; }; + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6051180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 17>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6051980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 19>; + interrupt-controller; + #interrupt-cells = <2>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; From aa70cbda745d5d2085f2847b875d0da3173a9032 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Apr 2022 14:32:44 +0200 Subject: [PATCH 377/791] ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer node "make dtbs_check": arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt.yaml: timer: compatible: 'oneOf' conditional failed, one must be fixed: ['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long 'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv7-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv8-timer'] From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml The Cortex-A7 timer should just declare compatibility with "arm,armv7-timer". Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a8e0cf00a983b4c539cdb1cfad5cc6b10b423c5b.1649680220.git.geert+renesas@glider.be --- arch/arm/boot/dts/r9a06g032.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 636a6ab31c58..2257706ce84f 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -214,8 +214,7 @@ }; timer { - compatible = "arm,cortex-a7-timer", - "arm,armv7-timer"; + compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; arm,cpu-registers-not-fw-configured; always-on; From 65b96377bf9130617ced41f317f3ec387d3e0dc3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:03:57 +0200 Subject: [PATCH 378/791] arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 8bd6d7e8a474..6b3057a09251 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1045,8 +1045,8 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0 - 0 0>; + freq-table-hz = <0 0>, + <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 636c8817df7e..3125c3869c69 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -671,8 +671,8 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0 - 0 0>; + freq-table-hz = <0 0>, + <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; From efaa952f95929554c677d6d236d8641e93aa0bc2 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Fri, 11 Mar 2022 13:14:48 +0100 Subject: [PATCH 379/791] ARM: dts: stm32: fix pinctrl node name warnings (MCU soc) The recent addition pinctrl.yaml in commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml") resulted in some node name warnings. Fix the node names to the preferred 'pinctrl'. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 2 +- arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 2 +- arch/arm/boot/dts/stm32h743.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 155d9ffacc83..500bcc302d42 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -45,7 +45,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index 1cf8a23c2644..8f37aefa7315 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 6e42ca2dada2..91dde07a38ba 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -583,7 +583,7 @@ status = "disabled"; }; - pinctrl: pin-controller@58020000 { + pinctrl: pinctrl@58020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; From 42da167bbd2910e4ac6334174f6dc273e079fb91 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Fri, 11 Mar 2022 13:13:23 +0100 Subject: [PATCH 380/791] ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) The recent addition pinctrl.yaml in commit c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml") resulted in some node name warnings. Fix the node names to the preferred 'pinctrl'. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 +- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 1708c79b5254..294c4aec3342 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -239,7 +239,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index f9aa9af31efd..7fdc324b3cf9 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1623,7 +1623,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; @@ -1754,7 +1754,7 @@ }; }; - pinctrl_z: pin-controller-z@54004000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; From ef2d90708883f4025a801feb0ba8411a7a4387e1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 25 Mar 2022 18:58:51 +0100 Subject: [PATCH 381/791] ARM: dts: stm32: Fix PHY post-reset delay on Avenger96 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per KSZ9031RNX PHY datasheet FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2: After the de-assertion of reset, wait a minimum of 100 μs before starting programming on the MIIM (MDC/MDIO) interface. Add 1ms post-reset delay to guarantee this figure. Fixes: 010ca9fe500bf ("ARM: dts: stm32: Add missing ethernet PHY reset on AV96") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 61e17f44ce81..76c54b006d87 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -141,6 +141,7 @@ compatible = "snps,dwmac-mdio"; reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; reset-delay-us = <1000>; + reset-post-delay-us = <1000>; phy0: ethernet-phy@7 { reg = <7>; From cc2b6b6fa4ced56faaf5bc7ad2e26fee08bfd1f7 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Thu, 7 Apr 2022 18:20:41 +0200 Subject: [PATCH 382/791] ARM: dts: stm32: add RTC node on stm32mp131 Add RTC node with compatible, clock, and interrupt properties on stm32mp131. Add clk_rtc_k fixed clock for RTC. Signed-off-by: Gabriel Fernandez Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 294c4aec3342..58647396704f 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -75,6 +75,12 @@ compatible = "fixed-clock"; clock-frequency = <99000000>; }; + + clk_rtc_k: clk-rtc-k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; }; intc: interrupt-controller@a0021000 { @@ -218,6 +224,15 @@ status = "disabled"; }; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>, <&clk_rtc_k>; + clock-names = "pclk", "rtc_ck"; + status = "disabled"; + }; + bsec: efuse@5c005000 { compatible = "st,stm32mp15-bsec"; reg = <0x5c005000 0x400>; From 448fb6ea127ce64efca1d91bef61e587583c2afe Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Thu, 7 Apr 2022 18:20:42 +0200 Subject: [PATCH 383/791] ARM: dts: stm32: enable RTC support on stm32mp135f-dk Enables the support of RTC on stm32mp135f-dk board. Signed-off-by: Gabriel Fernandez Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index ee100d108ea2..aefa25ee897d 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -37,6 +37,10 @@ status = "okay"; }; +&rtc { + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; From 368cfcbaa3bf7a8c482f596a131dea4befeba10a Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Mon, 11 Apr 2022 09:21:52 +0200 Subject: [PATCH 384/791] dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks Add definitions of four clocks which need to be manipulated in order to initialize the AHB bus which exposes the SCC block in the global address space. Signed-off-by: Michael Srba Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411072156.24451-2-michael.srba@seznam.cz --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 72c99e486d86..1badb4f9c58f 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -186,6 +186,10 @@ #define UFS_UNIPRO_CORE_CLK_SRC 177 #define GCC_MMSS_GPLL0_CLK 178 #define HMSS_GPLL0_CLK_SRC 179 +#define GCC_IM_SLEEP 180 +#define AGGRE2_SNOC_NORTH_AXI 181 +#define SSC_XO 182 +#define SSC_CNOC_AHBS_CLK 183 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 From 1ed29355df221407370933522a94dc8a0f47eb35 Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Mon, 11 Apr 2022 09:21:56 +0200 Subject: [PATCH 385/791] arm64: dts: qcom: msm8998: reserve potentially inaccessible clocks With the gcc driver now being more complete and describing clocks which might not always be write-accessible to the OS, conservatively specify all such clocks as protected in the SoC dts. The board dts - or even user-supplied dts - can override this property to reflect the actual configuration. Signed-off-by: Michael Srba Reviewed-by: Jeffrey Hugo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411072156.24451-6-michael.srba@seznam.cz --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 2fda21e810c9..4a84de6cee1e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -815,6 +815,21 @@ clock-names = "xo", "sleep_clk"; clocks = <&xo>, <&sleep_clk>; + + /* + * The hypervisor typically configures the memory region where these clocks + * reside as read-only for the HLOS. If the HLOS tried to enable or disable + * these clocks on a device with such configuration (e.g. because they are + * enabled but unused during boot-up), the device will most likely decide + * to reboot. + * In light of that, we are conservative here and we list all such clocks + * as protected. The board dts (or a user-supplied dts) can override the + * list of protected clocks if it differs from the norm, and it is in fact + * desired for the HLOS to manage these clocks + */ + protected-clocks = , + , + ; }; rpm_msg_ram: sram@778000 { From 48995e863307bf08a51362a0aafb10e70bdafb4e Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 11 Apr 2022 02:44:56 +0300 Subject: [PATCH 386/791] arm64: dts: qcom: sm8450: Add thermal sensor controllers The change adds description of two thermal sensor controllers found on SM8450. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410234458.1739279-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 2cfc67b75259..f498951a25f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1364,6 +1364,28 @@ interrupt-controller; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; From fccf8e31ac3d7c3f874ae5d78de495edaf1ead58 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 11 Apr 2022 02:44:57 +0300 Subject: [PATCH 387/791] arm64: dts: qcom: sm8450: Add thermal zones Add thermal zones handled by tsens sensors. The definitions and the trip points were taken from the downstream dts. For the CPU core thermal sensors, the trip points were changed to follow the example of other Qualcomm platforms. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410234458.1739279-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 843 +++++++++++++++++++++++++++ 1 file changed, 843 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f498951a25f8..82083b16e4c1 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -47,6 +48,7 @@ power-domains = <&CPU_PD0>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -65,6 +67,7 @@ power-domains = <&CPU_PD1>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -80,6 +83,7 @@ power-domains = <&CPU_PD2>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -95,6 +99,7 @@ power-domains = <&CPU_PD3>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -110,6 +115,7 @@ power-domains = <&CPU_PD4>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -125,6 +131,7 @@ power-domains = <&CPU_PD5>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -141,6 +148,7 @@ power-domains = <&CPU_PD6>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -156,6 +164,7 @@ power-domains = <&CPU_PD7>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; + #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -1906,6 +1915,840 @@ }; }; + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu7_middle_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-top-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu0_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-bottom-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu1_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cdsp0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_0_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_1_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_2_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From 568cd3243331b6bf0702665f7bd90baa93e2b3ac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Apr 2022 10:59:32 +0200 Subject: [PATCH 388/791] ARM: dts: qcom: sdx55: do not use underscore in BCM node name Align BCM voter node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411085935.130072-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index d455795da44c..4d45be049613 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -770,7 +770,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; From 97c246c825f73a018169834e56ffa9a89dea37a9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Apr 2022 10:59:33 +0200 Subject: [PATCH 389/791] ARM: dts: qcom: sdx55: remove wrong unit address from RPMH RSC clocks The clock controller of RPMH RSC does not have 'reg' property, so should not have unit address. Fixes: bae2f5979c6e ("ARM: dts: qcom: Add SDX65 platform and MTP board support") Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411085935.130072-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 210e55c0fb5f..df6f9d6288fe 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -343,7 +343,7 @@ , ; - rpmhcc: clock-controller@1 { + rpmhcc: clock-controller { compatible = "qcom,sdx65-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; From fc0e7dd6d2e2c9f8b2c6497a190ee29d8f3aef3a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Apr 2022 10:59:34 +0200 Subject: [PATCH 390/791] arm64: dts: qcom: do not use underscore in BCM node name Align BCM voter node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411085935.130072-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e1c46b80f14a..86175d257b1e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3522,7 +3522,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 6c6112427ef9..fb1a0f662575 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1450,7 +1450,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f0c550155d03..2700a8145cb9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4072,7 +4072,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 33ea5ed4c0f5..13f57c8e2f1c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4654,7 +4654,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e70687d6c2da..abdbfd456d2f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1881,7 +1881,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; From efbd3599154cb3d947564a9dce419a6754d233ef Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:02 +0530 Subject: [PATCH 391/791] arm64: dts: qcom: sdm845-xiaomi-beryllium: change firmware path and use mbn format The "qcom/sdm845/" path conflicts with db845c's firmware that are present in the linux-firmware package. Xiaomi uses their own signed firmware for Poco F1 and can't use the db845c's firmware. So let's use "qcom/sdm845/beryllium/" to distinguish Poco F1's firmware files. For easier handling and packaging, the mdt+bXX files are squashed using Bjorn Andersson's pil-squasher tool from this link: https://github.com/andersson/pil-squasher Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB700966DEE6F6044EBEB5B892D91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 367389526b41..27ba9ad1ad02 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -121,7 +121,7 @@ &adsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/adsp.mdt"; + firmware-name = "qcom/sdm845/beryllium/adsp.mbn"; }; &apps_rsc { @@ -208,7 +208,7 @@ &cdsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/cdsp.mdt"; + firmware-name = "qcom/sdm845/beryllium/cdsp.mbn"; }; &dsi0 { @@ -262,7 +262,7 @@ zap-shader { memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; + firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; }; }; @@ -289,7 +289,7 @@ &mss_pil { status = "okay"; - firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt"; + firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; }; &pm8998_gpio { From 84b6c2420415767079baa24ffd70d048cd35bdd8 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:03 +0530 Subject: [PATCH 392/791] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable qcom ipa driver Enable Qualcomm IP Accelerator (IPA) driver for mobile data functionality which works by using ModemManager. Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB7009405D7C06C0B480974063D91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 27ba9ad1ad02..801b8c5984a3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -292,6 +292,12 @@ firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; }; +&ipa { + status = "okay"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; +}; + &pm8998_gpio { vol_up_pin_a: vol-up-active { pins = "gpio6"; From 1f1c494082a1f10d03ce4ee1485ee96d212e22ff Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:04 +0530 Subject: [PATCH 393/791] arm64: dts: qcom: sdm845-xiaomi-beryllium: fix typo in panel's vddio-supply property vddio is misspelled with a "0" instead of "o". Fix it. Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB7009901651E6A8D5ACB0425ED91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 801b8c5984a3..f97900e7797b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -218,7 +218,7 @@ panel@0 { compatible = "tianma,fhd-video"; reg = <0>; - vddi0-supply = <&vreg_l14a_1p8>; + vddio-supply = <&vreg_l14a_1p8>; vddpos-supply = <&lab>; vddneg-supply = <&ibb>; From 3213b3741a147db59ed6f1ebc5f569854725b91f Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:05 +0530 Subject: [PATCH 394/791] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable second wifi channel Like the c630, the Poco F1 is also capable of using both antenna channels for 2.4 and 5ghz wifi, however unlike the c630 only the first channel is used for bluetooth. Similar to Oneplus 6. Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB7009E2566F9000F338432761D91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index f97900e7797b..798fc72578a7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -185,6 +185,12 @@ regulator-initial-mode = ; }; + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + vreg_l24a_3p075: ldo24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; @@ -547,6 +553,7 @@ vdd-1.8-xo-supply = <&vreg_l7a_1p8>; vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ From 89561886191c0dcb6ce1491f14552eac16e14a80 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Fri, 1 Apr 2022 05:48:10 +0530 Subject: [PATCH 395/791] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable qcom wled backlight and link to panel Xiaomi Poco F1 uses the QCOM WLED driver for backlight control. Enable and link it to the panel to use it. Signed-off-by: Joel Selvaraj Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB70092607CD7CDD8CF8BCD464D9E09@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 798fc72578a7..d88dc07205f7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -231,6 +231,7 @@ #address-cells = <1>; #size-cells = <0>; + backlight = <&pmi8998_wled>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; port { @@ -314,6 +315,17 @@ }; }; +&pmi8998_wled { + status = "okay"; + qcom,current-boost-limit = <970>; + qcom,ovp-millivolt = <29600>; + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; + qcom,switching-freq = <600>; + qcom,external-pfet; + qcom,cabc; +}; + &pm8998_pon { resin { compatible = "qcom,pm8941-resin"; From c46e3c4bdfaca1595b898bb58b112fd683fe0c11 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 2 Apr 2022 21:28:58 +0200 Subject: [PATCH 396/791] arm64: dts: qcom: msm8994: override nodes by label Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220402192859.154977-1-krzysztof.kozlowski@linaro.org --- .../dts/qcom/msm8994-huawei-angler-rev-101.dts | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 6e43e4339f55..dbfbb77e9ff5 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -27,15 +27,13 @@ chosen { stdout-path = "serial0:115200n8"; }; +}; - soc { - serial@f991e000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; +&blsp1_uart2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; }; &tlmm { From 2a80a66f68e37ce19dee7fdb3d3e946859712b53 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 2 Apr 2022 21:28:59 +0200 Subject: [PATCH 397/791] arm64: dts: qcom: msm8996: override nodes by label Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220402192859.154977-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 6a1699a96c99..596ad4c896f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -18,12 +18,10 @@ chosen { stdout-path = "serial0"; }; +}; - soc { - serial@75b0000 { - status = "okay"; - }; - }; +&blsp2_uart2 { + status = "okay"; }; &hdmi { From 97276cbfb4fbe33c3ab8b5f5277a73c0b5f3732b Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Tue, 12 Apr 2022 00:46:54 +0530 Subject: [PATCH 398/791] arm64: dts: qcom: sc7280: Add wakeup-source property for USB node Adding wakeup-source property for USB controller in SC7280. This property is added to inform that the USB controller is wake up capable and to conditionally power down the phy during system suspend. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649704614-31518-7-git-send-email-quic_c_sanm@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 9ece35736515..00bacc4ae4f7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3106,6 +3106,7 @@ phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; + wakeup-source; }; }; From bc08fbf49bc87e7613717e41674303905a9934fc Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 12 Apr 2022 14:51:35 -0700 Subject: [PATCH 399/791] arm64: dts: qcom: sm8350: Define GPI DMA engines The Qualcomm SM8350 has three GPI DMA engines, add definitions for these. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220412215137.2385831-1-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index abdbfd456d2f..f60e35d7fe08 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -675,6 +676,28 @@ }; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0xff>; + iommus = <&apps_smmu 0x5f6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -840,12 +863,37 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x09800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x5b6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; @@ -1078,12 +1126,37 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0xff>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; From ddc97e7d1765cb2bf6089e211dae8e0b63cb3892 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 12 Apr 2022 14:51:36 -0700 Subject: [PATCH 400/791] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220412215137.2385831-2-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 108 +++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index f60e35d7fe08..c0137bdcf94b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -718,6 +718,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -731,6 +734,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -744,6 +750,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -757,6 +766,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -770,6 +782,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -783,6 +798,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -796,6 +814,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -809,6 +830,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -824,6 +848,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -850,6 +877,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -914,6 +944,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -927,6 +960,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -940,6 +976,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -953,6 +992,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -966,6 +1008,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -979,6 +1024,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1009,6 +1057,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1022,6 +1073,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1035,6 +1089,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1048,6 +1105,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1061,6 +1121,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1074,6 +1137,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1087,6 +1153,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1113,6 +1182,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1177,6 +1249,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1190,6 +1265,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1203,6 +1281,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1216,6 +1297,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1229,6 +1313,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1242,6 +1329,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1255,6 +1345,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1268,6 +1361,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1281,6 +1377,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1294,6 +1393,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1307,6 +1409,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1320,6 +1425,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 83b8347a858d06f7d070663cc3898215d3d299a0 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 12 Apr 2022 14:51:37 -0700 Subject: [PATCH 401/791] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 Some versions of the firmware for the SM8350 Hardware Development Kit (HDK) has FIFO mode disabled for i2c13 and must thus use GPI DMA. Enable &gpi_dma1 to allow this. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220412215137.2385831-3-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 1e5e9405d8b1..0fcf5bd88fc7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -213,6 +213,10 @@ firmware-name = "qcom/sm8350/cdsp.mbn"; }; +&gpi_dma1 { + status = "okay"; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm8350/modem.mbn"; From b9c8433083097327cad19fbf633fb0735a008315 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:24 +0530 Subject: [PATCH 402/791] arm64: dts: qcom: sm8450: Add gpi_dma nodes GPI DMA can be used for DMA operations for QUP devices, so add the three gpi_dma insances found in this SoC Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 67 ++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 82083b16e4c1..8f1d07ab6163 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -702,6 +703,50 @@ "sleep_clk"; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8450-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x496 0x0>; + status = "disabled"; + }; + + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8450-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x900000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x5b6 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x2000>; @@ -727,6 +772,28 @@ }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8450-gpi-dma"; + #dma-cells = <3>; + reg = <0 0xa00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x56 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; From 488922c1a372579bf2caf40933e7459e3c86276f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:25 +0530 Subject: [PATCH 403/791] arm64: dts: qcom: sm8450: Fix missing iommus for qup qupv3_id_0 was missing iommus property which cause any dma transaction to fail and board crash. So add the missing iommus. While at it also add interconnect nodes for qup Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-3-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8f1d07ab6163..7b079afffe8f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -753,6 +753,9 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; + interconnect-names = "qup-core"; #address-cells = <2>; #size-cells = <2>; ranges; From a84e88e9a00334f1468a9f69a77091dbe80b7a3b Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:26 +0530 Subject: [PATCH 404/791] arm64: dts: qcom: sm8450: Add qup nodes for qup0 qup0 has 7 SEs, with SE7 as uart and already added, so add the remaining 6 SEs (i2c and spi) along with pinconf for these SEs Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-4-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 412 +++++++++++++++++++++++++++ 1 file changed, 412 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7b079afffe8f..1b11c16b241c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -343,6 +343,25 @@ }; }; + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -761,6 +780,292 @@ ranges; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00980000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00980000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + power-domains = <&rpmhpd SM8450_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00988000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00988000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00990000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00990000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + power-domains = <&rpmhpd SM8450_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00994000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00994000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x998000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x998000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart7: serial@99c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x0099c000 0 0x4000>; @@ -1541,6 +1846,41 @@ }; }; + qup_i2c0_data_clk: qup-i2c0-data-clk { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk { + pins = "gpio4", "gpio5"; + function = "qup1"; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk { + pins = "gpio8", "gpio9"; + function = "qup2"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk { + pins = "gpio12", "gpio13"; + function = "qup3"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk { + pins = "gpio16", "gpio17"; + function = "qup4"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk { + pins = "gpio206", "gpio207"; + function = "qup5"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk { + pins = "gpio20", "gpio21"; + function = "qup6"; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; @@ -1555,6 +1895,78 @@ bias-pull-up; }; + qup_spi0_cs: qup-spi0-cs { + pins = "gpio3"; + function = "qup0"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0"; + }; + + qup_spi1_cs: qup-spi1-cs { + pins = "gpio7"; + function = "qup1"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk { + pins = "gpio4", "gpio5", "gpio6"; + function = "qup1"; + }; + + qup_spi2_cs: qup-spi2-cs { + pins = "gpio11"; + function = "qup2"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk { + pins = "gpio8", "gpio9", "gpio10"; + function = "qup2"; + }; + + qup_spi3_cs: qup-spi3-cs { + pins = "gpio15"; + function = "qup3"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk { + pins = "gpio12", "gpio13", "gpio14"; + function = "qup3"; + }; + + qup_spi4_cs: qup-spi4-cs { + pins = "gpio19"; + function = "qup4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk { + pins = "gpio16", "gpio17", "gpio18"; + function = "qup4"; + }; + + qup_spi5_cs: qup-spi5-cs { + pins = "gpio85"; + function = "qup5"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk { + pins = "gpio206", "gpio207", "gpio84"; + function = "qup5"; + }; + + qup_spi6_cs: qup-spi6-cs { + pins = "gpio23"; + function = "qup6"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk { + pins = "gpio20", "gpio21", "gpio22"; + function = "qup6"; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; From 1a380216fd6fcf7135b2b413bb9431fc98e2fa23 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:27 +0530 Subject: [PATCH 405/791] arm64: dts: qcom: sm8450: Add qup nodes for qup1 qup1 has 7 SEs, I2C13 and I2C14 were already added so added the remaining SEs (i2c and spi) along with pinconf for these SEs Also add interconnect properties for I2C13 and I2C14 Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-5-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 359 +++++++++++++++++++++++++++ 1 file changed, 359 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1b11c16b241c..a39949f5329d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1113,6 +1113,206 @@ ranges; status = "disabled"; + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; @@ -1121,6 +1321,33 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_data_clk>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1134,6 +1361,33 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_data_clk>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1881,6 +2135,31 @@ function = "qup6"; }; + qup_i2c8_data_clk: qup-i2c8-data-clk { + pins = "gpio28", "gpio29"; + function = "qup8"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk { + pins = "gpio32", "gpio33"; + function = "qup9"; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk { + pins = "gpio36", "gpio37"; + function = "qup10"; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk { + pins = "gpio40", "gpio41"; + function = "qup11"; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk { + pins = "gpio44", "gpio45"; + function = "qup12"; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; @@ -1967,6 +2246,86 @@ function = "qup6"; }; + qup_spi8_cs: qup-spi8-cs { + pins = "gpio31"; + function = "qup8"; + }; + + qup_spi8_data_clk: qup-spi8-data-clk { + pins = "gpio28", "gpio29", "gpio30"; + function = "qup8"; + }; + + qup_spi9_cs: qup-spi9-cs { + pins = "gpio35"; + function = "qup9"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk { + pins = "gpio32", "gpio33", "gpio34"; + function = "qup9"; + }; + + qup_spi10_cs: qup-spi10-cs { + pins = "gpio39"; + function = "qup10"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk { + pins = "gpio36", "gpio37", "gpio38"; + function = "qup10"; + }; + + qup_spi11_cs: qup-spi11-cs { + pins = "gpio43"; + function = "qup11"; + }; + + qup_spi11_data_clk: qup-spi11-data-clk { + pins = "gpio40", "gpio41", "gpio42"; + function = "qup11"; + }; + + qup_spi12_cs: qup-spi12-cs { + pins = "gpio47"; + function = "qup12"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk { + pins = "gpio44", "gpio45", "gpio46"; + function = "qup12"; + }; + + qup_spi13_cs: qup-spi13-cs { + pins = "gpio51"; + function = "qup13"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk { + pins = "gpio48", "gpio49", "gpio50"; + function = "qup13"; + }; + + qup_spi14_cs: qup-spi14-cs { + pins = "gpio55"; + function = "qup14"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk { + pins = "gpio52", "gpio53", "gpio54"; + function = "qup14"; + }; + + qup_spi15_cs: qup-spi15-cs { + pins = "gpio59"; + function = "qup15"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk { + pins = "gpio56", "gpio57", "gpio58"; + function = "qup15"; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; From ba640cd31342b45dcf2f95f6ca7dcbc46629919f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:28 +0530 Subject: [PATCH 406/791] arm64: dts: qcom: sm8450: Add qup nodes for qup2 qup2 has 7 SEs, so add the SEs (i2c and spi) along with pinconf for these SEs Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-6-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 396 +++++++++++++++++++++++++++ 1 file changed, 396 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a39949f5329d..e2d55c3b12d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -744,6 +744,299 @@ status = "disabled"; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x483 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c15: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi15: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c16: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c16_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi16: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c17: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c17_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi17: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c18: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c18_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi18: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c19: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c19_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi19: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c20: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c20_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi20: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c21: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c21_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi21: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + gpi_dma0: dma-controller@900000 { compatible = "qcom,sm8450-gpi-dma"; #dma-cells = <3>; @@ -2174,6 +2467,41 @@ bias-pull-up; }; + qup_i2c15_data_clk: qup-i2c15-data-clk { + pins = "gpio56", "gpio57"; + function = "qup15"; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk { + pins = "gpio60", "gpio61"; + function = "qup16"; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk { + pins = "gpio64", "gpio65"; + function = "qup17"; + }; + + qup_i2c18_data_clk: qup-i2c18-data-clk { + pins = "gpio68", "gpio69"; + function = "qup18"; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk { + pins = "gpio72", "gpio73"; + function = "qup19"; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk { + pins = "gpio76", "gpio77"; + function = "qup20"; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk { + pins = "gpio80", "gpio81"; + function = "qup21"; + }; + qup_spi0_cs: qup-spi0-cs { pins = "gpio3"; function = "qup0"; @@ -2326,6 +2654,74 @@ function = "qup15"; }; + qup_spi16_cs: qup-spi16-cs { + pins = "gpio63"; + function = "qup16"; + }; + + qup_spi16_data_clk: qup-spi16-data-clk { + pins = "gpio60", "gpio61", "gpio62"; + function = "qup16"; + }; + + qup_spi17_cs: qup-spi17-cs { + pins = "gpio67"; + function = "qup17"; + }; + + qup_spi17_data_clk: qup-spi17-data-clk { + pins = "gpio64", "gpio65", "gpio66"; + function = "qup17"; + }; + + qup_spi18_cs: qup-spi18-cs { + pins = "gpio71"; + function = "qup18"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_data_clk: qup-spi18-data-clk { + pins = "gpio68", "gpio69", "gpio70"; + function = "qup18"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs { + pins = "gpio75"; + function = "qup19"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk { + pins = "gpio72", "gpio73", "gpio74"; + function = "qup19"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs { + pins = "gpio79"; + function = "qup20"; + }; + + qup_spi20_data_clk: qup-spi20-data-clk { + pins = "gpio76", "gpio77", "gpio78"; + function = "qup20"; + }; + + qup_spi21_cs: qup-spi21-cs { + pins = "gpio83"; + function = "qup21"; + }; + + qup_spi21_data_clk: qup-spi21-data-clk { + pins = "gpio80", "gpio81", "gpio82"; + function = "qup21"; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; From 67ebdc6dd1e2049fd9620f0572bc81a809afbe24 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:29 +0530 Subject: [PATCH 407/791] arm64: dts: qcom: sm8450: Fix missing iommus for qup1 qupv3_id_1 was missing iommus property which cause any dma transaction to fail and board crash. So add the missing iommus. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-7-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e2d55c3b12d2..764e4be756db 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1401,6 +1401,9 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; + interconnect-names = "qup-core"; #address-cells = <2>; #size-cells = <2>; ranges; From d953239726e971ecaee45d86b4bcd605be839b2a Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:30 +0530 Subject: [PATCH 408/791] arm64: dts: qcom: sm8450-qrd: Enable spi and i2c nodes Enable the i2c5, spi4, spi18 and spi19 nodes which were tested on qrd board along with related qup nodes and gpi_dma0 Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-8-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index d33e86a375c0..236e53974fdd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -352,10 +352,22 @@ vdda-pll-supply = <&vreg_l6b_1p2>; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; @@ -376,6 +388,18 @@ firmware-name = "qcom/sm8450/slpi.mbn"; }; +&spi4 { + status = "okay"; +}; + +&spi18 { + status = "okay"; +}; + +&spi19 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; }; From ca79a997f2c0826ccf7d313068de3d04d5e8c82b Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 15 Apr 2022 17:46:53 +0100 Subject: [PATCH 409/791] arm64: dts: qcom: sm8250: Add camcc DT node Add the camcc DT node for the Camera Clock Controller on sm8250. Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415164655.1679628-2-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 13f57c8e2f1c..ab75d0f0aa7f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include / { @@ -3149,6 +3150,21 @@ #power-domain-cells = <1>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sm8250-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; From 30325603b910e4ca61d56d20e2f5b9076d371e83 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 15 Apr 2022 17:46:54 +0100 Subject: [PATCH 410/791] arm64: dts: qcom: sm8250: camss: Add CAMSS block definition Adds a CAMSS definition block. Co-developed-by: Julian Grahsl Signed-off-by: Julian Grahsl Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415164655.1679628-3-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 153 +++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index ab75d0f0aa7f..061455bab53a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3150,6 +3150,159 @@ #power-domain-cells = <1>; }; + camss: camss@ac6a000 { + compatible = "qcom,sm8250-camss"; + status = "disabled"; + + reg = <0 0xac6a000 0 0x2000>, + <0 0xac6c000 0 0x2000>, + <0 0xac6e000 0 0x1000>, + <0 0xac70000 0 0x1000>, + <0 0xac72000 0 0x1000>, + <0 0xac74000 0 0x1000>, + <0 0xacb4000 0 0xd000>, + <0 0xacc3000 0 0xd000>, + <0 0xacd9000 0 0x2200>, + <0 0xacdb200 0 0x2200>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csid0", + "csid1", + "csid2", + "csid3", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "cam_ahb_clk", + "cam_hf_axi", + "cam_sf_axi", + "camnoc_axi", + "camnoc_axi_src", + "core_ahb", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "slow_ahb_src", + "vfe0_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe0_areg", + "vfe1_ahb", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe1_areg", + "vfe_lite_ahb", + "vfe_lite_axi", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + iommus = <&apps_smmu 0x800 0x400>, + <&apps_smmu 0x801 0x400>, + <&apps_smmu 0x840 0x400>, + <&apps_smmu 0x841 0x400>, + <&apps_smmu 0xc00 0x400>, + <&apps_smmu 0xc01 0x400>, + <&apps_smmu 0xc40 0x400>, + <&apps_smmu 0xc41 0x400>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "cam_ahb", + "cam_hf_0_mnoc", + "cam_sf_0_mnoc", + "cam_sf_icp_mnoc"; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sm8250-camcc"; reg = <0 0x0ad00000 0 0x10000>; From e7173009e139bc13bf7833ea4185dda4779b95f3 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 15 Apr 2022 17:46:55 +0100 Subject: [PATCH 411/791] arm64: dts: qcom: sm8250: camss: Add CCI definitions sm8250 has two CCI busses with two I2C busses apiece. Co-developed-by: Julian Grahsl Signed-off-by: Julian Grahsl Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415164655.1679628-4-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 162 +++++++++++++++++++++++++++ 1 file changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 061455bab53a..26afaa4f98fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3150,6 +3150,88 @@ #power-domain-cells = <1>; }; + cci0: cci@ac4f000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4f000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac50000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac50000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@ac6a000 { compatible = "qcom,sm8250-camss"; status = "disabled"; @@ -3688,6 +3770,86 @@ gpio-ranges = <&tlmm 0 0 181>; wakeup-parent = <&pdc>; + cci0_default: cci0-default { + cci0_i2c0_default: cci0-i2c0-default { + /* SDA, SCL */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_i2c1_default: cci0-i2c1-default { + /* SDA, SCL */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci0_sleep: cci0-sleep { + cci0_i2c0_sleep: cci0-i2c0-sleep { + /* SDA, SCL */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep { + /* SDA, SCL */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + }; + + cci1_default: cci1-default { + cci1_i2c0_default: cci1-i2c0-default { + /* SDA, SCL */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_i2c1_default: cci1-i2c1-default { + /* SDA, SCL */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci1_sleep: cci1-sleep { + cci1_i2c0_sleep: cci1-i2c0-sleep { + /* SDA, SCL */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + + bias-pull-down; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep { + /* SDA, SCL */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + + bias-pull-down; + drive-strength = <2>; /* 2 mA */ + }; + }; + pri_mi2s_active: pri-mi2s-active { sclk { pins = "gpio138"; From 5d04419045e7ad28155e2f7403599b2fdbd1548f Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Fri, 15 Apr 2022 17:22:41 -0700 Subject: [PATCH 412/791] arm64: dts: qcom: sc7280: Add SAR sensors to herobrine crd Enable the two SAR sensors of the CRD based on herobrine. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415172238.1.I671bdf40fdfce7a35f6349fca0dc56145d4210ee@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index fd6eadc8581a..b06f61e9b90b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -49,6 +49,18 @@ ap_tp_i2c: &i2c0 { }; }; +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&ap_sar_sensor0 { + status = "okay"; +}; + +&ap_sar_sensor1 { + status = "okay"; +}; + ap_ts_pen_1v8: &i2c13 { status = "okay"; clock-frequency = <400000>; From 2c663e5e5bbf2a5b85e0f76ccb69663f583c3e33 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 11 Apr 2022 22:01:38 +0200 Subject: [PATCH 413/791] ARM: dts: bcm2835-rpi-zero-w: Fix GPIO line name for Wifi/BT The GPIOs 30 to 39 are connected to the Cypress CYW43438 (Wifi/BT). So fix the GPIO line names accordingly. Fixes: 2c7c040c73e9 ("ARM: dts: bcm2835: Add Raspberry Pi Zero W") Signed-off-by: Phil Elwell Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 243236bc1e00..8b043ab62dc8 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -74,16 +74,18 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", "CAM_GPIO1", /* GPIO40 */ "WL_ON", /* GPIO41 */ "NC", /* GPIO42 */ From 9fd26fd02749ec964eb0d588a3bab9e09bf77927 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 11 Apr 2022 22:01:39 +0200 Subject: [PATCH 414/791] ARM: dts: bcm2837-rpi-cm3-io3: Fix GPIO line names for SMPS I2C The GPIOs 46 & 47 are already used for a I2C interface to a SMPS. So fix the GPIO line names accordingly. Fixes: a54fe8a6cf66 ("ARM: dts: add Raspberry Pi Compute Module 3 and IO board") Signed-off-by: Phil Elwell Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts index 588d9411ceb6..3dfce4312dfc 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts @@ -63,8 +63,8 @@ "GPIO43", "GPIO44", "GPIO45", - "GPIO46", - "GPIO47", + "SMPS_SCL", + "SMPS_SDA", /* Used by eMMC */ "SD_CLK_R", "SD_CMD_R", From 57f718aa4b93392fb1a8c0a874ab882b9e18136a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 11 Apr 2022 22:01:40 +0200 Subject: [PATCH 415/791] ARM: dts: bcm2837-rpi-3-b-plus: Fix GPIO line name of power LED The red LED on the Raspberry Pi 3 B Plus is the power LED. So fix the GPIO line name accordingly. Fixes: 71c0cd2283f2 ("ARM: dts: bcm2837: Add Raspberry Pi 3 B+") Signed-off-by: Phil Elwell Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index e12938baaf12..c263f5b48b96 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -45,7 +45,7 @@ #gpio-cells = <2>; gpio-line-names = "BT_ON", "WL_ON", - "STATUS_LED_R", + "PWR_LED_R", "LAN_RUN", "", "CAM_GPIO0", From 97bd8659c1c46c23e4daea7e040befca30939950 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 11 Apr 2022 22:01:41 +0200 Subject: [PATCH 416/791] ARM: dts: bcm2835-rpi-b: Fix GPIO line names Recently this has been fixed in the vendor tree, so upstream this. Fixes: 731b26a6ac17 ("ARM: bcm2835: Add names for the Raspberry Pi GPIO lines") Signed-off-by: Phil Elwell Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm2835-rpi-b.dts | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 1b63d6b19750..25d87212cefd 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -53,18 +53,17 @@ "GPIO18", "NC", /* GPIO19 */ "NC", /* GPIO20 */ - "GPIO21", + "CAM_GPIO0", "GPIO22", "GPIO23", "GPIO24", "GPIO25", "NC", /* GPIO26 */ - "CAM_GPIO0", - /* Binary number representing build/revision */ - "CONFIG0", - "CONFIG1", - "CONFIG2", - "CONFIG3", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", "NC", /* GPIO32 */ "NC", /* GPIO33 */ "NC", /* GPIO34 */ From 0b8c9a837cc3588f483f2a03723aa1e3651d8665 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 11 Apr 2022 22:01:42 +0200 Subject: [PATCH 417/791] ARM: dts: bcm283x: Remove gpio line name NC The convention to name not connected GPIOs with NC has never been adapted. Also newer Raspberry Pi boards like RPi 4 never did. So fix this inconsistency by removing all of the NC names. Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 21 +++++++------ arch/arm/boot/dts/bcm2835-rpi-a.dts | 35 +++++++++++----------- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 17 +++++------ arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 35 +++++++++++----------- arch/arm/boot/dts/bcm2835-rpi-b.dts | 35 +++++++++++----------- arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts | 1 - arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 3 +- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 29 +++++++++--------- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 1 - arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 1 - arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 1 - arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 1 - arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts | 1 - arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 12 ++++---- 14 files changed, 90 insertions(+), 103 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 40b9405f1a8e..9b9a18bbb20a 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -32,7 +32,6 @@ * This is based on the unreleased schematic for the Model A+. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -67,21 +66,21 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ + "", /* GPIO30 */ + "", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ + "", /* GPIO33 */ + "", /* GPIO34 */ "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ + "", /* GPIO36 */ + "", /* GPIO37 */ "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 11edb581dbaf..f664e4fced93 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -26,7 +26,6 @@ * RPI00021 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -42,41 +41,41 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ + "", /* GPIO19 */ + "", /* GPIO20 */ "GPIO21", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ + "", /* GPIO26 */ "CAM_GPIO0", /* Binary number representing build/revision */ "CONFIG0", "CONFIG1", "CONFIG2", "CONFIG3", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 1b435c64bd9c..7b7c363e5ee8 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -34,7 +34,6 @@ * RPI-BPLUS sheet 1 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -69,20 +68,20 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ + "", /* GPIO30 */ "LAN_RUN", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ + "", /* GPIO33 */ + "", /* GPIO34 */ "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ + "", /* GPIO36 */ + "", /* GPIO37 */ "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ + "", /* GPIO42 */ + "", /* GPIO43 */ "ETHCLK", /* GPIO44 */ "PWM1_OUT", /* GPIO45 */ "HDMI_HPD_N", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index a23c25c00eea..f5b66d3f4ff3 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -27,7 +27,6 @@ * RPI00022 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -43,40 +42,40 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ + "", /* GPIO19 */ + "", /* GPIO20 */ "CAM_GPIO", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ + "", /* GPIO26 */ "GPIO27", "GPIO28", "GPIO29", "GPIO30", "GPIO31", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 25d87212cefd..f589bede2b11 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -27,7 +27,6 @@ * RPI00021 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -43,40 +42,40 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ + "", /* GPIO19 */ + "", /* GPIO20 */ "CAM_GPIO0", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ + "", /* GPIO26 */ "GPIO27", "GPIO28", "GPIO29", "GPIO30", "GPIO31", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts index a75c882e6575..87958a96c3e0 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts @@ -13,7 +13,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 8b043ab62dc8..596bb1ef994e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -39,7 +39,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -88,7 +87,7 @@ "SD1_DATA3", "CAM_GPIO1", /* GPIO40 */ "WL_ON", /* GPIO41 */ - "NC", /* GPIO42 */ + "", /* GPIO42 */ "WIFI_CLK", /* GPIO43 */ "CAM_GPIO0", /* GPIO44 */ "BT_ON", /* GPIO45 */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 6f9b3a908f28..a65c2bca69ea 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -29,7 +29,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -64,22 +63,22 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ + "", /* GPIO30 */ + "", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "NC", /* GPIO40 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ + "", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "NC", /* GPIO45 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED_N", /* Used by SD Card */ diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index d8af8eeac7b6..c824a2cea02e 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -34,7 +34,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index d73daf5bff1d..f7222a28903e 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -55,7 +55,6 @@ * This is mostly based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index c263f5b48b96..fd4ac6f2d077 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -61,7 +61,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 42b5383b55d8..00ea439d601d 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -54,7 +54,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts index 3dfce4312dfc..cf84e69fced8 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts @@ -13,7 +13,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 828a20561b96..f57b4ca145dd 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -41,12 +41,12 @@ #gpio-cells = <2>; gpio-line-names = "HDMI_HPD_N", "EMMC_EN_N", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; + "", + "", + "", + "", + "", + ""; status = "okay"; }; }; From 604319e94fc2a1ffa7ee9e3afc5d59eafefda998 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 11 Apr 2022 22:01:43 +0200 Subject: [PATCH 418/791] ARM: dts: bcm283x: Align ETH_CLK GPIO line name The GPIO line name ETHCLK is not aligned with the other signals like WIFI_CLK. Recently this has been fixed in the vendor tree, so upstream this change. Signed-off-by: Phil Elwell Signed-off-by: Stefan Wahren Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 2 +- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 7b7c363e5ee8..248feb2ed23d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -82,7 +82,7 @@ "CAM_GPIO0", /* GPIO41 */ "", /* GPIO42 */ "", /* GPIO43 */ - "ETHCLK", /* GPIO44 */ + "ETH_CLK", /* GPIO44 */ "PWM1_OUT", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index c824a2cea02e..3635502b1e0a 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -82,7 +82,7 @@ "CAM_GPIO0", "SMPS_SCL", "SMPS_SDA", - "ETHCLK", + "ETH_CLK", "PWM1_OUT", "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index fd4ac6f2d077..ec721d323ac5 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -109,7 +109,7 @@ "SD1_DATA3", "PWM0_OUT", "PWM1_OUT", - "ETHCLK", + "ETH_CLK", "WIFI_CLK", "SDA0", "SCL0", diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 00ea439d601d..fb6a417d73e7 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -102,7 +102,7 @@ "SD1_DATA3", "PWM0_OUT", "PWM1_OUT", - "ETHCLK", + "ETH_CLK", "WIFI_CLK", "SDA0", "SCL0", From 73618b43dc5af291be0eb150f4ba8a3c1a5c5436 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:11 +0200 Subject: [PATCH 419/791] ARM: dts: qcom-*-sony*: Mention SONY board names in DT filenames SONY phones/tables are based on a common board ('platform'). Devices based on the same are often close to identical. Mention their association in filenames, like it's done in arm64 DTs. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-2-konrad.dybcio@somainline.org --- arch/arm/boot/dts/Makefile | 8 ++++---- ...a-yuga.dts => qcom-apq8064-sony-xperia-lagan-yuga.dts} | 0 ...amami.dts => qcom-msm8974-sony-xperia-rhine-amami.dts} | 0 ...nami.dts => qcom-msm8974-sony-xperia-rhine-honami.dts} | 0 ...or.dts => qcom-msm8974-sony-xperia-shinano-castor.dts} | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm/boot/dts/{qcom-apq8064-sony-xperia-yuga.dts => qcom-apq8064-sony-xperia-lagan-yuga.dts} (100%) rename arch/arm/boot/dts/{qcom-msm8974-sony-xperia-amami.dts => qcom-msm8974-sony-xperia-rhine-amami.dts} (100%) rename arch/arm/boot/dts/{qcom-msm8974-sony-xperia-honami.dts => qcom-msm8974-sony-xperia-rhine-honami.dts} (100%) rename arch/arm/boot/dts/{qcom-msm8974-sony-xperia-castor.dts => qcom-msm8974-sony-xperia-shinano-castor.dts} (100%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 093e90b80adb..abc7c3a65579 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -982,7 +982,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ - qcom-apq8064-sony-xperia-yuga.dtb \ + qcom-apq8064-sony-xperia-lagan-yuga.dtb \ qcom-apq8064-asus-nexus7-flo.dtb \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ @@ -1004,9 +1004,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ qcom-msm8974-samsung-klte.dtb \ - qcom-msm8974-sony-xperia-amami.dtb \ - qcom-msm8974-sony-xperia-castor.dtb \ - qcom-msm8974-sony-xperia-honami.dtb \ + qcom-msm8974-sony-xperia-rhine-amami.dtb \ + qcom-msm8974-sony-xperia-rhine-honami.dtb \ + qcom-msm8974-sony-xperia-shinano-castor.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ qcom-sdx55-mtp.dtb \ qcom-sdx55-t55.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts rename to arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts rename to arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts rename to arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts rename to arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts From eba5e62045b2848042435ae0503d7c2354edf2af Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:12 +0200 Subject: [PATCH 420/791] ARM: dts: qcom-msm8974: Remove properties that are always overriden Model and compatible are set per-device, so having them in the SoC DTSI is superfluous. Remove them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-3-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c8ff4c21d852..4c773b63e59a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -12,8 +12,6 @@ / { #address-cells = <1>; #size-cells = <1>; - model = "Qualcomm MSM8974"; - compatible = "qcom,msm8974"; interrupt-parent = <&intc>; reserved-memory { From b905c34ae7db6b564589f02fa7eac7afaa0294e9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:13 +0200 Subject: [PATCH 421/791] ARM: dts: qcom-msm8974*: Fix UART naming It's either uart10, or blsp2_uart4, not blsp2_uart10, as there aren't 10 UARTs on BLSP2. Fix the naming to align with what's done in arm64/qcom. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-4-konrad.dybcio@somainline.org --- .../boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 6 +++--- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 10 +++++----- .../dts/qcom-msm8974-sony-xperia-shinano-castor.dts | 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 5fbdba73c07f..dd2d0647d4be 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -12,7 +12,7 @@ aliases { serial0 = &blsp1_uart1; - serial1 = &blsp2_uart10; + serial1 = &blsp2_uart4; }; chosen { @@ -395,7 +395,7 @@ }; }; - blsp2_uart10_pin_a: blsp2-uart10-pin-active { + blsp2_uart4_pin_a: blsp2-uart4-pin-active { tx { pins = "gpio53"; function = "blsp_uart10"; @@ -473,7 +473,7 @@ status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart10_pin_a>; + pinctrl-0 = <&blsp2_uart4_pin_a>; bluetooth { compatible = "brcm,bcm43438-bt"; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 1f630120c01f..95ae30d06554 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -358,13 +358,13 @@ status = "okay"; }; - /* blsp2_uart8 */ + /* blsp2_uart2 */ serial@f995e000 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart8_pins_active>; - pinctrl-1 = <&blsp2_uart8_pins_sleep>; + pinctrl-0 = <&blsp2_uart2_pins_active>; + pinctrl-1 = <&blsp2_uart2_pins_sleep>; bluetooth { compatible = "brcm,bcm43540-bt"; @@ -380,14 +380,14 @@ }; pinctrl@fd510000 { - blsp2_uart8_pins_active: blsp2-uart8-pins-active { + blsp2_uart2_pins_active: blsp2-uart2-pins-active { pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "blsp_uart8"; drive-strength = <8>; bias-disable; }; - blsp2_uart8_pins_sleep: blsp2-uart8-pins-sleep { + blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep { pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts index 3c4a7d760ba9..e27b360951fd 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts @@ -11,7 +11,7 @@ aliases { serial0 = &blsp1_uart2; - serial1 = &blsp2_uart7; + serial1 = &blsp2_uart1; }; chosen { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 4c773b63e59a..ccd2593dc8c4 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -713,7 +713,7 @@ status = "disabled"; }; - blsp2_uart7: serial@f995d000 { + blsp2_uart1: serial@f995d000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995d000 0x1000>; interrupts = ; @@ -722,7 +722,7 @@ status = "disabled"; }; - blsp2_uart8: serial@f995e000 { + blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; interrupts = ; @@ -731,7 +731,7 @@ status = "disabled"; }; - blsp2_uart10: serial@f9960000 { + blsp2_uart4: serial@f9960000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf9960000 0x1000>; interrupts = ; From bb167546d06847a8729c973fe5165a231fd5c39d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:14 +0200 Subject: [PATCH 422/791] ARM: dts: qcom-msm8974*: Fix I2C labels Fix up the label names and add missing ones. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-5-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ccd2593dc8c4..3a2f84c5174f 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -957,7 +957,7 @@ interrupts = ; }; - i2c@f9923000 { + blsp1_i2c1: i2c@f9923000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9923000 0x1000>; @@ -968,7 +968,7 @@ #size-cells = <0>; }; - i2c@f9924000 { + blsp1_i2c2: i2c@f9924000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9924000 0x1000>; @@ -979,7 +979,7 @@ #size-cells = <0>; }; - blsp_i2c3: i2c@f9925000 { + blsp1_i2c3: i2c@f9925000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9925000 0x1000>; @@ -990,7 +990,7 @@ #size-cells = <0>; }; - blsp_i2c6: i2c@f9928000 { + blsp1_i2c6: i2c@f9928000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9928000 0x1000>; @@ -1001,7 +1001,7 @@ #size-cells = <0>; }; - blsp_i2c8: i2c@f9964000 { + blsp2_i2c2: i2c@f9964000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9964000 0x1000>; @@ -1012,7 +1012,7 @@ #size-cells = <0>; }; - blsp_i2c11: i2c@f9967000 { + blsp2_i2c5: i2c@f9967000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9967000 0x1000>; @@ -1025,7 +1025,7 @@ dma-names = "tx", "rx"; }; - blsp_i2c12: i2c@f9968000 { + blsp2_i2c6: i2c@f9968000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9968000 0x1000>; From 4de36f7b6d0e7e792d36800ac6c5e3392b59573a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:15 +0200 Subject: [PATCH 423/791] ARM: dts: qcom-msm8974: Fix up mdss nodes Fix up formatting, move status=disabled to the end where it belongs, rename DSI PHY label to match newer DTs, use tabs where possible, unwrap lines where wrapping is not necessary and don't disable mdp, as MDSS is useless without it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-6-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 75 +++++++++++++---------------- 1 file changed, 33 insertions(+), 42 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 3a2f84c5174f..636d68a6f603 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1459,35 +1459,29 @@ }; mdss: mdss@fd900000 { - status = "disabled"; - compatible = "qcom,mdss"; - reg = <0xfd900000 0x100>, - <0xfd924000 0x1000>; - reg-names = "mdss_phys", - "vbif_phys"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; power-domains = <&mmcc MDSS_GDSC>; clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync"; + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "vsync"; interrupts = ; interrupt-controller; #interrupt-cells = <1>; + status = "disabled"; + #address-cells = <1>; #size-cells = <1>; ranges; mdp: mdp@fd900000 { - status = "disabled"; - compatible = "qcom,mdp5"; reg = <0xfd900100 0x22000>; reg-names = "mdp_phys"; @@ -1499,10 +1493,7 @@ <&mmcc MDSS_AXI_CLK>, <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; + clock-names = "iface", "bus", "core", "vsync"; interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; interconnect-names = "mdp0-mem"; @@ -1521,8 +1512,6 @@ }; dsi0: dsi@fd922800 { - status = "disabled"; - compatible = "qcom,mdss-dsi-ctrl"; reg = <0xfd922800 0x1f8>; reg-names = "dsi_ctrl"; @@ -1530,29 +1519,32 @@ interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_PCLK0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>; + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core", - "core_mmss"; + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; - phys = <&dsi_phy0>; + phys = <&dsi0_phy>; phy-names = "dsi-phy"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1572,23 +1564,22 @@ }; }; - dsi_phy0: dsi-phy@fd922a00 { - status = "disabled"; - + dsi0_phy: dsi-phy@fd922a00 { compatible = "qcom,dsi-phy-28nm-hpm"; reg = <0xfd922a00 0xd4>, <0xfd922b00 0x280>, <0xfd922d80 0x30>; reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; + "dsi_phy", + "dsi_phy_regulator"; #clock-cells = <1>; #phy-cells = <0>; - qcom,dsi-phy-index = <0>; clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; clock-names = "iface", "ref"; + + status = "disabled"; }; }; From 64cf62683b5398e46cf967c308be95685137626a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:16 +0200 Subject: [PATCH 424/791] ARM: dts: qcom-msm8974: Fix up SDHCI nodes - Add missing labels (and remove their redefinition from klte) - Commonize bus-width - Add non-removable on sdhc_1, as it's supposed to have an eMMC on it Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-7-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 4 ++-- arch/arm/boot/dts/qcom-msm8974.dtsi | 13 ++++++++++--- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 95ae30d06554..3ee2508b20fb 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -534,7 +534,7 @@ }; }; - sdhc_1: sdhci@f9824900 { + sdhci@f9824900 { status = "okay"; vmmc-supply = <&pma8084_l20>; @@ -547,7 +547,7 @@ pinctrl-0 = <&sdhc1_pin_a>; }; - sdhc_2: sdhci@f9864900 { + sdhci@f9864900 { status = "okay"; max-frequency = <100000000>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 636d68a6f603..49b22392fd5e 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -740,7 +740,7 @@ status = "disabled"; }; - sdhci@f9824900 { + sdhc_1: sdhci@f9824900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -751,10 +751,13 @@ <&gcc GCC_SDCC1_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; + bus-width = <8>; + non-removable; + status = "disabled"; }; - sdhci@f9864900 { + sdhc_3: sdhci@f9864900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -765,10 +768,12 @@ <&gcc GCC_SDCC3_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; + bus-width = <4>; + status = "disabled"; }; - sdhci@f98a4900 { + sdhc_2: sdhci@f98a4900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -779,6 +784,8 @@ <&gcc GCC_SDCC2_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; + bus-width = <4>; + status = "disabled"; }; From 087c9704d5bb322dd5db52938416caeaf4cdc3c3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:17 +0200 Subject: [PATCH 425/791] ARM: dts: qcom-msm8974*: Rename msmgpio to tlmm Rename the label to match new the style used in newer DTs. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-8-konrad.dybcio@somainline.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 2 +- .../boot/dts/qcom-msm8974-fairphone-fp2.dts | 2 +- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 18 ++++++++--------- .../boot/dts/qcom-msm8974-samsung-klte.dts | 20 +++++++++---------- .../qcom-msm8974-sony-xperia-rhine-amami.dts | 2 +- .../qcom-msm8974-sony-xperia-rhine-honami.dts | 4 ++-- ...com-msm8974-sony-xperia-shinano-castor.dts | 10 +++++----- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++-- 8 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index e2b4e4fc6377..9076a24408c6 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -35,7 +35,7 @@ }; sdhci@f98a4900 { - cd-gpios = <&msmgpio 62 0x1>; + cd-gpios = <&tlmm 62 0x1>; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; bus-width = <4>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 9dbfc9f8646a..1e947bab06b6 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -51,7 +51,7 @@ vibrator { compatible = "gpio-vibrator"; - enable-gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; vcc-supply = <&pm8941_l18>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index dd2d0647d4be..4154ffb207ac 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -250,7 +250,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -482,9 +482,9 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_pin>; - host-wakeup-gpios = <&msmgpio 42 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&msmgpio 62 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&msmgpio 41 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; }; }; @@ -522,7 +522,7 @@ mpu6515@68 { compatible = "invensense,mpu6515"; reg = <0x68>; - interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&tlmm 73 IRQ_TYPE_EDGE_FALLING>; vddio-supply = <&pm8941_lvs1>; pinctrl-names = "default"; @@ -538,7 +538,7 @@ ak8963@f { compatible = "asahi-kasei,ak8963"; reg = <0x0f>; - gpios = <&msmgpio 67 0>; + gpios = <&tlmm 67 0>; vid-supply = <&pm8941_lvs1>; vdd-supply = <&pm8941_l17>; }; @@ -577,7 +577,7 @@ maxim,double-soc; maxim,rcomp = /bits/ 8 <0x4d>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <9 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; @@ -600,7 +600,7 @@ compatible = "syna,rmi4-i2c"; reg = <0x70>; - interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&tlmm 5 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&pm8941_l22>; vio-supply = <&pm8941_lvs3>; @@ -632,7 +632,7 @@ avago_apds993@39 { compatible = "avago,apds9930"; reg = <0x39>; - interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&pm8941_l17>; vddio-supply = <&pm8941_lvs1>; led-max-microamp = <100000>; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 3ee2508b20fb..60244e0c37ba 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -247,8 +247,8 @@ compatible = "i2c-gpio"; #address-cells = <1>; #size-cells = <0>; - sda-gpios = <&msmgpio 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&i2c_touchkey_pins>; @@ -272,8 +272,8 @@ compatible = "i2c-gpio"; #address-cells = <1>; #size-cells = <0>; - scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&i2c_led_gpioex_pins>; @@ -291,7 +291,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpioex_pin>; - reset-gpios = <&msmgpio 145 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; }; led-controller@30 { @@ -371,9 +371,9 @@ max-speed = <3000000>; pinctrl-names = "default"; pinctrl-0 = <&bt_pins>; - device-wakeup-gpios = <&msmgpio 91 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wakeup"; }; @@ -563,7 +563,7 @@ */ pinctrl-names = "default"; pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; - // cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + // cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; }; sdhci@f98a4900 { @@ -587,7 +587,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; @@ -818,7 +818,7 @@ vddr-supply = <&vreg_panel>; reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; - te-gpios = <&msmgpio 12 GPIO_ACTIVE_HIGH>; + te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; port { panel_in: endpoint { diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts index 8cace789fb26..6545917dd489 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts @@ -280,7 +280,7 @@ vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts index f4a2e2560777..313c755f590f 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts @@ -305,7 +305,7 @@ vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; @@ -331,7 +331,7 @@ compatible = "syna,rmi4-i2c"; reg = <0x2c>; - interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts index e27b360951fd..352689237140 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts @@ -239,7 +239,7 @@ regulator-min-microvolt = <3150000>; regulator-max-microvolt = <3150000>; - gpio = <&msmgpio 69 0>; + gpio = <&tlmm 69 0>; enable-active-high; vin-supply = <&pm8941_s3>; @@ -323,7 +323,7 @@ vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; @@ -351,8 +351,8 @@ <&bt_dev_wake_pin>, <&bt_reg_on_pin>; - host-wakeup-gpios = <&msmgpio 95 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&msmgpio 96 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; }; }; @@ -566,7 +566,7 @@ compatible = "syna,rmi4-i2c"; reg = <0x2c>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <86 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 49b22392fd5e..df72c4432fc5 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -953,11 +953,11 @@ }; }; - msmgpio: pinctrl@fd510000 { + tlmm: pinctrl@fd510000 { compatible = "qcom,msm8974-pinctrl"; reg = <0xfd510000 0x4000>; gpio-controller; - gpio-ranges = <&msmgpio 0 0 146>; + gpio-ranges = <&tlmm 0 0 146>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From 9f440d17e2309c7d14eba0898c775be6d6e6d6b7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:18 +0200 Subject: [PATCH 426/791] ARM: dts: qcom-apq8074-dragonboard: Use &labels Use &labels to align with the style used in new DTS and apply tiny style fixes. Signed-off-by: Konrad Dybcio [bjorn: Rebased ontop of Krzysztof's underscore fixes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-9-konrad.dybcio@somainline.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 619 +++++++++--------- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 2 files changed, 303 insertions(+), 318 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 9076a24408c6..f114debe4d95 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -16,331 +16,316 @@ chosen { stdout-path = "serial0:115200n8"; }; +}; - soc { - serial@f991e000 { - status = "okay"; - }; +&blsp1_uart2 { + status = "okay"; +}; - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "okay"; +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <200000>; - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; + pinctrl-0 = <&i2c11_pins>; + pinctrl-names = "default"; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - cd-gpios = <&tlmm 62 0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - bus-width = <4>; - status = "okay"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - }; - - usb@f9a55000 { - status = "okay"; - phys = <&usb_hs2_phy>; - phy-select = <&tcsr 0xb000 1>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - hnp-disable; - srp-disable; - adp-disable; - ulpi { - phy@b { - status = "okay"; - v3p3-supply = <&pm8941_l24>; - v1p8-supply = <&pm8941_l6>; - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x63>; - }; - }; - }; - - - pinctrl@fd510000 { - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - }; - }; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - }; - - i2c@f9967000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c11_pins>; - pinctrl-names = "default"; - - eeprom: eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - read-only; - }; - }; + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + read-only; }; +}; - smd { - rpm { - rpm-requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; +&otg { + status = "okay"; - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; + phys = <&usb_hs2_phy>; + phy-select = <&tcsr 0xb000 1>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + hnp-disable; + srp-disable; + adp-disable; - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vin_5vs-supply = <&pm8941_5v>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; + ulpi { + phy@b { + status = "okay"; + v3p3-supply = <&pm8941_l24>; + v1p8-supply = <&pm8941_l6>; + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x63>; + }; + }; +}; + +&rpm_requests { + pm8841-regulators { + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vin_5vs-supply = <&pm8941_5v>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; +}; + +&sdhc_2 { + status = "okay"; + cd-gpios = <&tlmm 62 0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; +}; + +&tlmm { + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + }; + }; + + spi8_default: spi8_default { + mosi { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk { + pins = "gpio48"; + function = "blsp_spi8"; + }; + }; + + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_cd_pin_a: sdhc2-cd-pin-active { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index df72c4432fc5..e14c15789e87 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1610,7 +1610,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm-requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8974"; qcom,smd-channels = "rpm_requests"; From 409ab7dc57c41d9db54d221f4d247e229ba34cf9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:19 +0200 Subject: [PATCH 427/791] ARM: dts: qcom-msm8974-fp2: Use &labels Use &labels to align with the style used in new DTS and apply tiny style fixes. Signed-off-by: Konrad Dybcio [bjorn: Rebased on top of Krzysztof underscore fixes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-10-konrad.dybcio@somainline.org --- .../boot/dts/qcom-msm8974-fairphone-fp2.dts | 627 +++++++++--------- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 2 files changed, 301 insertions(+), 328 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 1e947bab06b6..38e48ea021d9 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -5,7 +5,6 @@ #include #include - / { model = "Fairphone 2"; compatible = "fairphone,fp2", "qcom,msm8974"; @@ -54,356 +53,330 @@ enable-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; vcc-supply = <&pm8941_l18>; }; +}; - smd { - rpm { - rpm-requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; +&blsp1_uart2 { + status = "okay"; +}; - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; +&imem { + status = "okay"; - s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; + reboot-mode { + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; +}; - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; +&otg { + status = "okay"; - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; - regulator-always-on; - regulator-boot-on; - }; + hnp-disable; + srp-disable; + adp-disable; - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; + ulpi { + phy@a { + status = "okay"; - regulator-boot-on; - }; + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3350000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; }; }; }; -&soc { - serial@f991e000 { - status = "okay"; +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio1", "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; }; +}; - remoteproc@fb21b000 { - status = "okay"; +&pronto { + status = "okay"; - vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; + vddmx-supply = <&pm8841_s1>; + vddcx-supply = <&pm8841_s2>; - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; - smd-edge { - qcom,remote-pid = <4>; - label = "pronto"; + smd-edge { + qcom,remote-pid = <4>; + label = "pronto"; - wcnss { - status = "okay"; - }; - }; - }; - - pinctrl@fd510000 { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - wcnss_pin_a: wcnss-pin-active { - wlan { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "wlan"; - - drive-strength = <6>; - bias-pull-down; - }; - - bt { - pins = "gpio35", "gpio43", "gpio44"; - function = "bt"; - - drive-strength = <2>; - bias-pull-down; - }; - - fm { - pins = "gpio41", "gpio42"; - function = "fm"; - - drive-strength = <2>; - bias-pull-down; - }; - }; - }; - - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "okay"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - bus-width = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - imem@fe805000 { - status = "okay"; - - reboot-mode { - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + wcnss { + status = "okay"; }; }; }; -&spmi_bus { - pm8941@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio1", "gpio2", "gpio5"; - function = "normal"; +&rpm_requests { + pm8841-regulators { + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; - bias-pull-up; - power-source = ; - }; + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>; +}; + +&tlmm { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-pin-active { + wlan { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + + drive-strength = <6>; + bias-pull-down; + }; + + bt { + pins = "gpio35", "gpio43", "gpio44"; + function = "bt"; + + drive-strength = <2>; + bias-pull-down; + }; + + fm { + pins = "gpio41", "gpio42"; + function = "fm"; + + drive-strength = <2>; + bias-pull-down; }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index e14c15789e87..2f50d7692b50 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1590,7 +1590,7 @@ }; }; - imem@fe805000 { + imem: imem@fe805000 { status = "disabled"; compatible = "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; From 1c1574e24990e9f9d753958745b8274874241158 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:20 +0200 Subject: [PATCH 428/791] ARM: dts: qcom-msm8974-lge-nexus5: Use &labels Use &labels to align with the style used in new DTS and apply tiny style fixes. Signed-off-by: Konrad Dybcio [bjorn: Rebased on top of Krzysztof's fixes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-11-konrad.dybcio@somainline.org --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 1314 ++++++++--------- 1 file changed, 638 insertions(+), 676 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 4154ffb207ac..a1cae3d453c2 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -40,209 +40,6 @@ }; }; - smd { - rpm { - rpm-requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; - vreg_wlan: wlan-regulator { compatible = "regulator-fixed"; @@ -258,504 +55,669 @@ }; }; -&soc { - serial@f991d000 { - status = "okay"; +&blsp1_i2c1 { + status = "okay"; + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + charger: bq24192@6b { + compatible = "ti,bq24192"; + reg = <0x6b>; + interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; + + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; }; - pinctrl@fd510000 { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; + fuelgauge: max17048@36 { + compatible = "maxim,max17048"; + reg = <0x36>; - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x4d>; - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - i2c1_pins: i2c1 { - mux { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c3_pins: i2c3 { - mux { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c12_pins: i2c12 { - mux { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - drive-strength = <2>; - bias-disable; - }; - }; - - mpu6515_pin: mpu6515 { - irq { - pins = "gpio73"; - function = "gpio"; - bias-disable; - input-enable; - }; - }; - - touch_pin: touch { - int { - pins = "gpio5"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - - reset { - pins = "gpio8"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - panel_pin: panel { - te { - pins = "gpio12"; - function = "mdp_vsync"; - - drive-strength = <2>; - bias-disable; - }; - }; - - bt_pin: bt { - hostwake { - pins = "gpio42"; - function = "gpio"; - }; - - devwake { - pins = "gpio62"; - function = "gpio"; - }; - - shutdown { - pins = "gpio41"; - function = "gpio"; - }; - }; - - blsp2_uart4_pin_a: blsp2-uart4-pin-active { - tx { - pins = "gpio53"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio54"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-pull-up; - }; - - cts { - pins = "gpio55"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-pull-up; - }; - - rts { - pins = "gpio56"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-disable; - }; - }; - }; - - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-0 = <&fuelgauge_pin>; + + maxim,alert-low-soc-level = <2>; }; +}; - sdhci@f98a4900 { - status = "okay"; +&blsp1_i2c2 { + status = "okay"; + clock-frequency = <355000>; - max-frequency = <100000000>; - bus-width = <4>; - non-removable; - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pm8941_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + synaptics@70 { + compatible = "syna,rmi4-i2c"; + reg = <0x70>; + + interrupts-extended = <&tlmm 5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; + pinctrl-0 = <&touch_pin>; #address-cells = <1>; #size-cells = <0>; - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; - }; - }; - - serial@f9960000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart4_pin_a>; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bt_pin>; - - host-wakeup-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c@f9967000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - led-controller@38 { - compatible = "ti,lm3630a"; - status = "okay"; - reg = <0x38>; - - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - led-sources = <0 1>; - label = "lcd-backlight"; - default-brightness = <200>; - }; - }; - }; - - i2c@f9968000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - mpu6515@68 { - compatible = "invensense,mpu6515"; - reg = <0x68>; - interrupts-extended = <&tlmm 73 IRQ_TYPE_EDGE_FALLING>; - vddio-supply = <&pm8941_lvs1>; - - pinctrl-names = "default"; - pinctrl-0 = <&mpu6515_pin>; - - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "1"; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ak8963@f { - compatible = "asahi-kasei,ak8963"; - reg = <0x0f>; - gpios = <&tlmm 67 0>; - vid-supply = <&pm8941_lvs1>; - vdd-supply = <&pm8941_l17>; - }; - - bmp280@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - vdda-supply = <&pm8941_lvs1>; - vddd-supply = <&pm8941_l17>; - }; - }; - }; - }; - - i2c@f9923000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - charger: bq24192@6b { - compatible = "ti,bq24192"; - reg = <0x6b>; - interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; - - omit-battery-class; - - usb_otg_vbus: usb-otg-vbus { }; + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; }; - fuelgauge: max17048@36 { - compatible = "maxim,max17048"; - reg = <0x36>; - - maxim,double-soc; - maxim,rcomp = /bits/ 8 <0x4d>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&fuelgauge_pin>; - - maxim,alert-low-soc-level = <2>; - }; - }; - - i2c@f9924000 { - status = "okay"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - synaptics@70 { - compatible = "syna,rmi4-i2c"; - reg = <0x70>; - - interrupts-extended = <&tlmm 5 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; - }; - - i2c@f9925000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - avago_apds993@39 { - compatible = "avago,apds9930"; - reg = <0x39>; - interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l17>; - vddio-supply = <&pm8941_lvs1>; - led-max-microamp = <100000>; - amstaos,proximity-diodes = <0>; - }; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - - extcon = <&charger>, <&usb_id>; - vbus-supply = <&usb_otg_vbus>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - mdss@fd900000 { - status = "okay"; - - mdp@fd900000 { - status = "okay"; - }; - - dsi@fd922800 { - status = "okay"; - - vdda-supply = <&pm8941_l2>; - vdd-supply = <&pm8941_lvs3>; - vddio-supply = <&pm8941_l12>; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - reg = <0>; - compatible = "lg,acx467akm-7"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_pin>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi-phy@fd922a00 { - status = "okay"; - - vddio-supply = <&pm8941_l12>; + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; }; }; }; -&spmi_bus { - pm8941@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3"; - function = "normal"; +&blsp1_i2c3 { + status = "okay"; + clock-frequency = <100000>; - bias-pull-up; - power-source = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + avago_apds993@39 { + compatible = "avago,apds9930"; + reg = <0x39>; + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l17>; + vddio-supply = <&pm8941_lvs1>; + led-max-microamp = <100000>; + amstaos,proximity-diodes = <0>; + }; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c11_pins>; + + led-controller@38 { + compatible = "ti,lm3630a"; + status = "okay"; + reg = <0x38>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0 1>; + label = "lcd-backlight"; + default-brightness = <200>; + }; + }; +}; + +&blsp2_i2c6 { + status = "okay"; + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_pins>; + + mpu6515@68 { + compatible = "invensense,mpu6515"; + reg = <0x68>; + interrupts-extended = <&tlmm 73 IRQ_TYPE_EDGE_FALLING>; + vddio-supply = <&pm8941_lvs1>; + + pinctrl-names = "default"; + pinctrl-0 = <&mpu6515_pin>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ak8963@f { + compatible = "asahi-kasei,ak8963"; + reg = <0x0f>; + gpios = <&tlmm 67 0>; + vid-supply = <&pm8941_lvs1>; + vdd-supply = <&pm8941_l17>; }; - fuelgauge_pin: fuelgauge-int { - pins = "gpio9"; - function = "normal"; - - bias-disable; - input-enable; - power-source = ; - }; - - wlan_sleep_clk_pin: wl-sleep-clk { - pins = "gpio16"; - function = "func2"; - - output-high; - power-source = ; - }; - - wlan_regulator_pin: wl-reg-active { - pins = "gpio17"; - function = "normal"; - - bias-disable; - power-source = ; - }; - - otg { - gpio-hog; - gpios = <35 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "otg-gpio"; + bmp280@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + vdda-supply = <&pm8941_lvs1>; + vddd-supply = <&pm8941_l17>; }; }; }; }; + +&blsp1_uart1 { + status = "okay"; +}; + +&blsp2_uart4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart4_pin_a>; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_pin>; + + host-wakeup-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + }; +}; + +&dsi0 { + status = "okay"; + + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_lvs3>; + vddio-supply = <&pm8941_l12>; + + panel: panel@0 { + reg = <0>; + compatible = "lg,acx467akm-7"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_pin>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + + vddio-supply = <&pm8941_l12>; +}; + +&mdss { + status = "okay"; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + extcon = <&charger>, <&usb_id>; + vbus-supply = <&usb_otg_vbus>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + + fuelgauge_pin: fuelgauge-int { + pins = "gpio9"; + function = "normal"; + + bias-disable; + input-enable; + power-source = ; + }; + + wlan_sleep_clk_pin: wl-sleep-clk { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + }; + + wlan_regulator_pin: wl-reg-active { + pins = "gpio17"; + function = "normal"; + + bias-disable; + power-source = ; + }; + + otg { + gpio-hog; + gpios = <35 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "otg-gpio"; + }; +}; + +&rpm_requests { + pm8841-regulators { + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; +}; + +&sdhc_2 { + status = "okay"; + + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8941_s3>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; +}; + +&tlmm { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1 { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c3_pins: i2c3 { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c12_pins: i2c12 { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-disable; + }; + }; + + mpu6515_pin: mpu6515 { + irq { + pins = "gpio73"; + function = "gpio"; + bias-disable; + input-enable; + }; + }; + + touch_pin: touch { + int { + pins = "gpio5"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + + reset { + pins = "gpio8"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + panel_pin: panel { + te { + pins = "gpio12"; + function = "mdp_vsync"; + + drive-strength = <2>; + bias-disable; + }; + }; + + bt_pin: bt { + hostwake { + pins = "gpio42"; + function = "gpio"; + }; + + devwake { + pins = "gpio62"; + function = "gpio"; + }; + + shutdown { + pins = "gpio41"; + function = "gpio"; + }; + }; + + blsp2_uart4_pin_a: blsp2-uart4-pin-active { + tx { + pins = "gpio53"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio54"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-pull-up; + }; + + cts { + pins = "gpio55"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-pull-up; + }; + + rts { + pins = "gpio56"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-disable; + }; + }; +}; From 1d59524b9181e17110ae7b809c62a6a66f336fd6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:21 +0200 Subject: [PATCH 429/791] ARM: dts: qcom-msm8974-klte: Use &labels Use &labels to align with the style used in new DTS and apply tiny style fixes. Signed-off-by: Konrad Dybcio [bjorn: Rebased on top of Krzysztof's fixes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-12-konrad.dybcio@somainline.org --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 1392 ++++++++--------- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 +- 2 files changed, 680 insertions(+), 716 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 60244e0c37ba..3b1ea8c24f57 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -13,7 +13,7 @@ aliases { serial0 = &blsp1_uart1; mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ + mmc1 = &sdhc_3; /* SDC2 SD card slot */ }; chosen { @@ -52,197 +52,6 @@ }; }; - smd { - rpm { - rpm-requests { - pma8084-regulators { - compatible = "qcom,rpm-pma8084-regulators"; - status = "okay"; - - pma8084_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - pma8084_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_s5: s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - pma8084_s6: s6 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l3: l3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pma8084_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pma8084_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l19: l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - pma8084_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - pma8084_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pma8084_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pma8084_l25: l25 { - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - }; - - pma8084_l26: l26 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l27: l27 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; - }; - }; - }; - i2c-gpio-touchkey { compatible = "i2c-gpio"; #address-cells = <1>; @@ -347,562 +156,717 @@ }; /delete-node/ vreg-boost; - - adsp-pil { - cx-supply = <&pma8084_s2>; - }; }; -&soc { - serial@f991e000 { - status = "okay"; - }; +&blsp1_i2c2 { + status = "okay"; - /* blsp2_uart2 */ - serial@f995e000 { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_pins_active>; - pinctrl-1 = <&blsp2_uart2_pins_sleep>; + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; - bluetooth { - compatible = "brcm,bcm43540-bt"; - max-speed = <3000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_pins>; - device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&tlmm>; - interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - }; - }; + interrupt-parent = <&pma8084_gpios>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - pinctrl@fd510000 { - blsp2_uart2_pins_active: blsp2-uart2-pins-active { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "blsp_uart8"; - drive-strength = <8>; - bias-disable; - }; - - blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - bt_pins: bt-pins { - hostwake { - pins = "gpio75"; - function = "gpio"; - drive-strength = <16>; - input-enable; - }; - - devwake { - pins = "gpio91"; - function = "gpio"; - drive-strength = <2>; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <4>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <4>; - bias-pull-up; - }; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk-cmd-data { - pins = "gpio35", "gpio36", "gpio37", "gpio38", - "gpio39", "gpio40"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; - }; - - sdhc2_cd_pin: sdhc2-cd { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc3_pin_a: sdhc3-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c6_pins: i2c6 { - mux { - pins = "gpio29", "gpio30"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c12_pins: i2c12 { - mux { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_touchkey_pins: i2c-touchkey { - mux { - pins = "gpio95", "gpio96"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - }; - - i2c_led_gpioex_pins: i2c-led-gpioex { - mux { - pins = "gpio120", "gpio121"; - function = "gpio"; - input-enable; - bias-pull-down; - }; - }; - - gpioex_pin: gpioex { - res { - pins = "gpio145"; - function = "gpio"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - wifi_pin: wifi { - int { - pins = "gpio92"; - function = "gpio"; - - input-enable; - bias-pull-down; - }; - }; - - panel_te_pin: panel { - te { - pins = "gpio12"; - function = "mdp_vsync"; - - drive-strength = <2>; - bias-disable; - }; - }; - }; - - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pma8084_l20>; - vqmmc-supply = <&pma8084_s4>; - - bus-width = <8>; - non-removable; + vdd-supply = <&max77826_ldo13>; + vio-supply = <&pma8084_lvs2>; pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; + pinctrl-0 = <&touch_pin>; - sdhci@f9864900 { - status = "okay"; - - max-frequency = <100000000>; - - vmmc-supply = <&pma8084_l21>; - vqmmc-supply = <&pma8084_l13>; - - bus-width = <4>; - - /* cd-gpio is intentionally disabled. If enabled, an SD card - * present during boot is not initialized correctly. Without - * cd-gpios the driver resorts to polling, so hotplug works. - */ - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; - // cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - }; - - sdhci@f98a4900 { - status = "okay"; + syna,startup-delay-ms = <100>; #address-cells = <1>; #size-cells = <0>; - max-frequency = <100000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_pin_a>; - - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pma8084_s4>; - - bus-width = <4>; - non-removable; - - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - - interrupt-parent = <&tlmm>; - interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; - }; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - /*extcon = <&smbb>, <&usb_id>;*/ - /*vbus-supply = <&chg_otg>;*/ - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pma8084_l6>; - v3p3-supply = <&pma8084_l24>; - - /*extcon = <&smbb>;*/ - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - i2c@f9924000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - vdd-supply = <&max77826_ldo13>; - vio-supply = <&pma8084_lvs2>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - - syna,startup-delay-ms = <100>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; - }; - - i2c@f9928000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - - pmic@60 { - reg = <0x60>; - compatible = "maxim,max77826"; - - regulators { - max77826_ldo1: LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo2: LDO2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - max77826_ldo3: LDO3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo4: LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo5: LDO5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo6: LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo7: LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo8: LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo9: LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo10: LDO10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo11: LDO11 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo12: LDO12 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo13: LDO13 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo14: LDO14 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo15: LDO15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_buck: BUCK { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - max77826_buckboost: BUCKBOOST { - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - }; - }; - }; - }; - - i2c@f9968000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_pins>; - - fuelgauge@36 { - compatible = "maxim,max17048"; - reg = <0x36>; - - maxim,double-soc; - maxim,rcomp = /bits/ 8 <0x56>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&fuelgauge_pin>; - }; - }; - - adreno@fdb00000 { - status = "ok"; - }; - - mdss@fd900000 { - status = "ok"; - - mdp@fd900000 { - status = "ok"; + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; }; - dsi@fd922800 { - status = "ok"; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - reg = <0>; - compatible = "samsung,s6e3fa2"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_te_pin &panel_rst_pin>; - - iovdd-supply = <&pma8084_lvs4>; - vddr-supply = <&vreg_panel>; - - reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; - te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; }; - - dsi-phy@fd922a00 { - status = "ok"; - - vddio-supply = <&pma8084_l12>; - }; - }; - - remoteproc@fc880000 { - cx-supply = <&pma8084_s2>; - mss-supply = <&pma8084_s6>; - mx-supply = <&pma8084_s1>; - pll-supply = <&pma8084_l12>; }; }; -&spmi_bus { - pma8084@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio5"; - function = "normal"; +&blsp1_i2c6 { + status = "okay"; - bias-pull-up; - power-source = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + + pmic@60 { + reg = <0x60>; + compatible = "maxim,max77826"; + + regulators { + max77826_ldo1: LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; }; - touchkey_pin: touchkey-int-pin { - pins = "gpio6"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; + max77826_ldo2: LDO2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; }; - touch_pin: touchscreen-int-pin { - pins = "gpio8"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; + max77826_ldo3: LDO3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; }; - panel_en_pin: panel-en-pin { - pins = "gpio14"; - function = "normal"; - bias-pull-up; - power-source = ; - qcom,drive-strength = ; + max77826_ldo4: LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - wlan_sleep_clk_pin: wlan-sleep-clk-pin { - pins = "gpio16"; - function = "func2"; - - output-high; - power-source = ; - qcom,drive-strength = ; + max77826_ldo5: LDO5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - panel_rst_pin: panel-rst-pin { - pins = "gpio17"; - function = "normal"; - bias-disable; - power-source = ; - qcom,drive-strength = ; + max77826_ldo6: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; + max77826_ldo7: LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - fuelgauge_pin: fuelgauge-int-pin { - pins = "gpio21"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; + max77826_ldo8: LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo9: LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo10: LDO10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo11: LDO11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo12: LDO12 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo13: LDO13 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo14: LDO14 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo15: LDO15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_buck: BUCK { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + max77826_buckboost: BUCKBOOST { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; }; }; }; }; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c6 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_pins>; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + }; +}; + +&blsp2_uart2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_pins_active>; + pinctrl-1 = <&blsp2_uart2_pins_sleep>; + + bluetooth { + compatible = "brcm,bcm43540-bt"; + max-speed = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&tlmm>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + }; +}; + +&dsi0 { + status = "okay"; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + panel: panel@0 { + reg = <0>; + compatible = "samsung,s6e3fa2"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_te_pin &panel_rst_pin>; + + iovdd-supply = <&pma8084_lvs4>; + vddr-supply = <&vreg_panel>; + + reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; + te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + + vddio-supply = <&pma8084_l12>; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "okay"; + + v1p8-supply = <&pma8084_l6>; + v3p3-supply = <&pma8084_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; +}; + +&pma8084_gpios { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + + touchkey_pin: touchkey-int-pin { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + touch_pin: touchscreen-int-pin { + pins = "gpio8"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + panel_en_pin: panel-en-pin { + pins = "gpio14"; + function = "normal"; + bias-pull-up; + power-source = ; + qcom,drive-strength = ; + }; + + wlan_sleep_clk_pin: wlan-sleep-clk-pin { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + qcom,drive-strength = ; + }; + + panel_rst_pin: panel-rst-pin { + pins = "gpio17"; + function = "normal"; + bias-disable; + power-source = ; + qcom,drive-strength = ; + }; + + fuelgauge_pin: fuelgauge-int-pin { + pins = "gpio21"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; +}; + +&remoteproc_adsp { + cx-supply = <&pma8084_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pma8084_s2>; + mss-supply = <&pma8084_s6>; + mx-supply = <&pma8084_s1>; + pll-supply = <&pma8084_l12>; +}; + +&rpm_requests { + pma8084-regulators { + compatible = "qcom,rpm-pma8084-regulators"; + + pma8084_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + pma8084_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pma8084_s6: s6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pma8084_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pma8084_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pma8084_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pma8084_l25: l25 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pma8084_l26: l26 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pma8084_l20>; + vqmmc-supply = <&pma8084_s4>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; +}; + +&sdhc_2 { + status = "okay"; + max-frequency = <100000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_pin_a>; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pma8084_s4>; + + non-removable; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + interrupt-parent = <&tlmm>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; + }; +}; + +&sdhc_3 { + status = "okay"; + max-frequency = <100000000>; + + vmmc-supply = <&pma8084_l21>; + vqmmc-supply = <&pma8084_l13>; + + /* + * cd-gpio is intentionally disabled. If enabled, an SD card + * present during boot is not initialized correctly. Without + * cd-gpios the driver resorts to polling, so hotplug works. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; + /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ +}; + +&tlmm { + blsp2_uart2_pins_active: blsp2-uart2-pins-active { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_uart8"; + drive-strength = <8>; + bias-disable; + }; + + blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + bt_pins: bt-pins { + hostwake { + pins = "gpio75"; + function = "gpio"; + drive-strength = <16>; + input-enable; + }; + + devwake { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + }; + }; + + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk-cmd-data { + pins = "gpio35", "gpio36", "gpio37", "gpio38", + "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + }; + + sdhc2_cd_pin: sdhc2-cd { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc3_pin_a: sdhc3-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c6_pins: i2c6 { + mux { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c12_pins: i2c12 { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_touchkey_pins: i2c-touchkey { + mux { + pins = "gpio95", "gpio96"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + + i2c_led_gpioex_pins: i2c-led-gpioex { + mux { + pins = "gpio120", "gpio121"; + function = "gpio"; + input-enable; + bias-pull-down; + }; + }; + + gpioex_pin: gpioex { + res { + pins = "gpio145"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + }; + + wifi_pin: wifi { + int { + pins = "gpio92"; + function = "gpio"; + + input-enable; + bias-pull-down; + }; + }; + + panel_te_pin: panel { + te { + pins = "gpio12"; + function = "mdp_vsync"; + + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 2f50d7692b50..35d595a2796f 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -339,7 +339,7 @@ clock-frequency = <19200000>; }; - adsp-pil { + remoteproc_adsp: adsp-pil { compatible = "qcom,msm8974-adsp-pil"; interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, @@ -840,7 +840,7 @@ clock-names = "core"; }; - remoteproc@fc880000 { + remoteproc_mss: remoteproc@fc880000 { compatible = "qcom,msm8974-mss-pil"; reg = <0xfc880000 0x100>, <0xfc820000 0x020>; reg-names = "qdsp6", "rmb"; From 5c554c2d67a8c6c43a1fb542cbc73c33ff04c344 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:22 +0200 Subject: [PATCH 430/791] ARM: dts: qcom-msm8974-{"hon","am"}ami: Commonize and modernize the DTs Sony Xperia Z1 and Z1 compact are almost identical, and that shows in their DTs. Commonize the repeating parts and modernize the DTs to use labels. As a bonus, Z1C gains touchscreen support in this commit, as it was present on Z1 already. Signed-off-by: Konrad Dybcio [bjorn: Rebased on top of Krzysztof's fixes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-13-konrad.dybcio@somainline.org --- .../qcom-msm8974-sony-xperia-rhine-amami.dts | 432 +--------------- .../qcom-msm8974-sony-xperia-rhine-honami.dts | 479 +----------------- .../dts/qcom-msm8974-sony-xperia-rhine.dtsi | 449 ++++++++++++++++ arch/arm/boot/dts/qcom-pm8941.dtsi | 2 +- 4 files changed, 456 insertions(+), 906 deletions(-) create mode 100644 arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts index 6545917dd489..68d5626bf491 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts @@ -1,435 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include +#include "qcom-msm8974-sony-xperia-rhine.dtsi" / { model = "Sony Xperia Z1 Compact"; compatible = "sony,xperia-amami", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; - - smd { - rpm { - rpm-requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; }; -&soc { - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "okay"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - }; - - dma-controller@f9944000 { - qcom,controlled-remotely; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1300000>; - qcom,fast-charge-current-limit = <1300000>; - qcom,dc-current-limit = <1300000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - }; - - coincell@2800 { - status = "okay"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; - - pm8941@1 { - wled@d800 { - status = "okay"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - }; - }; +&smbb { + qcom,fast-charge-safe-current = <1300000>; + qcom,fast-charge-current-limit = <1300000>; + qcom,dc-current-limit = <1300000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts index 313c755f590f..ea6a941d8f8c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts @@ -1,484 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include -#include -#include +#include "qcom-msm8974-sony-xperia-rhine.dtsi" / { model = "Sony Xperia Z1"; compatible = "sony,xperia-honami", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - }; - }; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; - - smd { - rpm { - rpm-requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "okay"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - i2c@f9924000 { - status = "okay"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - syna,sensor-type = <1>; - }; - }; - }; - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - ts_int_pin: touch-int { - pin { - pins = "gpio61"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - }; - }; - - dma-controller@f9944000 { - qcom,controlled-remotely; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - }; - - coincell@2800 { - status = "okay"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; - - pm8941@1 { - wled@d800 { - status = "okay"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - }; - }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi new file mode 100644 index 000000000000..87ec3694add9 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include +#include +#include + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + clock-frequency = <355000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + syna,startup-delay-ms = <10>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-inverted-x; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_pin_a>; +}; + +&blsp2_dma { + qcom,controlled-remotely; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; +}; + +&pm8941_coincell { + status = "okay"; + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3", "gpio4", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; +}; + +&pm8941_wled { + status = "okay"; + + qcom,cs-out; + qcom,current-limit = <20>; + qcom,current-boost-limit = <805>; + qcom,switching-freq = <1600>; + qcom,ovp = <29>; + qcom,num-strings = <2>; +}; + +&rpm_requests { + pm8841-regulators { + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s4: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; +}; + +&tlmm { + ts_int_pin: touch-int { + pin { + pins = "gpio61"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + blsp1_uart2_pin_a: blsp1-uart2-pin-active { + rx { + pins = "gpio5"; + function = "blsp_uart2"; + + drive-strength = <2>; + bias-pull-up; + }; + + tx { + pins = "gpio4"; + function = "blsp_uart2"; + + drive-strength = <4>; + bias-disable; + }; + }; + + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_cd_pin_a: sdhc2-cd-pin-active { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index da00b8f5eecd..cdd2bdb77b32 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -131,7 +131,7 @@ qcom,external-resistor-micro-ohms = <10000>; }; - coincell@2800 { + pm8941_coincell: coincell@2800 { compatible = "qcom,pm8941-coincell"; reg = <0x2800>; status = "disabled"; From 598a1e333224e73ae8f078ed6aa8dcd416cfb490 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:23 +0200 Subject: [PATCH 431/791] ARM: dts: qcom-msm8974-castor: Use &labels Use &labels to align with the style used in new DTS and apply tiny style fixes. Signed-off-by: Konrad Dybcio [bjorn: Rebased ontop of Krzysztof's fixes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-14-konrad.dybcio@somainline.org --- ...com-msm8974-sony-xperia-shinano-castor.dts | 1170 ++++++++--------- 1 file changed, 572 insertions(+), 598 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts index 352689237140..687f6149268c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts @@ -53,186 +53,6 @@ }; }; - smd { - rpm { - rpm-requests { - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-system-load = <154000>; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <500000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; - vreg_bl_vddio: lcd-backlight-vddio { compatible = "regulator-fixed"; regulator-name = "vreg_bl_vddio"; @@ -277,447 +97,601 @@ }; }; -&soc { - sdhci@f9824900 { - status = "okay"; +&blsp1_uart2 { + status = "okay"; - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_pin_a>; +}; - bus-width = <8>; - non-removable; +&blsp2_i2c2 { + status = "okay"; + clock-frequency = <355000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_pins>; - sdhci@f9864900 { - status = "okay"; + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; - max-frequency = <100000000>; - non-removable; - vmmc-supply = <&vreg_wlan>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_pin_a>; + interrupt-parent = <&tlmm>; + interrupts = <86 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; #size-cells = <0>; - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; - }; - }; - - sdhci@f98a4900 { - status = "okay"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; + pinctrl-0 = <&ts_int_pin>; - serial@f991e000 { - status = "okay"; + syna,startup-delay-ms = <10>; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - serial@f995d000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart7_pin_a>; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_pin>, - <&bt_dev_wake_pin>, - <&bt_reg_on_pin>; - - host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; - }; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; + rmi-f01@1 { + reg = <0x1>; + syna,nosleep = <1>; }; - blsp2_uart7_pin_a: blsp2-uart7-pin-active { - tx { - pins = "gpio41"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio42"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-pull-up; - }; - - cts { - pins = "gpio43"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-pull-up; - }; - - rts { - pins = "gpio44"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c8_pins: i2c8 { - mux { - pins = "gpio47", "gpio48"; - function = "blsp_i2c8"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - - drive-strength = <2>; - bias-disable; - }; - }; - - lcd_backlight_en_pin_a: lcd-backlight-vddio { - pins = "gpio69"; - drive-strength = <10>; - output-low; - bias-disable; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - sdhc3_pin_a: sdhc3-pin-active { - clk { - pins = "gpio40"; - function = "sdc3"; - - drive-strength = <10>; - bias-disable; - }; - - cmd { - pins = "gpio39"; - function = "sdc3"; - - drive-strength = <10>; - bias-pull-up; - }; - - data { - pins = "gpio35", "gpio36", "gpio37", "gpio38"; - function = "sdc3"; - - drive-strength = <10>; - bias-pull-up; - }; - }; - - ts_int_pin: synaptics { - pin { - pins = "gpio86"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - }; - - bt_host_wake_pin: bt-host-wake { - pins = "gpio95"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - output-low; - }; - - bt_dev_wake_pin: bt-dev-wake { - pins = "gpio96"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c@f9964000 { - status = "okay"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_pins>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupt-parent = <&tlmm>; - interrupts = <86 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi-f01@1 { - reg = <0x1>; - syna,nosleep = <1>; - }; - - rmi-f11@11 { - reg = <0x11>; - syna,f11-flip-x = <1>; - syna,sensor-type = <1>; - }; - }; - }; - - i2c@f9967000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - lp8566_wled: backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - power-supply = <&vreg_bl_vddio>; - - bl-name = "backlight"; - dev-ctrl = /bits/ 8 <0x05>; - init-brt = /bits/ 8 <0x3f>; - rom_a0h { - rom-addr = /bits/ 8 <0xa0>; - rom-val = /bits/ 8 <0xff>; - }; - rom_a1h { - rom-addr = /bits/ 8 <0xa1>; - rom-val = /bits/ 8 <0x3f>; - }; - rom_a2h { - rom-addr = /bits/ 8 <0xa2>; - rom-val = /bits/ 8 <0x20>; - }; - rom_a3h { - rom-addr = /bits/ 8 <0xa3>; - rom-val = /bits/ 8 <0x5e>; - }; - rom_a4h { - rom-addr = /bits/ 8 <0xa4>; - rom-val = /bits/ 8 <0x02>; - }; - rom_a5h { - rom-addr = /bits/ 8 <0xa5>; - rom-val = /bits/ 8 <0x04>; - }; - rom_a6h { - rom-addr = /bits/ 8 <0xa6>; - rom-val = /bits/ 8 <0x80>; - }; - rom_a7h { - rom-addr = /bits/ 8 <0xa7>; - rom-val = /bits/ 8 <0xf7>; - }; - rom_a9h { - rom-addr = /bits/ 8 <0xa9>; - rom-val = /bits/ 8 <0x80>; - }; - rom_aah { - rom-addr = /bits/ 8 <0xaa>; - rom-val = /bits/ 8 <0x0f>; - }; - rom_aeh { - rom-addr = /bits/ 8 <0xae>; - rom-val = /bits/ 8 <0x0f>; - }; + rmi-f11@11 { + reg = <0x11>; + syna,f11-flip-x = <1>; + syna,sensor-type = <1>; }; }; }; -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c11_pins>; + + lp8566_wled: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + power-supply = <&vreg_bl_vddio>; + + bl-name = "backlight"; + dev-ctrl = /bits/ 8 <0x05>; + init-brt = /bits/ 8 <0x3f>; + rom_a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - - bt_reg_on_pin: bt-reg-on { - pins = "gpio16"; - function = "normal"; - - output-low; - power-source = ; - }; - - wlan_sleep_clk_pin: wl-sleep-clk { - pins = "gpio17"; - function = "func2"; - - output-high; - power-source = ; - }; - - wlan_regulator_pin: wl-reg-active { - pins = "gpio18"; - function = "normal"; - - bias-disable; - power-source = ; - }; - - lcd_dcdc_en_pin_a: lcd-dcdc-en-active { - pins = "gpio20"; - function = "normal"; - - bias-disable; - power-source = ; - input-disable; - output-low; - }; - + rom_a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; }; + rom_a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + rom_a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + rom_a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x02>; + }; + rom_a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x04>; + }; + rom_a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + rom_a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf7>; + }; + rom_a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0x80>; + }; + rom_aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x0f>; + }; + rom_aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; +}; - coincell@2800 { +&blsp2_uart1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart7_pin_a>; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_pin>, + <&bt_dev_wake_pin>, + <&bt_reg_on_pin>; + + host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; + }; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { status = "okay"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; }; }; }; + +&pm8941_coincell { + status = "okay"; + + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + + bt_reg_on_pin: bt-reg-on { + pins = "gpio16"; + function = "normal"; + + output-low; + power-source = ; + }; + + wlan_sleep_clk_pin: wl-sleep-clk { + pins = "gpio17"; + function = "func2"; + + output-high; + power-source = ; + }; + + wlan_regulator_pin: wl-reg-active { + pins = "gpio18"; + function = "normal"; + + bias-disable; + power-source = ; + }; + + lcd_dcdc_en_pin_a: lcd-dcdc-en-active { + pins = "gpio20"; + function = "normal"; + + bias-disable; + power-source = ; + input-disable; + output-low; + }; + +}; + +&rpm_requests { + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <154000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s4: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <500000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; +}; + +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_pin_a>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; +}; + +&tlmm { + blsp1_uart2_pin_a: blsp1-uart2-pin-active { + rx { + pins = "gpio5"; + function = "blsp_uart2"; + + drive-strength = <2>; + bias-pull-up; + }; + + tx { + pins = "gpio4"; + function = "blsp_uart2"; + + drive-strength = <4>; + bias-disable; + }; + }; + + blsp2_uart7_pin_a: blsp2-uart7-pin-active { + tx { + pins = "gpio41"; + function = "blsp_uart7"; + + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio42"; + function = "blsp_uart7"; + + drive-strength = <2>; + bias-pull-up; + }; + + cts { + pins = "gpio43"; + function = "blsp_uart7"; + + drive-strength = <2>; + bias-pull-up; + }; + + rts { + pins = "gpio44"; + function = "blsp_uart7"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c8_pins: i2c8 { + mux { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + + drive-strength = <2>; + bias-disable; + }; + }; + + lcd_backlight_en_pin_a: lcd-backlight-vddio { + pins = "gpio69"; + drive-strength = <10>; + output-low; + bias-disable; + }; + + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_cd_pin_a: sdhc2-cd-pin-active { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + sdhc3_pin_a: sdhc3-pin-active { + clk { + pins = "gpio40"; + function = "sdc3"; + + drive-strength = <10>; + bias-disable; + }; + + cmd { + pins = "gpio39"; + function = "sdc3"; + + drive-strength = <10>; + bias-pull-up; + }; + + data { + pins = "gpio35", "gpio36", "gpio37", "gpio38"; + function = "sdc3"; + + drive-strength = <10>; + bias-pull-up; + }; + }; + + ts_int_pin: synaptics { + pin { + pins = "gpio86"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + bt_host_wake_pin: bt-host-wake { + pins = "gpio95"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-low; + }; + + bt_dev_wake_pin: bt-dev-wake { + pins = "gpio96"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; From 7bdc6d8c37c0848da6646484aa1b5e3554525ee5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:24 +0200 Subject: [PATCH 432/791] ARM: dts: qcom-msm8974pro: Use &labels Use &labels to align with the style used in new DTS and apply tiny style fixes. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-15-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974pro.dtsi | 35 +++++++++++--------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi index b64c28036dd0..973bd1dafbfe 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -1,23 +1,18 @@ #include "qcom-msm8974.dtsi" -/ { - soc { - sdhci@f9824900 { - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>, - <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, - <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names = "core", "iface", "xo", "cal", "sleep"; - }; - - clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974pro"; - }; - - adreno@fdb00000 { - compatible = "qcom,adreno-330.2", - "qcom,adreno"; - }; - }; +&gcc { + compatible = "qcom,gcc-msm8974pro"; +}; + +&gpu { + compatible = "qcom,adreno-330.2", "qcom,adreno"; +}; + +&sdhc_1 { + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, + <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; + clock-names = "core", "iface", "xo", "cal", "sleep"; }; From c919956818361826903707e023efbb6db7b49091 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:25 +0200 Subject: [PATCH 433/791] ARM: dts: qcom-msm8974pro-*: Use the 8974pro name in DT filenames Add the 'pro' part to the filenames of DTs of devices that are based on this SoC to make in easier to differentiate between Snapdragon 800- and 801-based platforms. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-16-konrad.dybcio@somainline.org --- arch/arm/boot/dts/Makefile | 4 ++-- ...8974-samsung-klte.dts => qcom-msm8974pro-samsung-klte.dts} | 0 ...tor.dts => qcom-msm8974pro-sony-xperia-shinano-castor.dts} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/boot/dts/{qcom-msm8974-samsung-klte.dts => qcom-msm8974pro-samsung-klte.dts} (100%) rename arch/arm/boot/dts/{qcom-msm8974-sony-xperia-shinano-castor.dts => qcom-msm8974pro-sony-xperia-shinano-castor.dts} (100%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index abc7c3a65579..56aa6fc4d3a4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1003,10 +1003,10 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-samsung-klte.dtb \ qcom-msm8974-sony-xperia-rhine-amami.dtb \ qcom-msm8974-sony-xperia-rhine-honami.dtb \ - qcom-msm8974-sony-xperia-shinano-castor.dtb \ + qcom-msm8974pro-samsung-klte.dtb \ + qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ qcom-sdx55-mtp.dtb \ qcom-sdx55-t55.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts rename to arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-shinano-castor.dts rename to arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts From 2daa785817dd35172b856c30fc5148b2773b6891 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:26 +0200 Subject: [PATCH 434/791] ARM: dts: qcom-msm8974: Convert ADSP to a MMIO device The cx-supply has been removed as it's supposed to be set on a per-board basis. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-17-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 60 ++++++++++++++--------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 35d595a2796f..606d1a57c39f 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -339,36 +339,6 @@ clock-frequency = <19200000>; }; - remoteproc_adsp: adsp-pil { - compatible = "qcom,msm8974-adsp-pil"; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - cx-supply = <&pm8841_s2>; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; - - label = "lpass"; - }; - }; - smem { compatible = "qcom,smem"; @@ -1590,6 +1560,36 @@ }; }; + remoteproc_adsp: remoteproc@fe200000 { + compatible = "qcom,msm8974-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + label = "lpass"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + imem: imem@fe805000 { status = "disabled"; compatible = "syscon", "simple-mfd"; From f300826d27be7f7f671c922bf57007c98c683590 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:27 +0200 Subject: [PATCH 435/791] ARM: dts: qcom-msm8974: Sort and clean up nodes - Remove regulators from the SoC DTSI - cpu_pmu{} -> pmu{} - move modem/iris regulators out of here; only FP2 used them - tcsr_mutex is moved out of /soc Signed-off-by: Konrad Dybcio [bjorn: Rebased on top of Krzysztof's fixes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-18-konrad.dybcio@somainline.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 4 + .../boot/dts/qcom-msm8974-fairphone-fp2.dts | 12 + .../qcom-msm8974-lge-nexus5-hammerhead.dts | 7 + .../dts/qcom-msm8974-sony-xperia-rhine.dtsi | 6 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2740 ++++++++--------- ...-msm8974pro-sony-xperia-shinano-castor.dts | 4 + 6 files changed, 1372 insertions(+), 1401 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index f114debe4d95..f47020cf7a90 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -61,6 +61,8 @@ &rpm_requests { pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + pm8841_s1: s1 { regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; @@ -83,6 +85,8 @@ }; pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + vdd_l1_l3-supply = <&pm8941_s1>; vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; vdd_l4_l11-supply = <&pm8941_s1>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 38e48ea021d9..d6799a1b820b 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -109,10 +109,18 @@ vddmx-supply = <&pm8841_s1>; vddcx-supply = <&pm8841_s2>; + vddpx-supply = <&pm8941_s3>; pinctrl-names = "default"; pinctrl-0 = <&wcnss_pin_a>; + iris { + vddxo-supply = <&pm8941_l6>; + vddrfa-supply = <&pm8941_l11>; + vddpa-supply = <&pm8941_l19>; + vdddig-supply = <&pm8941_s3>; + }; + smd-edge { qcom,remote-pid = <4>; label = "pronto"; @@ -125,6 +133,8 @@ &rpm_requests { pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + pm8841_s1: s1 { regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; @@ -142,6 +152,8 @@ }; pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + vdd_l1_l3-supply = <&pm8941_s1>; vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; vdd_l4_l11-supply = <&pm8941_s1>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index a1cae3d453c2..6537950c30ba 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -334,6 +334,8 @@ &rpm_requests { pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + pm8841_s1: s1 { regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; @@ -356,6 +358,8 @@ }; pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + vdd_l1_l3-supply = <&pm8941_s1>; vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; vdd_l4_l11-supply = <&pm8941_s1>; @@ -517,6 +521,9 @@ regulator-max-microvolt = <3075000>; regulator-boot-on; }; + + pm8941_lvs1: lvs1 {}; + pm8941_lvs3: lvs3 {}; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 87ec3694add9..870e0aeb4d05 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -153,6 +153,8 @@ &rpm_requests { pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + pm8841_s1: s1 { regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; @@ -175,6 +177,8 @@ }; pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + vdd_l1_l3-supply = <&pm8941_s1>; vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; vdd_l4_l11-supply = <&pm8941_s1>; @@ -335,6 +339,8 @@ regulator-max-microvolt = <3075000>; regulator-boot-on; }; + + pm8941_lvs3: lvs3 {}; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 606d1a57c39f..1799d204c409 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -14,57 +14,17 @@ #size-cells = <1>; interrupt-parent = <&intc>; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_region: mpss@8000000 { - reg = <0x08000000 0x5100000>; - no-map; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; }; - mba_region: mba@d100000 { - reg = <0x0d100000 0x100000>; - no-map; - }; - - wcnss_region: wcnss@d200000 { - reg = <0x0d200000 0xa00000>; - no-map; - }; - - adsp_region: adsp@dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - - venus@f500000 { - reg = <0x0f500000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - - tz@fc00000 { - reg = <0x0fc00000 0x160000>; - no-map; - }; - - rfsa@fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; - }; - - rmtfs@fd80000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0fd80000 0x180000>; - no-map; - - qcom,client-id = <1>; + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; }; @@ -134,11 +94,1340 @@ }; }; + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + memory { device_type = "memory"; reg = <0x0 0x0>; }; + pmu { + compatible = "qcom,krait-pmu"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_region: mpss@8000000 { + reg = <0x08000000 0x5100000>; + no-map; + }; + + mba_region: mba@d100000 { + reg = <0x0d100000 0x100000>; + no-map; + }; + + wcnss_region: wcnss@d200000 { + reg = <0x0d200000 0xa00000>; + no-map; + }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; + }; + + venus_region: memory@f500000 { + reg = <0x0f500000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0xfa00000 0x200000>; + no-map; + }; + + tz_region: memory@fc00000 { + reg = <0x0fc00000 0x160000>; + no-map; + }; + + rfsa_mem: memory@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-2 = <&apcs 8 9>; + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + adsp_smsm: adsp@2 { + reg = <2>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@7 { + reg = <7>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm_requests { + compatible = "qcom,rpm-msm8974"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + apcs: syscon@f9011000 { + compatible = "syscon"; + reg = <0xf9011000 0x1000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + saw0: power-controller@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { + compatible = "qcom,saw2"; + reg = <0xf9012000 0x1000>; + regulator; + }; + + acc0: clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + }; + + acc1: clock-controller@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + }; + + acc2: clock-controller@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + }; + + acc3: clock-controller@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + }; + + sdhc_1: sdhci@f9824900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + bus-width = <8>; + non-removable; + + status = "disabled"; + }; + + sdhc_3: sdhci@f9864900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC3_APPS_CLK>, + <&gcc GCC_SDCC3_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + bus-width = <4>; + + status = "disabled"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + bus-width = <4>; + + status = "disabled"; + }; + + blsp1_uart1: serial@f991d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991d000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_i2c1: i2c@f9923000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@f9924000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9924000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@f9925000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9925000 0x1000>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c6: i2c@f9928000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_dma: dma-controller@f9944000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xf9944000 0x19000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp2_uart1: serial@f995d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995d000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp2_uart2: serial@f995e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995e000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp2_uart4: serial@f9960000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf9960000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp2_i2c2: i2c@f9964000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9964000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c5: i2c@f9967000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9967000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; + }; + + blsp2_i2c6: i2c@f9968000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9968000 0x1000>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + + otg: usb@f9a55000 { + compatible = "qcom,ci-hdrc"; + reg = <0xf9a55000 0x200>, + <0xf9a55200 0x200>; + interrupts = ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <75000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs1_phy: phy@a { + compatible = "qcom,usb-hs-phy-msm8974", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb_hs2_phy: phy@b { + compatible = "qcom,usb-hs-phy-msm8974", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; + reset-names = "phy", "por"; + status = "disabled"; + }; + }; + }; + + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + pronto: remoteproc@fb21b000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_region>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + iris { + compatible = "qcom,wcn3680"; + + clocks = <&rpmcc RPM_SMD_CXO_A2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + status = "disabled"; + + qcom,mmio = <&pronto>; + + bt { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + etf@fc307000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0xfc307000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&merger_out>; + }; + }; + }; + }; + + tpiu@fc318000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xfc318000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = <&replicator_out1>; + }; + }; + }; + }; + + funnel@fc31a000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc31a000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 0 - not-connected + * 1 - connected trought funnel to Multimedia CPU + * 2 - connected to Wireless CPU + * 3 - not-connected + * 4 - not-connected + * 6 - not-connected + * 7 - connected to STM + */ + port@5 { + reg = <5>; + funnel1_in5: endpoint { + remote-endpoint = <&kpss_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&merger_in1>; + }; + }; + }; + }; + + funnel@fc31b000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc31b000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 0 - connected trought funnel to Audio, Modem and + * Resource and Power Manager CPU's + * 2...7 - not-connected + */ + port@1 { + reg = <1>; + merger_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + }; + + out-ports { + port { + merger_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + }; + + replicator@fc31c000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0xfc31c000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etr@fc322000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0xfc322000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out0>; + }; + }; + }; + }; + + etm@fc33c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33c000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&kpss_in0>; + }; + }; + }; + }; + + etm@fc33d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33d000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&kpss_in1>; + }; + }; + }; + }; + + etm@fc33e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33e000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&kpss_in2>; + }; + }; + }; + }; + + etm@fc33f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0xfc33f000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&kpss_in3>; + }; + }; + }; + }; + + /* KPSS funnel, only 4 inputs are used */ + funnel@fc345000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc345000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + kpss_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + kpss_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + port@2 { + reg = <2>; + kpss_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + port@3 { + reg = <3>; + kpss_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + kpss_out: endpoint { + remote-endpoint = <&funnel1_in5>; + }; + }; + }; + }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x4000>; + }; + + rpm_msg_ram: memory@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + + bimc: interconnect@fc380000 { + reg = <0xfc380000 0x6a000>; + compatible = "qcom,msm8974-bimc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + snoc: interconnect@fc460000 { + reg = <0xfc460000 0x4000>; + compatible = "qcom,msm8974-snoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + pnoc: interconnect@fc468000 { + reg = <0xfc468000 0x4000>; + compatible = "qcom,msm8974-pnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PNOC_CLK>, + <&rpmcc RPM_SMD_PNOC_A_CLK>; + }; + + ocmemnoc: interconnect@fc470000 { + reg = <0xfc470000 0x4000>; + compatible = "qcom,msm8974-ocmemnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; + }; + + mmssnoc: interconnect@fc478000 { + reg = <0xfc478000 0x4000>; + compatible = "qcom,msm8974-mmssnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&mmcc MMSS_S0_AXI_CLK>, + <&mmcc MMSS_S0_AXI_CLK>; + }; + + cnoc: interconnect@fc480000 { + reg = <0xfc480000 0x4000>; + compatible = "qcom,msm8974-cnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + tsens: thermal-sensor@fc4a9000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #qcom,sensors = <11>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + qfprom: qfprom@fc4bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + remoteproc_mss: remoteproc@fc880000 { + compatible = "qcom,msm8974-mss-pil"; + reg = <0xfc880000 0x100>, <0xfc820000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 12>; + qcom,smd-edge = <0>; + + label = "modem"; + }; + }; + + tcsr_mutex_block: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + tcsr: syscon@fd4a0000 { + compatible = "syscon"; + reg = <0xfd4a0000 0x10000>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8974-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfd8c0000 0x6000>; + }; + + mdss: mdss@fd900000 { + compatible = "qcom,mdss"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@fd900000 { + compatible = "qcom,mdp5"; + reg = <0xfd900100 0x22000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; + interconnect-names = "mdp0-mem"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xfd922800 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&dsi0_phy>; + phy-names = "dsi-phy"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x280>, + <0xfd922d80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + gpu: adreno@fdb00000 { + compatible = "qcom,adreno-330.1", "qcom,adreno"; + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + clock-names = "core", "iface", "mem_iface"; + + sram = <&gmu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, + <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; + interconnect-names = "gfx-mem", "ocmem"; + + // iommus = <&gpu_iommu 0>; + + status = "disabled"; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-27000000 { + opp-hz = /bits/ 64 <27000000>; + }; + }; + }; + + ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", "mem"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x100000>; + }; + }; + + remoteproc_adsp: remoteproc@fe200000 { + compatible = "qcom,msm8974-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + label = "lpass"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + imem: imem@fe805000 { + status = "disabled"; + compatible = "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + }; + }; + }; + + tcsr_mutex: tcsr-mutex { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x80>; + + #hwlock-cells = <1>; + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; @@ -311,25 +1600,6 @@ }; }; - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - timer { compatible = "arm,armv7-timer"; interrupts = , @@ -339,1339 +1609,6 @@ clock-frequency = <19200000>; }; - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcnss { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; - - interrupt-parent = <&intc>; - interrupts = ; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - adsp_smsm: adsp@2 { - reg = <2>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@7 { - reg = <7>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; - }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; - }; - }; - - tsens: thermal-sensor@fc4a9000 { - compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #qcom,sensors = <11>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-controller@f9089000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-controller@f9099000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-controller@f90a9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-controller@f90b9000 { - compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: clock-controller@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; - }; - - acc1: clock-controller@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; - }; - - acc2: clock-controller@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; - }; - - acc3: clock-controller@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - }; - - tcsr: syscon@fd4a0000 { - compatible = "syscon"; - reg = <0xfd4a0000 0x10000>; - }; - - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfd8c0000 0x6000>; - }; - - tcsr_mutex: tcsr-mutex { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - - #hwlock-cells = <1>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - blsp1_uart1: serial@f991d000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991d000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_uart1: serial@f995d000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995d000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_uart4: serial@f9960000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf9960000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhc_1: sdhci@f9824900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - bus-width = <8>; - non-removable; - - status = "disabled"; - }; - - sdhc_3: sdhci@f9864900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - bus-width = <4>; - - status = "disabled"; - }; - - sdhc_2: sdhci@f98a4900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - bus-width = <4>; - - status = "disabled"; - }; - - otg: usb@f9a55000 { - compatible = "qcom,ci-hdrc"; - reg = <0xf9a55000 0x200>, - <0xf9a55200 0x200>; - interrupts = ; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <75000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs1_phy: phy@a { - compatible = "qcom,usb-hs-phy-msm8974", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; - reset-names = "phy", "por"; - status = "disabled"; - }; - - usb_hs2_phy: phy@b { - compatible = "qcom,usb-hs-phy-msm8974", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; - reset-names = "phy", "por"; - status = "disabled"; - }; - }; - }; - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - remoteproc_mss: remoteproc@fc880000 { - compatible = "qcom,msm8974-mss-pil"; - reg = <0xfc880000 0x100>, <0xfc820000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - - qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - - label = "modem"; - }; - }; - - pronto: remoteproc@fb21b000 { - compatible = "qcom,pronto-v2-pil", "qcom,pronto"; - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - memory-region = <&wcnss_region>; - - interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - vddpx-supply = <&pm8941_s3>; - - qcom,smem-states = <&wcnss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - iris { - compatible = "qcom,wcn3680"; - - clocks = <&rpmcc RPM_SMD_CXO_A2>; - clock-names = "xo"; - - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - status = "disabled"; - - qcom,mmio = <&pronto>; - - bluetooth { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = , - ; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8974-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - blsp1_i2c1: i2c@f9923000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9923000 0x1000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c2: i2c@f9924000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9924000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c3: i2c@f9925000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9925000 0x1000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c6: i2c@f9928000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9928000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c2: i2c@f9964000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9964000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c5: i2c@f9967000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9967000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; - dma-names = "tx", "rx"; - }; - - blsp2_i2c6: i2c@f9968000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9968000 0x1000>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - blsp2_dma: dma-controller@f9944000 { - compatible = "qcom,bam-v1.4.0"; - reg = <0xf9944000 0x19000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - etr@fc322000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc322000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - tpiu@fc318000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0xfc318000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - replicator@fc31c000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0xfc31c000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@fc307000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc307000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merger_out>; - }; - }; - }; - }; - - funnel@fc31b000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc31b000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - connected trought funnel to Audio, Modem and - * Resource and Power Manager CPU's - * 2...7 - not-connected - */ - port@1 { - reg = <1>; - merger_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - }; - - out-ports { - port { - merger_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - }; - - funnel@fc31a000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc31a000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - not-connected - * 1 - connected trought funnel to Multimedia CPU - * 2 - connected to Wireless CPU - * 3 - not-connected - * 4 - not-connected - * 6 - not-connected - * 7 - connected to STM - */ - port@5 { - reg = <5>; - funnel1_in5: endpoint { - remote-endpoint = <&kpss_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merger_in1>; - }; - }; - }; - }; - - funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc345000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - kpss_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - kpss_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - kpss_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - kpss_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - kpss_out: endpoint { - remote-endpoint = <&funnel1_in5>; - }; - }; - }; - }; - - etm@fc33c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33c000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&kpss_in0>; - }; - }; - }; - }; - - etm@fc33d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33d000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&kpss_in1>; - }; - }; - }; - }; - - etm@fc33e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33e000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&kpss_in2>; - }; - }; - }; - }; - - etm@fc33f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0xfc33f000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&kpss_in3>; - }; - }; - }; - }; - - ocmem@fdd00000 { - compatible = "qcom,msm8974-ocmem"; - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x180000>; - reg-names = "ctrl", - "mem"; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&mmcc OCMEMCX_OCMEMNOC_CLK>; - clock-names = "core", - "iface"; - - #address-cells = <1>; - #size-cells = <1>; - - gmu_sram: gmu-sram@0 { - reg = <0x0 0x100000>; - }; - }; - - bimc: interconnect@fc380000 { - reg = <0xfc380000 0x6a000>; - compatible = "qcom,msm8974-bimc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - snoc: interconnect@fc460000 { - reg = <0xfc460000 0x4000>; - compatible = "qcom,msm8974-snoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - pnoc: interconnect@fc468000 { - reg = <0xfc468000 0x4000>; - compatible = "qcom,msm8974-pnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; - }; - - ocmemnoc: interconnect@fc470000 { - reg = <0xfc470000 0x4000>; - compatible = "qcom,msm8974-ocmemnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; - }; - - mmssnoc: interconnect@fc478000 { - reg = <0xfc478000 0x4000>; - compatible = "qcom,msm8974-mmssnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&mmcc MMSS_S0_AXI_CLK>, - <&mmcc MMSS_S0_AXI_CLK>; - }; - - cnoc: interconnect@fc480000 { - reg = <0xfc480000 0x4000>; - compatible = "qcom,msm8974-cnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; - }; - - gpu: adreno@fdb00000 { - status = "disabled"; - - compatible = "qcom,adreno-330.1", - "qcom,adreno"; - reg = <0xfdb00000 0x10000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = "core", - "iface", - "mem_iface"; - clocks = <&mmcc OXILI_GFX3D_CLK>, - <&mmcc OXILICX_AHB_CLK>, - <&mmcc OXILICX_AXI_CLK>; - sram = <&gmu_sram>; - power-domains = <&mmcc OXILICX_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - - interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, - <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; - interconnect-names = "gfx-mem", - "ocmem"; - - // iommus = <&gpu_iommu 0>; - - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-320000000 { - opp-hz = /bits/ 64 <320000000>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - - opp-27000000 { - opp-hz = /bits/ 64 <27000000>; - }; - }; - }; - - mdss: mdss@fd900000 { - compatible = "qcom,mdss"; - reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&mmcc MDSS_GDSC>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "vsync"; - - interrupts = ; - - interrupt-controller; - #interrupt-cells = <1>; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@fd900000 { - compatible = "qcom,mdp5"; - reg = <0xfd900100 0x22000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; - interconnect-names = "mdp0-mem"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0xfd922800 0x1f8>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_PCLK0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>; - clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core", - "core_mmss"; - - phys = <&dsi0_phy>; - phy-names = "dsi-phy"; - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - dsi0_phy: dsi-phy@fd922a00 { - compatible = "qcom,dsi-phy-28nm-hpm"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x280>, - <0xfd922d80 0x30>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - }; - - remoteproc_adsp: remoteproc@fe200000 { - compatible = "qcom,msm8974-adsp-pil"; - reg = <0xfe200000 0x100>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; - label = "lpass"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - imem: imem@fe805000 { - status = "disabled"; - compatible = "syscon", "simple-mfd"; - reg = <0xfe805000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; - }; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - pm8841-regulators { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 {}; - pm8841_s2: s2 {}; - pm8841_s3: s3 {}; - pm8841_s4: s4 {}; - pm8841_s5: s5 {}; - pm8841_s6: s6 {}; - pm8841_s7: s7 {}; - pm8841_s8: s8 {}; - }; - - pm8941-regulators { - compatible = "qcom,rpm-pm8941-regulators"; - - pm8941_s1: s1 {}; - pm8941_s2: s2 {}; - pm8941_s3: s3 {}; - - pm8941_l1: l1 {}; - pm8941_l2: l2 {}; - pm8941_l3: l3 {}; - pm8941_l4: l4 {}; - pm8941_l5: l5 {}; - pm8941_l6: l6 {}; - pm8941_l7: l7 {}; - pm8941_l8: l8 {}; - pm8941_l9: l9 {}; - pm8941_l10: l10 {}; - pm8941_l11: l11 {}; - pm8941_l12: l12 {}; - pm8941_l13: l13 {}; - pm8941_l14: l14 {}; - pm8941_l15: l15 {}; - pm8941_l16: l16 {}; - pm8941_l17: l17 {}; - pm8941_l18: l18 {}; - pm8941_l19: l19 {}; - pm8941_l20: l20 {}; - pm8941_l21: l21 {}; - pm8941_l22: l22 {}; - pm8941_l23: l23 {}; - pm8941_l24: l24 {}; - - pm8941_lvs1: lvs1 {}; - pm8941_lvs2: lvs2 {}; - pm8941_lvs3: lvs3 {}; - }; - }; - }; - }; - vreg_boost: vreg-boost { compatible = "regulator-fixed"; @@ -1688,6 +1625,7 @@ pinctrl-names = "default"; pinctrl-0 = <&boost_bypass_n_pin>; }; + vreg_vph_pwr: vreg-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph-pwr"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 687f6149268c..b8b6447b3217 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -304,6 +304,8 @@ &rpm_requests { pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + vdd_l1_l3-supply = <&pm8941_s1>; vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; vdd_l4_l11-supply = <&pm8941_s1>; @@ -465,6 +467,8 @@ regulator-max-microvolt = <3075000>; regulator-boot-on; }; + + pm8941_lvs3: lvs3 {}; }; }; From 9f43e1973840955c0bd639c504095fba5f565e20 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:28 +0200 Subject: [PATCH 436/791] ARM: dts: qcom-msm8974*: Enable IMEM unconditionally It's always a part of the SoC, so it makes little sense to disable it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-19-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 2 -- arch/arm/boot/dts/qcom-msm8974.dtsi | 1 - 2 files changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index d6799a1b820b..7056c6f7145d 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -60,8 +60,6 @@ }; &imem { - status = "okay"; - reboot-mode { mode-normal = <0x77665501>; mode-bootloader = <0x77665500>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 1799d204c409..c7dffb36be57 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1410,7 +1410,6 @@ }; imem: imem@fe805000 { - status = "disabled"; compatible = "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; From 1dfe967ec7cfb03b468d096a69d945070f1cd2a0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:29 +0200 Subject: [PATCH 437/791] ARM: dts: qcom-msm8974*: Consolidate I2C/UART/SDHCI Clean up and commonize (where possible and it makes sense to) I2C, UART and SDHCI nodes and pin configurations. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-20-konrad.dybcio@somainline.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 61 ++--- .../boot/dts/qcom-msm8974-fairphone-fp2.dts | 14 +- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 117 +-------- .../dts/qcom-msm8974-sony-xperia-rhine.dtsi | 63 ++--- arch/arm/boot/dts/qcom-msm8974.dtsi | 245 +++++++++++++++++- .../boot/dts/qcom-msm8974pro-samsung-klte.dts | 77 ++---- ...-msm8974pro-sony-xperia-shinano-castor.dts | 141 ++-------- 7 files changed, 331 insertions(+), 387 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index f47020cf7a90..3051a861ff0c 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -26,9 +26,6 @@ status = "okay"; clock-frequency = <200000>; - pinctrl-0 = <&i2c11_pins>; - pinctrl-names = "default"; - eeprom: eeprom@52 { compatible = "atmel,24c128"; reg = <0x52>; @@ -256,48 +253,25 @@ vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; }; &sdhc_2 { status = "okay"; - cd-gpios = <&tlmm 62 0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; + cd-gpios = <&tlmm 62 0x1>; vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; }; &tlmm { - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - }; - }; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; drive-strength = <16>; @@ -311,15 +285,7 @@ }; }; - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { + sdc2_on: sdc2-on { clk { pins = "sdc2_clk"; drive-strength = <10>; @@ -331,5 +297,12 @@ drive-strength = <6>; bias-pull-up; }; + + cd { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 7056c6f7145d..7ae0b15e50f9 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -321,8 +321,9 @@ vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; }; &sdhc_2 { @@ -331,12 +332,13 @@ vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; }; &tlmm { - sdhc1_pin_a: sdhc1-pin-active { + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; drive-strength = <16>; @@ -350,7 +352,7 @@ }; }; - sdhc2_pin_a: sdhc2-pin-active { + sdc2_on: sdc2-on { clk { pins = "sdc2_clk"; drive-strength = <10>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 6537950c30ba..7e4e723f1dc3 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -59,9 +59,6 @@ status = "okay"; clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - charger: bq24192@6b { compatible = "ti,bq24192"; reg = <0x6b>; @@ -93,9 +90,6 @@ status = "okay"; clock-frequency = <355000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - synaptics@70 { compatible = "syna,rmi4-i2c"; reg = <0x70>; @@ -126,9 +120,6 @@ status = "okay"; clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - avago_apds993@39 { compatible = "avago,apds9930"; reg = <0x39>; @@ -144,9 +135,6 @@ status = "okay"; clock-frequency = <355000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - led-controller@38 { compatible = "ti,lm3630a"; status = "okay"; @@ -168,9 +156,6 @@ status = "okay"; clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_pins>; - mpu6515@68 { compatible = "invensense,mpu6515"; reg = <0x68>; @@ -212,9 +197,6 @@ &blsp2_uart4 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart4_pin_a>; - bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <3000000>; @@ -533,8 +515,9 @@ vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; }; &sdhc_2 { @@ -545,11 +528,9 @@ vqmmc-supply = <&pm8941_s3>; non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; - - #address-cells = <1>; - #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; bcrmf@1 { compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; @@ -563,7 +544,7 @@ }; &tlmm { - sdhc1_pin_a: sdhc1-pin-active { + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; drive-strength = <16>; @@ -577,7 +558,7 @@ }; }; - sdhc2_pin_a: sdhc2-pin-active { + sdc2_on: sdc2-on { clk { pins = "sdc2_clk"; drive-strength = <6>; @@ -591,54 +572,6 @@ }; }; - i2c1_pins: i2c1 { - mux { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c3_pins: i2c3 { - mux { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c12_pins: i2c12 { - mux { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - drive-strength = <2>; - bias-disable; - }; - }; - mpu6515_pin: mpu6515 { irq { pins = "gpio73"; @@ -693,38 +626,4 @@ function = "gpio"; }; }; - - blsp2_uart4_pin_a: blsp2-uart4-pin-active { - tx { - pins = "gpio53"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio54"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-pull-up; - }; - - cts { - pins = "gpio55"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-pull-up; - }; - - rts { - pins = "gpio56"; - function = "blsp_uart10"; - - drive-strength = <2>; - bias-disable; - }; - }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 870e0aeb4d05..c2e423d2a21e 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -55,9 +55,6 @@ status = "okay"; clock-frequency = <355000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - synaptics@2c { compatible = "syna,rmi4-i2c"; reg = <0x2c>; @@ -90,9 +87,6 @@ &blsp1_uart2 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; }; &blsp2_dma { @@ -350,8 +344,9 @@ vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; }; &sdhc_2 { @@ -362,8 +357,9 @@ cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; }; &smbb { @@ -389,35 +385,7 @@ }; }; - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; drive-strength = <16>; @@ -431,15 +399,7 @@ }; }; - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { + sdc2_on: sdc-on { clk { pins = "sdc2_clk"; drive-strength = <10>; @@ -451,5 +411,12 @@ drive-strength = <6>; bias-pull-up; }; + + cd { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c7dffb36be57..814ad0b46232 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -466,6 +466,9 @@ clock-names = "core", "iface", "xo"; bus-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -482,6 +485,9 @@ clock-names = "core", "iface", "xo"; bus-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -510,6 +516,9 @@ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c1_default>; + pinctrl-1 = <&blsp1_i2c1_sleep>; #address-cells = <1>; #size-cells = <0>; }; @@ -521,6 +530,9 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; #address-cells = <1>; #size-cells = <0>; }; @@ -532,6 +544,9 @@ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; #address-cells = <1>; #size-cells = <0>; }; @@ -543,6 +558,9 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c6_default>; + pinctrl-1 = <&blsp1_i2c6_sleep>; #address-cells = <1>; #size-cells = <0>; }; @@ -591,6 +609,9 @@ interrupts = ; clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; #address-cells = <1>; #size-cells = <0>; }; @@ -602,10 +623,13 @@ interrupts = ; clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c5_default>; + pinctrl-1 = <&blsp2_i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; }; blsp2_i2c6: i2c@f9968000 { @@ -1185,6 +1209,223 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = ; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; + }; + + blsp1_uart2_active: blsp1-uart2-active { + rx { + pins = "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-pull-up; + }; + + tx { + pins = "gpio4"; + function = "blsp_uart2"; + drive-strength = <4>; + bias-disable; + }; + }; + + blsp2_uart1_active: blsp2-uart1-active { + tx-rts { + pins = "gpio41", "gpio44"; + function = "blsp_uart7"; + drive-strength = <2>; + bias-disable; + }; + + rx-cts { + pins = "gpio42", "gpio43"; + function = "blsp_uart7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp2_uart1_sleep: blsp2-uart1-sleep { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_uart4_active: blsp2-uart4-active { + tx-rts { + pins = "gpio53", "gpio56"; + function = "blsp_uart10"; + drive-strength = <2>; + bias-disable; + }; + + rx-cts { + pins = "gpio54", "gpio55"; + function = "blsp_uart10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_i2c1_default: blsp1-i2c1-default { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c1_sleep: blsp1-i2c1-sleep { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c2_default: blsp1-i2c2-default { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c3_default: blsp1-i2c3-default { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-pull-up; + }; + + /* BLSP1_I2C4 info is missing */ + + /* BLSP1_I2C5 info is missing */ + + blsp1_i2c6_default: blsp1-i2c6-default { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c6_sleep: blsp1-i2c6-sleep { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-pull-up; + }; + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ + + /* BLSP2_I2C1 info is missing */ + + blsp2_i2c2_default: blsp2-i2c2-default { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-pull-up; + }; + + /* BLSP2_I2C3 info is missing */ + + /* BLSP2_I2C4 info is missing */ + + blsp2_i2c5_default: blsp2-i2c5-default { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c5_sleep: blsp2-i2c5-sleep { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-pull-up; + }; + + /* BLSP2_I2C6 info is missing - nobody uses it though? */ + + spi8_default: spi8_default { + mosi { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk { + pins = "gpio48"; + function = "blsp_spi8"; + }; + }; }; mmcc: clock-controller@fd8c0000 { diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts index 3b1ea8c24f57..c8151a665ea7 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -161,9 +161,6 @@ &blsp1_i2c2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - touchscreen@20 { compatible = "syna,rmi4-i2c"; reg = <0x20>; @@ -197,9 +194,6 @@ &blsp1_i2c6 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - pmic@60 { reg = <0x60>; compatible = "maxim,max77826"; @@ -300,9 +294,6 @@ &blsp2_i2c6 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_pins>; - fuelgauge@36 { compatible = "maxim,max17048"; reg = <0x36>; @@ -667,24 +658,21 @@ vmmc-supply = <&pma8084_l20>; vqmmc-supply = <&pma8084_s4>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; }; &sdhc_2 { status = "okay"; max-frequency = <100000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_pin_a>; - vmmc-supply = <&vreg_wlan>; vqmmc-supply = <&pma8084_s4>; - non-removable; - #address-cells = <1>; - #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; wifi@1 { reg = <1>; @@ -702,7 +690,6 @@ &sdhc_3 { status = "okay"; max-frequency = <100000000>; - vmmc-supply = <&pma8084_l21>; vqmmc-supply = <&pma8084_l13>; @@ -712,11 +699,12 @@ * cd-gpios the driver resorts to polling, so hotplug works. */ pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; + pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>; /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ }; &tlmm { + /* This seems suspicious, but somebody with this device should look into it. */ blsp2_uart2_pins_active: blsp2-uart2-pins-active { pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "blsp_uart8"; @@ -746,7 +734,7 @@ }; }; - sdhc1_pin_a: sdhc1-pin-active { + sdc1_on: sdhc1-on { clk { pins = "sdc1_clk"; drive-strength = <4>; @@ -760,17 +748,14 @@ }; }; - sdhc2_pin_a: sdhc2-pin-active { - clk-cmd-data { - pins = "gpio35", "gpio36", "gpio37", "gpio38", - "gpio39", "gpio40"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; + sdc3_on: sdc3-on { + pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; }; - sdhc2_cd_pin: sdhc2-cd { + sdhc3_cd_pin: sdc3-cd-on { pins = "gpio62"; function = "gpio"; @@ -778,7 +763,7 @@ bias-disable; }; - sdhc3_pin_a: sdhc3-pin-active { + sdc2_on: sdhc2-on { clk { pins = "sdc2_clk"; drive-strength = <6>; @@ -792,36 +777,6 @@ }; }; - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c6_pins: i2c6 { - mux { - pins = "gpio29", "gpio30"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c12_pins: i2c12 { - mux { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - - drive-strength = <2>; - bias-disable; - }; - }; - i2c_touchkey_pins: i2c-touchkey { mux { pins = "gpio95", "gpio96"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index b8b6447b3217..465d01da9d69 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -99,18 +99,12 @@ &blsp1_uart2 { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; }; &blsp2_i2c2 { status = "okay"; clock-frequency = <355000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_pins>; - synaptics@2c { compatible = "syna,rmi4-i2c"; reg = <0x2c>; @@ -146,9 +140,6 @@ status = "okay"; clock-frequency = <355000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - lp8566_wled: backlight@2c { compatible = "ti,lp8556"; reg = <0x2c>; @@ -207,17 +198,12 @@ &blsp2_uart1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart7_pin_a>; - bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <3000000>; pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_pin>, - <&bt_dev_wake_pin>, - <&bt_reg_on_pin>; + pinctrl-0 = <&bt_host_wake_pin>, <&bt_dev_wake_pin>, <&bt_reg_on_pin>; host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; @@ -478,8 +464,9 @@ vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; }; &sdhc_2 { @@ -490,8 +477,9 @@ cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; }; &sdhc_3 { @@ -502,7 +490,7 @@ non-removable; pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_pin_a>; + pinctrl-0 = <&sdc3_on>; #address-cells = <1>; #size-cells = <0>; @@ -530,78 +518,6 @@ }; &tlmm { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - blsp2_uart7_pin_a: blsp2-uart7-pin-active { - tx { - pins = "gpio41"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio42"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-pull-up; - }; - - cts { - pins = "gpio43"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-pull-up; - }; - - rts { - pins = "gpio44"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c8_pins: i2c8 { - mux { - pins = "gpio47", "gpio48"; - function = "blsp_i2c8"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - - drive-strength = <2>; - bias-disable; - }; - }; - lcd_backlight_en_pin_a: lcd-backlight-vddio { pins = "gpio69"; drive-strength = <10>; @@ -609,7 +525,7 @@ bias-disable; }; - sdhc1_pin_a: sdhc1-pin-active { + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; drive-strength = <16>; @@ -623,15 +539,7 @@ }; }; - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { + sdc2_on: sdc2-on { clk { pins = "sdc2_clk"; drive-strength = <6>; @@ -643,13 +551,19 @@ drive-strength = <6>; bias-pull-up; }; + + cd { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; - sdhc3_pin_a: sdhc3-pin-active { + sdc3_on: sdc3-on { clk { pins = "gpio40"; function = "sdc3"; - drive-strength = <10>; bias-disable; }; @@ -657,7 +571,6 @@ cmd { pins = "gpio39"; function = "sdc3"; - drive-strength = <10>; bias-pull-up; }; @@ -665,27 +578,22 @@ data { pins = "gpio35", "gpio36", "gpio37", "gpio38"; function = "sdc3"; - drive-strength = <10>; bias-pull-up; }; }; - ts_int_pin: synaptics { - pin { - pins = "gpio86"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; + ts_int_pin: ts-int-pin { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; }; bt_host_wake_pin: bt-host-wake { pins = "gpio95"; function = "gpio"; - drive-strength = <2>; bias-disable; output-low; @@ -694,7 +602,6 @@ bt_dev_wake_pin: bt-dev-wake { pins = "gpio96"; function = "gpio"; - drive-strength = <2>; bias-disable; }; From 09db313d392b42a3a356867d84dc933bcb4556ef Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:30 +0200 Subject: [PATCH 438/791] ARM: dts: qcom-msm8974*: Clean up old GPIO declarations Remove unneeded level of nesting, as it does not match the current DTS style. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-21-konrad.dybcio@somainline.org --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 21 +++----- .../dts/qcom-msm8974-sony-xperia-rhine.dtsi | 13 ++--- .../boot/dts/qcom-msm8974pro-samsung-klte.dts | 53 +++++++------------ 3 files changed, 33 insertions(+), 54 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 7e4e723f1dc3..52b3f055e834 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -573,12 +573,10 @@ }; mpu6515_pin: mpu6515 { - irq { - pins = "gpio73"; - function = "gpio"; - bias-disable; - input-enable; - }; + pins = "gpio73"; + function = "gpio"; + bias-disable; + input-enable; }; touch_pin: touch { @@ -601,13 +599,10 @@ }; panel_pin: panel { - te { - pins = "gpio12"; - function = "mdp_vsync"; - - drive-strength = <2>; - bias-disable; - }; + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; }; bt_pin: bt { diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index c2e423d2a21e..1120972ae4d2 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -375,14 +375,11 @@ &tlmm { ts_int_pin: touch-int { - pin { - pins = "gpio61"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; }; sdc1_on: sdc1-on { diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts index c8151a665ea7..edf374da352a 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -778,50 +778,37 @@ }; i2c_touchkey_pins: i2c-touchkey { - mux { - pins = "gpio95", "gpio96"; - function = "gpio"; - input-enable; - bias-pull-up; - }; + pins = "gpio95", "gpio96"; + function = "gpio"; + input-enable; + bias-pull-up; }; i2c_led_gpioex_pins: i2c-led-gpioex { - mux { - pins = "gpio120", "gpio121"; - function = "gpio"; - input-enable; - bias-pull-down; - }; + pins = "gpio120", "gpio121"; + function = "gpio"; + input-enable; + bias-pull-down; }; gpioex_pin: gpioex { - res { - pins = "gpio145"; - function = "gpio"; - - bias-pull-up; - drive-strength = <2>; - }; + pins = "gpio145"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; wifi_pin: wifi { - int { - pins = "gpio92"; - function = "gpio"; - - input-enable; - bias-pull-down; - }; + pins = "gpio92"; + function = "gpio"; + input-enable; + bias-pull-down; }; panel_te_pin: panel { - te { - pins = "gpio12"; - function = "mdp_vsync"; - - drive-strength = <2>; - bias-disable; - }; + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; }; }; From e82be679de942decbcdaac82aecbcd1277e03fd1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:31 +0200 Subject: [PATCH 439/791] ARM: dts: qcom-msm8974-rhine: Add NFC and enable I2C hosts Enable I2C hosts that are (supposed to be) used on Rhine and add NXP PN544 NFC node. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-22-konrad.dybcio@somainline.org --- .../dts/qcom-msm8974-sony-xperia-rhine.dtsi | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 1120972ae4d2..15beb9df3631 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -85,6 +85,22 @@ }; }; +&blsp1_i2c6 { + status = "okay"; + clock-frequency = <355000>; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <59 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&pm8941_gpios 23 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -93,6 +109,13 @@ qcom,controlled-remotely; }; +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + /* sii8334 MHL HDMI bridge */ +}; + &otg { status = "okay"; From e63d4c51997af75cdf3f096c333a957b4579e43a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:32 +0200 Subject: [PATCH 440/791] ARM: dts: qcom-msm8974-rhine: Add pstore node Add pstore node to allow for retrieving crash logs. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-23-konrad.dybcio@somainline.org --- .../boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 15beb9df3631..91082d31f3c6 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -49,6 +49,22 @@ linux,code = ; }; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@3e8e0000 { + compatible = "ramoops"; + reg = <0x3e8e0000 0x200000>; + + console-size = <0x100000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x80000>; + }; + }; }; &blsp1_i2c2 { From 4b6a151f17cbea6e9bd5b043d0e6e7d19b77c3f7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 Apr 2022 13:56:33 +0200 Subject: [PATCH 441/791] ARM: dts: qcom-msm8974*: Remove unnecessary include gpio.h is already included in the SoC DTSI. Don't include it again. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415115633.575010-24-konrad.dybcio@somainline.org --- arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 1 - arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 1 - arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi | 1 - arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts | 1 - arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 1 - 5 files changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 7ae0b15e50f9..2b9c5a87b014 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -1,7 +1,6 @@ #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" -#include #include #include diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 52b3f055e834..9493886a5c0d 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -2,7 +2,6 @@ #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" -#include #include #include diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 91082d31f3c6..1d21de46f85c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -2,7 +2,6 @@ #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" -#include #include #include diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts index edf374da352a..d6b2300a8223 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" #include "qcom-pma8084.dtsi" -#include #include #include #include diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 465d01da9d69..34aed41856a6 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -1,7 +1,6 @@ #include "qcom-msm8974pro.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" -#include #include #include From d1ba2b36b25a8ecbd9ca898d23488bf8c9c83a09 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:27 +0200 Subject: [PATCH 442/791] ARM: dts: nuvoton: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220407143127.295008-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/nuvoton-npcm730-gbs.dts | 6 +++--- arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 2 +- arch/arm/boot/dts/nuvoton-npcm730-kudo.dts | 6 +++--- arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 8 ++++---- arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts | 6 +++--- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts index eb6eb21cb2a4..d10669fcd527 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts @@ -358,7 +358,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -406,7 +406,7 @@ pinctrl-0 = <&spi3_pins>, <&spi3cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -416,7 +416,7 @@ m25p,fast-read; label = "pnor"; }; - spi-nor@1 { + flash@1 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts index d4ff49939a3d..491606c4f044 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts @@ -135,7 +135,7 @@ pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts index 82a104b2a65f..a0c2d7652625 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts @@ -380,7 +380,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -415,7 +415,7 @@ }; }; }; - spi-nor@1 { + flash@1 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -440,7 +440,7 @@ &fiu3 { pinctrl-0 = <&spi3_pins>; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts index 0334641f8829..3dad32834e5e 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -67,7 +67,7 @@ &fiu0 { status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -128,7 +128,7 @@ &fiu3 { pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -324,7 +324,7 @@ &spi0 { cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; status = "okay"; - Flash@0 { + flash@0 { compatible = "winbond,w25q128", "jedec,spi-nor"; reg = <0x0>; @@ -345,7 +345,7 @@ &spi1 { cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; status = "okay"; - Flash@0 { + flash@0 { compatible = "winbond,w25q128fw", "jedec,spi-nor"; reg = <0x0>; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts index 767e0ac0df7c..132e702281fc 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts @@ -100,7 +100,7 @@ pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -139,7 +139,7 @@ }; }; - spi-nor@1 { + flash@1 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -166,7 +166,7 @@ pinctrl-0 = <&spi3_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; From d8e5c884cca3b3ca11ddf25694c503d1952031b3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:33:04 +0200 Subject: [PATCH 443/791] ARM: dts: omap: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220407143304.295610-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 2 +- arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi | 2 +- arch/arm/boot/dts/am335x-phycore-som.dtsi | 2 +- arch/arm/boot/dts/am335x-sl50.dts | 2 +- arch/arm/boot/dts/am3874-iceboard.dts | 2 +- arch/arm/boot/dts/am437x-cm-t43.dts | 2 +- arch/arm/boot/dts/am437x-idk-evm.dts | 2 +- arch/arm/boot/dts/am437x-sk-evm.dts | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/am574x-idk.dts | 2 +- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 2 +- arch/arm/boot/dts/am57xx-idk-common.dtsi | 2 +- arch/arm/boot/dts/dra7-evm-common.dtsi | 2 +- arch/arm/boot/dts/dra72-evm-common.dtsi | 2 +- arch/arm/boot/dts/dra76-evm.dts | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 11e8f64b6606..92a0e98ec231 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -182,7 +182,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - m25p80@0 { + flash@0 { compatible = "mx25l6405d"; spi-max-frequency = <40000000>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index a7269b90d795..e7e439a0630a 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -394,7 +394,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - m25p80@0 { + flash@0 { compatible = "mx25l6405d"; spi-max-frequency = <40000000>; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index f65cd1331315..e2cec1ffaa4c 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -331,7 +331,7 @@ pinctrl-0 = <&spi0_pins>; status = "okay"; - serial_flash: m25p80@0 { + serial_flash: flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <48000000>; reg = <0x0>; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 6516907ed579..73b5d1a024bd 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -588,7 +588,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - flash: n25q032@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q032"; diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index 9423e9feaa10..c9323d1df303 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -434,7 +434,7 @@ }; &mcspi1 { - s25fl256@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 3e3354780db8..0861e868b75a 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -302,7 +302,7 @@ &edma 17 0>; dma-names = "tx0", "rx0"; - flash: w25q64cvzpig@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 53f64e3ce735..5a74b83145cf 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -437,7 +437,7 @@ pinctrl-1 = <&qspi_pins_sleep>; spi-max-frequency = <48000000>; - m25p80@0 { + flash@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 20a34d2d85df..0bc391243816 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -746,7 +746,7 @@ pinctrl-0 = <&qspi_pins>; spi-max-frequency = <48000000>; - m25p80@0 { + flash@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 4f9a7251a107..1165804658bc 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -902,7 +902,7 @@ pinctrl-1 = <&qspi1_pins_sleep>; spi-max-frequency = <48000000>; - m25p80@0 { + flash@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index 6dff3660bf09..47b9174d2353 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -18,7 +18,7 @@ &qspi { spi-max-frequency = <96000000>; - m25p80@0 { + flash@0 { spi-max-frequency = <96000000>; }; }; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 2e94f32d9dfc..2fc9a5d5e0c0 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -491,7 +491,7 @@ spi-max-frequency = <48000000>; - spi_flash: spi_flash@0 { + spi_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 9fcb8944aa3e..c06eda817242 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -526,7 +526,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1", "jedec,spi-nor"; spi-max-frequency = <76800000>; reg = <0>; diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 0f71a9f37a72..68c43eb12c1a 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -135,7 +135,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index f12825268188..8948e10dbeb8 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -474,7 +474,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index e2b7fcb061cf..57868ac60d29 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -511,7 +511,7 @@ &qspi { spi-max-frequency = <96000000>; - m25p80@0 { + flash@0 { spi-max-frequency = <96000000>; }; }; From 89e73afc3f54059c3baabf45d935fd333ee5b55e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:33 +0200 Subject: [PATCH 444/791] ARM: dts: marvell: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220407143234.295426-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/armada-370-db.dts | 2 +- arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi | 2 +- arch/arm/boot/dts/armada-370-synology-ds213j.dts | 2 +- arch/arm/boot/dts/armada-375-db.dts | 2 +- arch/arm/boot/dts/armada-381-netgear-gs110emx.dts | 2 +- arch/arm/boot/dts/armada-385-atl-x530.dts | 2 +- arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi | 2 +- arch/arm/boot/dts/armada-385-db-88f6820-amc.dts | 2 +- arch/arm/boot/dts/armada-385-db-ap.dts | 2 +- arch/arm/boot/dts/armada-385-synology-ds116.dts | 2 +- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 +- arch/arm/boot/dts/armada-388-db.dts | 2 +- arch/arm/boot/dts/armada-388-gp.dts | 2 +- arch/arm/boot/dts/armada-388-rd.dts | 2 +- arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 2 +- arch/arm/boot/dts/armada-390-db.dts | 2 +- arch/arm/boot/dts/armada-398-db.dts | 2 +- arch/arm/boot/dts/armada-xp-axpwifiap.dts | 2 +- arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts | 2 +- arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi | 2 +- arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts | 2 +- arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi | 2 +- arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts | 2 +- arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi | 2 +- arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 2 +- arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 2 +- arch/arm/boot/dts/armada-xp-db.dts | 2 +- arch/arm/boot/dts/armada-xp-gp.dts | 2 +- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 2 +- arch/arm/boot/dts/armada-xp-synology-ds414.dts | 2 +- arch/arm/boot/dts/dove-cubox.dts | 2 +- arch/arm/boot/dts/dove-d2plug.dts | 2 +- arch/arm/boot/dts/dove-d3plug.dts | 2 +- arch/arm/boot/dts/dove-dove-db.dts | 2 +- arch/arm/boot/dts/kirkwood-dir665.dts | 2 +- arch/arm/boot/dts/kirkwood-synology.dtsi | 2 +- 36 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 77261a2fb949..a7dc4c04d10b 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -203,7 +203,7 @@ pinctrl-names = "default"; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mx25l25635e", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi index a624b2371fb6..0abac5ffe45a 100644 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi @@ -159,7 +159,7 @@ pinctrl-0 = <&spi0_pins2>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; /* MX25L8006E */ diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index 64f2ce254fb6..e72b8ed4b997 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -258,7 +258,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q064", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 0e679465cbb5..4c4092790a20 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -64,7 +64,7 @@ status = "disabled"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts index 0a961116a1f9..396172067f6a 100644 --- a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts +++ b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts @@ -242,7 +242,7 @@ pinctrl-names = "default"; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/armada-385-atl-x530.dts index ed3f41c7df71..241f5d7c80e9 100644 --- a/arch/arm/boot/dts/armada-385-atl-x530.dts +++ b/arch/arm/boot/dts/armada-385-atl-x530.dts @@ -168,7 +168,7 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; - spi-flash@1 { + flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi index 624bbcae68c0..10ad46f29393 100644 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi @@ -365,7 +365,7 @@ pinctrl-names = "default"; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <0>; compatible = "w25q32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts index 7881df3b28a0..389d9c75d546 100644 --- a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts +++ b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts @@ -126,7 +126,7 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 0e4613bb56ee..332f8fce77dc 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -192,7 +192,7 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts index d8769956cbfc..2622af73c9da 100644 --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts +++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts @@ -223,7 +223,7 @@ pinctrl-0 = <&spi0_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "macronix,mx25l6405d", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index f240018148f6..c9ff3f8c5e58 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -485,7 +485,7 @@ pinctrl-0 = <&spi0_pins &spi0cs0_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "spansion,s25fl164k", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts index a2bec07bf4c5..5130eccc32af 100644 --- a/arch/arm/boot/dts/armada-388-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -133,7 +133,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25q32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index 9d873257ac45..e2ba50520b6b 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -395,7 +395,7 @@ pinctrl-0 = <&spi0_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts index 328a4d6afd2c..c0efafd45b33 100644 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -97,7 +97,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi index 363ac4238859..2c64bc6e5a17 100644 --- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi @@ -101,7 +101,7 @@ /* The microsom has an optional W25Q32 on board, connected to CS0 */ pinctrl-0 = <&spi1_pins>; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25q32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts index 0e29474ae9a2..792d0a0184e8 100644 --- a/arch/arm/boot/dts/armada-390-db.dts +++ b/arch/arm/boot/dts/armada-390-db.dts @@ -81,7 +81,7 @@ pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; - spi-flash@1 { + flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts index fc28308e5bc5..ec6cdbeedde7 100644 --- a/arch/arm/boot/dts/armada-398-db.dts +++ b/arch/arm/boot/dts/armada-398-db.dts @@ -79,7 +79,7 @@ pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <0>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index 606fd3476a59..3e77b4337802 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -134,7 +134,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts index a022c68dc943..c28e140b4afc 100644 --- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts @@ -15,7 +15,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi index 32fb21b2bf6a..47b003a81bd4 100644 --- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi @@ -80,7 +80,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts index 21f442afab1f..20ba5c823bb2 100644 --- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts @@ -15,7 +15,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi index f3e1a25ca5f2..cab99d8e2911 100644 --- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi @@ -80,7 +80,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts index e05aee6cdc04..2caa3980fdf6 100644 --- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts @@ -15,7 +15,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi index c8b1355ce15e..7028482ce4b2 100644 --- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi @@ -80,7 +80,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts index 8a3aa616bbd0..02bef8dc4270 100644 --- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts +++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts @@ -93,7 +93,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p64"; diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts index 4ec0ae01b61d..d1b61dad0c46 100644 --- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts +++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts @@ -89,7 +89,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p64"; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 5d04dc68cf57..75318fd0fc11 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -235,7 +235,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p64", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index b4cca507cf13..d1d348b91c0a 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -220,7 +220,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 8480a16919a0..36932e3b781a 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -255,7 +255,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "everspin,mr25h256"; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index 809e821d7399..5551bac1962c 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -274,7 +274,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q064", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 3e1584e787ae..2639b9fe0ab4 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -127,7 +127,7 @@ status = "okay"; /* spi0.0: 4M Flash Winbond W25Q32BV */ - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts index 273f12ca2512..a0e8996c2ffd 100644 --- a/arch/arm/boot/dts/dove-d2plug.dts +++ b/arch/arm/boot/dts/dove-d2plug.dts @@ -62,7 +62,7 @@ status = "okay"; /* spi0.0: 4M Flash Macronix MX25L3205D */ - spi-flash@0 { + flash@0 { compatible = "st,m25l3205d"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts index 826026c28f90..1e81d1b97055 100644 --- a/arch/arm/boot/dts/dove-d3plug.dts +++ b/arch/arm/boot/dts/dove-d3plug.dts @@ -79,7 +79,7 @@ status = "okay"; /* spi0.0: 2M Flash Macronix MX25L1605D */ - spi-flash@0 { + flash@0 { compatible = "st,m25l1605d"; spi-max-frequency = <86000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts index 1754a62e014e..c1912dc6bfc3 100644 --- a/arch/arm/boot/dts/dove-dove-db.dts +++ b/arch/arm/boot/dts/dove-dove-db.dts @@ -27,7 +27,7 @@ status = "okay"; /* spi0.0: 4M Flash ST-M25P32-VMF6P */ - spi-flash@0 { + flash@0 { compatible = "st,m25p32"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts index b3ad3f607d31..c32300611d2c 100644 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -78,7 +78,7 @@ spi@10600 { status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 217bd374e52b..8f6c387d3a8b 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -198,7 +198,7 @@ spi@10600 { status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80", "jedec,spi-nor"; From f5582834f3809292f98e4b471e0756b1f9d0e78d Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:25 +0100 Subject: [PATCH 445/791] ARM: dts: omap3/4/5: fix ethernet node name for different OMAP boards The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Message-Id: <20220216074927.3619425-8-o.rempel@pengutronix.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-beagle-xm.dts | 2 +- arch/arm/boot/dts/omap4-panda-common.dtsi | 2 +- arch/arm/boot/dts/omap5-igep0050.dts | 2 +- arch/arm/boot/dts/omap5-uevm.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index a858ebfa1500..35eced6521ef 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -370,7 +370,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 609a8dea946b..518652a599bd 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -558,7 +558,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 76e499d89d24..3851120857d7 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -128,7 +128,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@3 { + ethernet: ethernet@3 { compatible = "usb424,7500"; reg = <3>; }; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 51d5fcae5081..453da9f18a99 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -209,7 +209,7 @@ #size-cells = <0>; }; - ethernet: usbether@3 { + ethernet: ethernet@3 { compatible = "usb424,9730"; reg = <3>; }; From f41f5a993395d1e05d9400998c6ab1d737dbec6b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 3 Mar 2022 11:18:18 -0600 Subject: [PATCH 446/791] ARM: dts: logicpd-som-lv: Move pinmuxing to peripheral nodes Move some pinmux references to their respective peripherals. This keeps the pins in safe-mode until they are requested. Signed-off-by: Adam Ford Message-Id: <20220303171818.11060-2-aford173@gmail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-som-lv.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index b56524cc7fe2..5475e5de3d78 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -27,6 +27,8 @@ /* HS USB Host PHY on PORT 1 */ hsusb2_phy: hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_reset_pin>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ #phy-cells = <0>; @@ -144,6 +146,8 @@ }; &usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>; port2-mode = "ehci-phy"; }; @@ -151,10 +155,7 @@ phys = <0 &hsusb2_phy>; }; - &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; mmc3_pins: pinmux_mm3_pins { pinctrl-single,pins = < @@ -250,8 +251,7 @@ }; &omap3_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; + hsusb2_reset_pin: pinmux_hsusb1_reset_pin { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ From bbcd3f73e83ed1303b8a3afd9bf437da536d6412 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:05:59 +0000 Subject: [PATCH 447/791] ARM: dts: am335x: Guardian: Update NAND partition table * Update partition table to save env and splash image * GPMC config values optimized for Bosch Guardian Board * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-2-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 65 ++++++++++++++++++++------- 1 file changed, 48 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 1918766c1f80..41b7adf78656 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -133,28 +133,29 @@ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; + gpmc,we-off-ns = <15>; + gpmc,oe-on-ns = <1>; + gpmc,oe-off-ns = <15>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; + gpmc,wr-access-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* @@ -198,18 +199,33 @@ }; partition@6 { - label = "u-boot-env"; - reg = <0x300000 0x40000>; + label = "u-boot-2"; + reg = <0x300000 0x100000>; }; partition@7 { - label = "u-boot-env.backup1"; - reg = <0x340000 0x40000>; + label = "u-boot-2.backup1"; + reg = <0x400000 0x100000>; }; partition@8 { + label = "u-boot-env"; + reg = <0x500000 0x40000>; + }; + + partition@9 { + label = "u-boot-env.backup1"; + reg = <0x540000 0x40000>; + }; + + partition@10 { + label = "splash-screen"; + reg = <0x580000 0x40000>; + }; + + partition@11 { label = "UBI"; - reg = <0x380000 0x1fc80000>; + reg = <0x5c0000 0x1fa40000>; }; }; }; @@ -470,20 +486,35 @@ nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < + /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) + /* (V7) gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) + /* (R8) gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) + /* (T8) gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) + /* (U8) gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) + /* (V8) gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) + /* (R9) gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) + /* (T9) gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) + /* (T17) gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) + /* (U17) gpmc_wpn.gpmc_wpn */ AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) + /* (V6) gpmc_csn0.gpmc_csn0 */ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) + /* (R7) gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) + /* (T7) gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) + /* (U6) gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) + /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) >; }; From 062859b506ba393997f06a96f40eb6041f6b4c6c Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:00 +0000 Subject: [PATCH 448/791] ARM: dts: am335x: Guardian: Rename power button label * Rename label button to power button Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-3-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 41b7adf78656..645de77bdb56 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -29,21 +29,22 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - gpio_keys { + guardian_buttons: gpio-keys { + pinctrl-names = "default"; + pinctrl-0 = <&guardian_button_pins>; compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - button21 { + power-button { label = "guardian-power-button"; linux,code = ; - gpios = <&gpio2 21 0>; + gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; wakeup-source; }; }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -365,9 +366,9 @@ >; }; - gpio_keys_pins: pinmux_gpio_keys_pins { + guardian_button_pins: pinmux_guardian_button_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ >; }; From 87e4e2bf90fbed8b9e73d80be387aabced5a39a3 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:01 +0000 Subject: [PATCH 449/791] ARM: dts: am335x: Guardian: Add keypad * Add support to guardian mt gpio keypad Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-4-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 645de77bdb56..6f59c5f36c0d 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -36,6 +36,13 @@ #address-cells = <1>; #size-cells = <0>; + select-button { + label = "guardian-select-button"; + linux,code = ; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + power-button { label = "guardian-power-button"; linux,code = ; @@ -115,6 +122,22 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + mt_keypad: mt_keypad@0 { + compatible = "gpio-mt-keypad"; + debounce-delay-ms = <10>; + col-scan-delay-us = <2>; + keypad,num-lines = <5>; + linux,no-autorepeat; + gpio-activelow; + line-gpios = < + &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/ + &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/ + &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/ + &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/ + &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/ + >; + }; }; &elm { @@ -369,6 +392,7 @@ guardian_button_pins: pinmux_guardian_button_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ >; }; From d8da0fd615172671f7245795e8d82ac8cce97667 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:02 +0000 Subject: [PATCH 450/791] ARM: dts: am335x: Guardian: Disable poweroff support from RTC * Disabling poweroff support form RTC will allow poweroff to handle from other machanism Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-5-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 6f59c5f36c0d..46314f1bc85b 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -282,7 +282,6 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; - system-power-controller; }; &spi0 { From 42c83b73aea112ba4341467bec58a3b3e44fa822 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:03 +0000 Subject: [PATCH 451/791] ARM: dts: am335x: Guardian: Remove mmc status led * MMC presence indicater LED removed from Guardian Board Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-6-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 46314f1bc85b..749239081bf1 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -51,7 +51,6 @@ }; }; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -63,13 +62,6 @@ linux,default-trigger = "heartbeat"; default-state = "off"; }; - - led2 { - label = "green:mmc0"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; }; panel { @@ -475,7 +467,6 @@ leds_pins: pinmux_leds_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) >; }; From 6794adf4a2aac7243d17a2420e00146f083116bd Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:04 +0000 Subject: [PATCH 452/791] ARM: dts: am335x: Guardian: Update life led * update life led label and pin number Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-7-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 749239081bf1..68443c59aba4 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -51,14 +51,14 @@ }; }; - leds { - compatible = "gpio-leds"; + guardian_leds: gpio-leds { pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; + pinctrl-0 = <&guardian_led_pins>; + compatible = "gpio-leds"; - led1 { - label = "green:heartbeat"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + life-led { + label = "guardian:life-led"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; @@ -465,9 +465,9 @@ >; }; - leds_pins: pinmux_leds_pins { + guardian_led_pins: pinmux_guardian_led_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ >; }; From b5bf6b434575d32aeaa70c82ec84b3cec92e2973 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:05 +0000 Subject: [PATCH 453/791] ARM: dts: am335x: Guardian: Update beeper label * Update lable pwm to guardian beeper Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-8-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 68443c59aba4..ed4cd51dd838 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -100,11 +100,11 @@ }; - pwm7: dmtimer-pwm { + guardian_beeper: dmtimer-pwm@7 { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer7>; pinctrl-names = "default"; - pinctrl-0 = <&dmtimer7_pins>; + pinctrl-0 = <&guardian_beeper_pins>; ti,clock-source = <0x01>; }; @@ -374,9 +374,9 @@ >; }; - dmtimer7_pins: pinmux_dmtimer7_pins { + guardian_beeper_pins: pinmux_dmtimer7_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ >; }; From 228e0021e73337c37536603900332fdb59246d5c Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:06 +0000 Subject: [PATCH 454/791] ARM: dts: am335x: Guardian: Update regulator node name * Update mmcsd voltage regulator node name Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-9-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index ed4cd51dd838..e0186043f18c 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -108,7 +108,7 @@ ti,clock-source = <0x01>; }; - vmmcsd_fixed: regulator-3v3 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; @@ -303,6 +303,7 @@ }; dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1351500>; @@ -311,6 +312,7 @@ }; dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1150000>; From 677d855707089982e13cad5ddaaddfd03f889217 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:07 +0000 Subject: [PATCH 455/791] ARM: dts: am335x: Guardian: Add lcd port * Add port to the node lcdc Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-10-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 54 +++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index e0186043f18c..75ac8686091a 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -260,6 +260,11 @@ &lcdc { blue-and-red-wiring = "crossed"; status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <0>; + }; + }; }; &mmc1 { @@ -405,64 +410,113 @@ lcd_disen_pins: pinmux_lcd_disen_pins { pinctrl-single,pins = < + /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) >; }; lcd_pins_default: pinmux_lcd_pins_default { pinctrl-single,pins = < + /* (U10) gpmc_ad8.lcd_data23 */ AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T10) gpmc_ad9.lcd_data22 */ AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T11) gpmc_ad10.lcd_data21 */ AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U12) gpmc_ad11.lcd_data20 */ AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T12) gpmc_ad12.lcd_data19 */ AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (R12) gpmc_ad13.lcd_data18 */ AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (V13) gpmc_ad14.lcd_data17 */ AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U13) gpmc_ad15.lcd_data16 */ AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_ac_bias_en.lcd_ac_bias_en */ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) >; }; lcd_pins_sleep: pinmux_lcd_pins_sleep { pinctrl-single,pins = < + /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_ac_bias_en.lcd_ac_bias_en */ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) >; }; From 60f68df3971b7314bdf7246ca548aac1c12401f5 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:08 +0000 Subject: [PATCH 456/791] ARM: dts: am335x: Guardian: Update backlight parameter * Update default brightness and dimming frequency * Enable current sink, while initialization Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-11-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 31 +++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 75ac8686091a..fab844815065 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -291,14 +291,34 @@ #include "tps65217.dtsi" &tps { + /* + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only + * mode") at poweroff. Most BeagleBone versions do not support RTC-only + * mode and risk hardware damage if this mode is entered. + * + * For details, see linux-omap mailing list May 2015 thread + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller + * In particular, messages: + * http://www.spinics.net/lists/linux-omap/msg118585.html + * http://www.spinics.net/lists/linux-omap/msg118615.html + * + * You can override this later with + * &tps { /delete-property/ ti,pmic-shutdown-controller; } + * if you want to use RTC-only mode and made sure you are not affected + * by the hardware problems. (Tip: double-check by performing a current + * measurement after shutdown: it should be less than 1 mA.) + */ ti,pmic-shutdown-controller; interrupt-parent = <&intc>; interrupts = <7>; /* NMI */ backlight { isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ - default-brightness = <100>; + fdim = <500>; /* TPS65217_BL_FDIM_500HZ */ + default-brightness = <50>; + /* 1(on) - enable current sink, while initialization */ + /* 0(off) - disable current sink, while initialization */ + isink-en = <1>; }; regulators { @@ -408,6 +428,13 @@ >; }; + led_bl_pins: gpio_led_bl_pins { + pinctrl-single,pins = < + /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) + >; + }; + lcd_disen_pins: pinmux_lcd_disen_pins { pinctrl-single,pins = < /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ From 2d983a375511bfd8dd2e8df0a3add9fe36484944 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:09 +0000 Subject: [PATCH 457/791] ARM: dts: am335x: Guardian: Enable UART port two * Add support for uart2 port Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-12-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index fab844815065..9f60f5430f36 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -383,6 +383,12 @@ status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + &usb0 { dr_mode = "peripheral"; }; @@ -582,6 +588,15 @@ >; }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + /* K18 uart2_rxd.mirx_txd */ + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) + /* L18 uart2_txd.mirx_rxd */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) + >; + }; + nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < /* (U7) gpmc_ad0.gpmc_ad0 */ From 783bc2bb4fb10bcc3a9dec14561e9fe2599865f5 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:10 +0000 Subject: [PATCH 458/791] ARM: dts: am335x: Guardian: Disable DMA property of USB1 * Dispble DMA property of USB1 Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-13-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 9f60f5430f36..93576f136368 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -395,6 +395,8 @@ &usb1 { dr_mode = "host"; + /delete-property/dmas; + /delete-property/dma-names; }; &am33xx_pinmux { From 6e049b9a42108eeae494a370b3ea8bb46ade0674 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:11 +0000 Subject: [PATCH 459/791] ARM: dts: am335x: Guardian: Update interface pinmux * Update interface pinmux for - poweroff button - battery and coincell enable - ASP and Miraculix Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-14-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 44 ++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 93576f136368..b225210d5e11 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -64,6 +64,11 @@ }; }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + panel { compatible = "ti,tilcdc,panel"; pinctrl-names = "default", "sleep"; @@ -401,14 +406,45 @@ &am33xx_pinmux { pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin &gpio_pins>; + pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < + /* xdma_event_intr1.clkout2 */ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) >; }; + guardian_interface_pins: pinmux_interface_pins { + pinctrl-single,pins = < + /* ADC_BATSENSE_EN */ + /* (A14) MCASP0_AHCLKx.gpio3[21] */ + AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ADC_COINCELL_EN */ + /* (J16) MII1_TX_EN.gpio3[3] */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ASP_ENABLE */ + /* (A13) MCASP0_ACLKx.gpio3[14] */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* (D16) uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) + /* (D15) uart1_txd.uart1_txd */ + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) + /*SWITCH-OFF_3V6*/ + /* (M18) gpio0[1] */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* MIRACULIX */ + /* (H17) gmii1_crs.gpio3[1] */ + AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (H18) rmii1_refclk.gpio0[29] */ + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 ) + /* (J17) gmii1_rxdv.gpio3[4] */ + AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + >; + }; + guardian_beeper_pins: pinmux_dmtimer7_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ @@ -422,12 +458,6 @@ >; }; - gpio_pins: pinmux_gpio_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) - >; - }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < From 762217eaf92545d35833e4a6b48fc3e79bb7ef41 Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:12 +0000 Subject: [PATCH 460/791] ARM: dts: am335x: Guardian: Add gpio line manes * assign name to gpio line Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-15-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index b225210d5e11..cc56b4510930 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -382,6 +382,80 @@ }; }; +&gpio0 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MirxWakeup", + "", + ""; +}; + +&gpio3 { + ti,gpio-always-on; + ti,no-reset-on-init; + gpio-line-names = + "", + "MirxBtReset", + "", + "CcVolAdcEn", + "MirxBlePause", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AspEn", + "", + "", + "", + "", + "", + "", + "BatVolAdcEn", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; From 521153f25c2f17a2da0e0785b46143baa3bc2d5a Mon Sep 17 00:00:00 2001 From: Gireesh Hiremath Date: Fri, 25 Mar 2022 10:06:13 +0000 Subject: [PATCH 461/791] ARM: dts: am335x: Guardian: Update comments * Add comment to improve readability Signed-off-by: Gireesh Hiremath Message-Id: <20220325100613.1494-16-Gireesh.Hiremath@in.bosch.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-guardian.dts | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index cc56b4510930..1a7e187b1953 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -535,8 +535,8 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; @@ -668,28 +668,34 @@ mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < + /* SPI0_CLK - spi0_clk.spi */ AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + /* SPI0_MOSI - spi0_d0.spi0 */ AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) + /* SPI0_MISO - spi0_d1.spi0 */ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) + /* SPI0_CS0 - spi */ AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < + /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart0_txd.uart0_txd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; }; From dff844e1fe17e6c41e5899d46a378f857ea4f354 Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Tue, 19 Apr 2022 16:39:23 +0200 Subject: [PATCH 462/791] ARM: dts: am335x-baltos: update MPU regulator range Update the max MPU voltage range to align with the maximum possible value allowed in the operating-points table, which is max target voltage of 132500 uV + 2%. Signed-off-by: Yegor Yefremov Message-Id: <20220419143923.25196-1-yegorslists@googlemail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 366702630290..d3eafee79a23 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -285,7 +285,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; From a044e6a0883bcd4ad71849c97f79fd213e940077 Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Thu, 21 Apr 2022 11:51:08 +0800 Subject: [PATCH 463/791] arm: dts: mediatek: Get rid of mediatek, larb for MM nodes After adding device_link between the IOMMU consumer and smi, the mediatek,larb is unnecessary now. CC: Matthias Brugger Signed-off-by: Yong Wu Signed-off-by: Allen-KH Cheng Reviewed-by: Evan Green Tested-by: Frank Wunderlich # BPI-R2/MT7623 Link: https://lore.kernel.org/r/20220421035111.7267-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 2 -- arch/arm/boot/dts/mt7623n.dtsi | 5 ----- 2 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 4776f85d6d5b..ef583cfd3baf 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -564,7 +564,6 @@ clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -577,7 +576,6 @@ clocks = <&imgsys CLK_IMG_VENC>; clock-names = "jpgenc"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; }; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi index bcb0846e29fd..3adab5cd1fef 100644 --- a/arch/arm/boot/dts/mt7623n.dtsi +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -121,7 +121,6 @@ clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -144,7 +143,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_OVL>; iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; - mediatek,larb = <&larb0>; }; rdma0: rdma@14008000 { @@ -154,7 +152,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_RDMA>; iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; - mediatek,larb = <&larb0>; }; wdma@14009000 { @@ -164,7 +161,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_WDMA>; iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; - mediatek,larb = <&larb0>; }; bls: pwm@1400a000 { @@ -215,7 +211,6 @@ interrupts = ; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb0>; }; dpi0: dpi@14014000 { From 625f5c507994fd8ff9c70b2477902b0e3e1f355f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 20 Apr 2022 11:02:46 +0200 Subject: [PATCH 464/791] ARM: dts: keystone: Align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Nishanth Menon Reviewed-by: Grygorii Strashko Link: https://lore.kernel.org/r/20220420090247.73410-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/keystone-k2e-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2g-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2g-ice.dts | 2 +- arch/arm/boot/dts/keystone-k2hk-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2l-evm.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index 66fec5f5d081..8f49883a675e 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -137,7 +137,7 @@ }; &spi0 { - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "Micron,n25q128a11"; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index d800f26b6275..88be868cf71e 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -392,7 +392,7 @@ pinctrl-0 = <&qspi_pins>; cdns,rclk-en; - flash0: m25p80@0 { + flash0: flash@0 { compatible = "s25fl512s", "jedec,spi-nor"; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts index 2a2d38cf0fff..bd84d7f0f2fe 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -325,7 +325,7 @@ cdns,rclk-en; status = "okay"; - flash0: m25p80@0 { + flash0: flash@0 { compatible = "s25fl256s1", "jedec,spi-nor"; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index ad4e22afe133..f968af0bfad3 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -161,7 +161,7 @@ }; &spi0 { - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "Micron,n25q128a11"; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index e200533d26a4..32619b3c5804 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -110,7 +110,7 @@ }; &spi0 { - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "Micron,n25q128a11"; From 6273a1864d437553ab4220d1abc010c5bb758ad2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 20 Apr 2022 11:02:47 +0200 Subject: [PATCH 465/791] ARM: dts: keystone: Fix missing fallback and case in SPI NOR node compatible Vendor prefix in compatible should be lower-case and the jedec,spi-nor should be used as fallback, according to the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20220420090247.73410-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/keystone-k2e-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2hk-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2l-evm.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index 8f49883a675e..5d6d074011df 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -140,7 +140,7 @@ nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index f968af0bfad3..4a91f5ded402 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -164,7 +164,7 @@ nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index 32619b3c5804..1c880cf8fa91 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -113,7 +113,7 @@ nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; From ad984c428c311a7df4b33c038be40d795a9299bf Mon Sep 17 00:00:00 2001 From: William Zhang Date: Wed, 13 Apr 2022 12:26:41 -0700 Subject: [PATCH 466/791] dt-bindings: arm: add bcmbca device tree binding document Add arch bcmbca device tree binding document for Broadcom ARM based broadband SoC chipsets. In this change, only BCM47622 is added. Other chipsets will be added in the future. Signed-off-by: William Zhang Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- .../bindings/arm/bcm/brcm,bcmbca.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml new file mode 100644 index 000000000000..5fb455840417 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC device tree bindings + +description: + Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless + chips that can be used as home gateway, router and WLAN AP for residential, + enterprise and carrier applications. + +maintainers: + - William Zhang + - Anand Gore + - Kursad Oney + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM47622 based boards + items: + - enum: + - brcm,bcm947622 + - const: brcm,bcm47622 + - const: brcm,bcmbca + +additionalProperties: true + +... From 643661e0033632658862d73247665099db40fbd3 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Wed, 13 Apr 2022 12:26:43 -0700 Subject: [PATCH 467/791] ARM: dts: add dts files for bcmbca soc 47622 Add dts for ARMv7 based broadband SoC BCM47622. bcm47622.dtsi is the SoC description dts header and bcm947622.dts is a simple dts file for Broadcom BCM947622 Reference board that only enable the UART port. Signed-off-by: William Zhang Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm47622.dtsi | 126 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm947622.dts | 30 ++++++++ 3 files changed, 158 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47622.dtsi create mode 100644 arch/arm/boot/dts/bcm947622.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..ff0054d55590 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -179,6 +179,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2q-marvell-dmp.dtb dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi new file mode 100644 index 000000000000..c016e12b7372 --- /dev/null +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm47622", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x818000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts new file mode 100644 index 000000000000..6f083724ab8e --- /dev/null +++ b/arch/arm/boot/dts/bcm947622.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm47622.dtsi" + +/ { + model = "Broadcom BCM947622 Reference Board"; + compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; From 1eae95fb1d696968ca72be3ac8e0d62bb4d8da42 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 13:05:02 +0530 Subject: [PATCH 468/791] arm64: dts: qcom: qrb5165-rb5: Fix can-clock node name Per DT spec node names should not have underscores (_) in them, so change can_clock to can-clock. Fixes: 5c44c564e449 ("arm64: dts: qcom: qrb5165-rb5: Add support for MCP2518FD") Signed-off-by: Vinod Koul Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421073502.1824089-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 845eb7a6bf92..0e63f707b911 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -29,7 +29,7 @@ }; /* Fixed crystal oscillator dedicated to MCP2518FD */ - clk40M: can_clock { + clk40M: can-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <40000000>; From cb29e7106d4ee7bc3860fc65d28b6d7d0b71c0f8 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 13:04:38 +0530 Subject: [PATCH 469/791] arm64: dts: qcom: db845c: Add support for MCP2517FD Add support for onboard MCP2517FD SPI CAN transceiver attached to SPI0 of RB3. Signed-off-by: Vinod Koul Reviewed-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421073438.1824061-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 9206efa9d6d2..194ebeb3259c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -28,6 +28,13 @@ stdout-path = "serial0:115200n8"; }; + /* Fixed crystal oscillator dedicated to MCP2517FD */ + clk40M: can-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + dc12v: dc12v-regulator { compatible = "regulator-fixed"; regulator-name = "DC12V"; @@ -746,6 +753,23 @@ }; }; +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + can@0 { + compatible = "microchip,mcp2517fd"; + reg = <0>; + clocks = <&clk40M>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + }; +}; + &spi2 { /* On Low speed expansion */ label = "LS-SPI0"; @@ -1220,3 +1244,11 @@ }; }; }; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +&qup_spi0_default { + config { + drive-strength = <6>; + bias-disable; + }; +}; From 2a31f958f8326c263f2af2511cd6d8256d81e810 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 19 Apr 2022 02:25:09 +0530 Subject: [PATCH 470/791] arm64: dts: qcom: sm8450: Fix qmp phy node (use phy@ instead of lanes@) Fix the following 'make dtbs_check' warning(s) by using phy@ instead of lanes@: arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: phy@1c0f000: 'lanes@1c0e000' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220418205509.1102109-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 764e4be756db..7f52c3cfdfb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1785,7 +1785,7 @@ status = "disabled"; - pcie0_lane: lanes@1c06200 { + pcie0_lane: phy@1c06200 { reg = <0 0x1c06e00 0 0x200>, /* tx */ <0 0x1c07000 0 0x200>, /* rx */ <0 0x1c06200 0 0x200>, /* pcs */ @@ -1892,7 +1892,7 @@ status = "disabled"; - pcie1_lane: lanes@1c0e000 { + pcie1_lane: phy@1c0e000 { reg = <0 0x1c0e000 0 0x200>, /* tx */ <0 0x1c0e200 0 0x300>, /* rx */ <0 0x1c0f200 0 0x200>, /* pcs */ From c11e239f6aee32e20718dc3cf5349894d0e994ec Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 17:25:24 +0530 Subject: [PATCH 471/791] arm64: dts: qcom: sc7280: Add GPI DMAengines The Qualcomm SC7280 has two GPI DMAengines, add definitions for these. Co-developed-by: Vijaya Krishna Nivarthi Signed-off-by: Vijaya Krishna Nivarthi Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421115526.1828659-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 00bacc4ae4f7..43641db0e7de 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -915,6 +915,28 @@ }; + gpi_dma0: dma-controller@900000 { + #dma-cells = <3>; + compatible = "qcom,sc7280-gpi-dma"; + reg = <0 0x00900000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7f>; + iommus = <&apps_smmu 0x0136 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>; @@ -1344,6 +1366,28 @@ }; }; + gpi_dma1: dma-controller@a00000 { + #dma-cells = <3>; + compatible = "qcom,sc7280-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x1e>; + iommus = <&apps_smmu 0x56 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x2000>; From 18bec7f725c5184f7c5b2a404602dd95f630d4d7 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 17:25:25 +0530 Subject: [PATCH 472/791] arm64: dts: qcom: sc7280: Add GENI I2C/SPI DMA channels The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Co-developed-by: Vijaya Krishna Nivarthi Signed-off-by: Vijaya Krishna Nivarthi Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421115526.1828659-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 97 ++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 43641db0e7de..f72451f7f539 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -964,6 +965,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -982,6 +986,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1016,6 +1023,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1034,6 +1044,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1068,6 +1081,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1086,6 +1102,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1120,6 +1139,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1138,6 +1160,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1172,6 +1197,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1190,6 +1218,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1224,6 +1255,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1242,6 +1276,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1276,6 +1313,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1294,6 +1334,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1328,6 +1371,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1346,6 +1392,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1415,6 +1464,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1433,6 +1485,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1467,6 +1522,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1485,6 +1543,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1519,6 +1580,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1537,6 +1601,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1571,6 +1638,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1589,6 +1659,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1623,6 +1696,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1641,6 +1717,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1675,6 +1754,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1693,6 +1775,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1727,6 +1812,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1745,6 +1833,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1779,6 +1870,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1797,6 +1891,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; From f238ff81e8946540e1a7c1496aa92fa2386893dc Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 17:25:26 +0530 Subject: [PATCH 473/791] arm64: dts: qcom: sc7280-idp: Enable GPI DMAs Some versions of the firmware for the sc7280-idp board FIFO mode disabled and must thus use GPI DMA. Enable gpi_dma0 and gpi_dma1 to allow this. Co-developed-by: Vijaya Krishna Nivarthi Signed-off-by: Vijaya Krishna Nivarthi Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421115526.1828659-3-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 015a3474d401..6a14259b93c4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -233,6 +233,14 @@ }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &ipa { status = "okay"; modem-init; From 510c527b4ff574bda5c20429eb563eda63c41198 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 18 Apr 2022 15:24:57 +0200 Subject: [PATCH 474/791] arm64: dts: imx8mm: Add i.MX8M Mini Toradex Verdin based Menlo board Add new board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo. The board is a compatible replacement for i.MX53 M53Menlo and features USB, multiple UARTs, ethernet, LEDs, SD and eMMC. Reviewed-by: Fabio Estevam Reviewed-by: Francesco Dolcini Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Francesco Dolcini Cc: Marcel Ziswiler Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mm-mx8menlo.dts | 321 ++++++++++++++++++ 2 files changed, 322 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 851e6faf8c05..cdf9dfcbe020 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts new file mode 100644 index 000000000000..c20db0c550da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021-2022 Marek Vasut + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" + +/ { + model = "MENLO MX8MM EMBEDDED DEVICE"; + compatible = "menlo,mx8menlo", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; + + /delete-node/ gpio-keys; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "TestLed601"; + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "TestLed602"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + beeper { + compatible = "gpio-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + }; + + /* Fixed clock dedicated to SPI CAN on carrier board */ + clk_xtal20: clk-xtal20 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* CAN controller on the baseboard */ + canfd: can@0 { + compatible = "microchip,mcp2518fd"; + clocks = <&clk_xtal20>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + reg = <0>; + spi-max-frequency = <2000000>; + }; + +}; + +&ecspi2 { + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +ðphy0 { + max-speed = <100>; +}; + +&fec1 { + status = "okay"; +}; + +&flexspi { + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "DISP_reset", "KBD_intI", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + /* + * CPLD_D[n] is ARM_CPLD[n] in schematic + * CPLD_int is SA_INTERRUPT in schematic + * CPLD_reset is RESET_SOFT in schematic + */ + gpio-line-names = + "CPLD_D[1]", "CPLD_int", "CPLD_reset", "", + "", "CPLD_D[0]", "", "", + "", "", "", "CPLD_D[2]", + "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]", + "CPLD_D[7]", "", "", "", + "", "", "", "", + "", "", "", "KBD_intK", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio_expander_21 { + status = "okay"; +}; + +&hwmon { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + /* None of this is present on the SoM. */ + /delete-node/ bridge@2c; + /delete-node/ hdmi@48; + /delete-node/ touch@4a; + /delete-node/ sensor@4f; + /delete-node/ eeprom@50; + /delete-node/ eeprom@57; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; + + pinctrl_beeper: beepergrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 + >; + }; + + pinctrl_uart4_rts: uart4rtsgrp { + fsl,pins = < + /* SODIMM 222 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 + >; + }; +}; + +&pinctrl_gpio1 { + fsl,pins = < + /* SODIMM 206 */ + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4 + >; +}; + +&pinctrl_gpio_hog1 { + fsl,pins = < + /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 + /* CPLD_int */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 + /* CPLD_reset */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 + /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 + /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 + /* CPLD_D[7] */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 + /* CPLD_D[6] */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 + /* CPLD_D[5] */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 + /* CPLD_D[4] */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 + /* CPLD_D[3] */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 + /* CPLD_D[2] */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 + /* CPLD_D[1] */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 + /* CPLD_D[0] */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 + /* KBD_intK */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4 + /* DISP_reset */ + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4 + /* KBD_intI */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4 + /* SODIMM 46 */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4 + >; +}; + +&pinctrl_uart1 { + fsl,pins = < + /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 + /* SODIMM 147 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 + /* SODIMM 210 */ + MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4 + /* SODIMM 212 */ + MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4 + >; +}; + +®_usb_otg1_vbus { + /delete-property/ enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; +}; + +®_usb_otg2_vbus { + /delete-property/ enable-active-high; + gpio = <&gpio1 14 GPIO_ACTIVE_LOW>; +}; + +&sai2 { + status = "disabled"; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>; + linux,rs485-enabled-at-boot-time; + rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; From cc545760170590b5e6733ebfef8398f97d7dee05 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 18 Apr 2022 15:36:17 -0300 Subject: [PATCH 475/791] arm64: dts: imx8mn-evk: Add UART3 support UART3 pins are available in the J1003 connector. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index dc75d6d13bb3..d1f6cccfa00d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -212,6 +212,15 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -374,6 +383,15 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 From 17efcc33e4f5fa3ffd62f6e5ce830106484817c0 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:08 +0200 Subject: [PATCH 476/791] ARM: dts: imx6qdl-vicut1.dtsi: remove TiWi module Only the first prototypes had a TiWi module. There is no publicly available hardware where this module is fitted and there are no plan to produce any. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 51 --------------------------- 1 file changed, 51 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index ec39008c0950..fe2685642bf1 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -144,18 +144,6 @@ enable-active-high; }; - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - regulator-name = "wifi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <70000>; - }; - sound { compatible = "simple-audio-card"; simple-audio-card,name = "prti6q-sgtl5000"; @@ -530,26 +518,6 @@ status = "okay"; }; -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_wifi>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - no-1-8-v; - no-mmc; - no-sd; - status = "okay"; - - wifi { - compatible = "ti,wl1271"; - interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = "38400000"; - tcxo-clock-frequency = "19200000"; - }; -}; - &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -808,19 +776,6 @@ >; }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - /* WL12xx IRQ */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 @@ -836,10 +791,4 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 >; }; - - pinctrl_wifi_npd: wifinpdgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 - >; - }; }; From 092073263226b3f417597bb13145042c60b1ab93 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:09 +0200 Subject: [PATCH 477/791] ARM: dts: imx6qdl-vicut1.dtsi: Put nON_SWITCH in own pinctrl grp Unify nON_SWITCH pinctrl configuration with imx6dl-victgo.dts. This patch is a preparation to reduce duplicated code between vicut1 and victgo. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index fe2685642bf1..32f7eb379e60 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -72,6 +72,8 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; power { @@ -621,6 +623,13 @@ >; }; + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < /* ITU656_nRESET */ @@ -631,8 +640,6 @@ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* CAM_nDETECT */ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 /* ISB_IN1 */ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 /* ISB_nIN2 */ From 2a0a0c5dc0764b00154f6784883ea60c69e5c275 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:10 +0200 Subject: [PATCH 478/791] ARM: dts: imx6qdl-vicut1.dtsi: Remove PCIe Only the very first prototypes had PCIe and there are no plant to add it in the future. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 32f7eb379e60..b126ef4d5255 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -296,8 +296,8 @@ &gpio5 { gpio-line-names = - "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS", - "PCIE_RESET", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", "I2S_BITCLK", "I2S_DOUT", "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", @@ -439,10 +439,6 @@ }; }; -&pcie { - status = "okay"; -}; - &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; From f6d8a739b35758d6958d51e39dc760f49629047e Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:11 +0200 Subject: [PATCH 479/791] ARM: dts: imx6qdl-vicut1/victgo: Remove UART2 Only first prototype had UART2 and there are no plans to add it in the future. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 13 ------------- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 15 --------------- 2 files changed, 28 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 7dd7fb165432..9cf4df3eaeb0 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -616,12 +616,6 @@ status = "okay"; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -905,13 +899,6 @@ >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - /* YaCO Touchscreen UART */ pinctrl_uart3: uart3grp { fsl,pins = < diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index b126ef4d5255..ea474aa93485 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -463,12 +463,6 @@ status = "okay"; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -728,15 +722,6 @@ >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; - /* YaCO Touchscreen UART */ pinctrl_uart3: uart3grp { fsl,pins = < From 1a0e71889dea95fa73a5cfc1fb505952b1f099f0 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:12 +0200 Subject: [PATCH 480/791] ARM: dts: imx6qdl-vicut1.dtsi: Fix LED names The names should be consistent with the names in imx6dl-victgo.dts This patch is preparation to unify vicut1 and victgo DTs. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index ea474aa93485..b7a705b39178 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -90,21 +90,21 @@ pinctrl-0 = <&pinctrl_leds>; led-0 { - label = "LED_DI0_DEBUG_0"; + label = "debug0"; function = LED_FUNCTION_HEARTBEAT; gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-1 { - label = "LED_DI0_DEBUG_1"; + label = "debug1"; function = LED_FUNCTION_DISK; gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; }; led-2 { - label = "POWER_LED"; + label = "power_led"; function = LED_FUNCTION_POWER; gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; default-state = "on"; From c061895eb0248d3d2c250930a2c69353d4ba94c2 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:13 +0200 Subject: [PATCH 481/791] ARM: dts: imx6qdl-vicut1.dtsi: Fix debug LED gpio pins While there are LEDs connected on some variants on GPIO4 pins 16 and 17, those are not the debug LEDs that should be visible to user-space. It should be the same as in imx6dl-victgo.dtsi. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index b7a705b39178..a5f962f1028b 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -92,14 +92,14 @@ led-0 { label = "debug0"; function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-1 { label = "debug1"; function = LED_FUNCTION_DISK; - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; }; From 4e6ab6837e326c975443168ac1aaf2b6132caf5b Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:14 +0200 Subject: [PATCH 482/791] ARM: dts: imx6qdl-vicut1.dtsi: Update GPIO line names Add some missing names and remove names to pins that have never been used and/or are not present on any hardware. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index a5f962f1028b..a93e7f8302aa 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -257,12 +257,10 @@ gpio-line-names = "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3", - "SDIO_D2", "SDIO_D1", "SDIO_D0", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "", "", - "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "", - "WL_IRQ", "ETH_MDC"; + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; }; &gpio2 { @@ -270,8 +268,8 @@ "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", "", "LED_PWM", "", "", "", "", "", "", - "", "", "", "", "", "", "", "ON_SWITCH", - "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", + "POWER_LED", "", "", "", "", "", "", ""; }; &gpio3 { @@ -280,7 +278,8 @@ "", "", "", "", "", "", "", "", "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "", "", "", "", "", "", "", ""; + "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", + "YACO_RESET"; }; &gpio4 { @@ -288,8 +287,8 @@ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "ON1_CTRL", - "ON2_CTRL", "HITCH_IN_OUT", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", "ISB_LED"; }; From 1d039a1ae2c7ccfd269ebfdb11c10085fc394aff Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:15 +0200 Subject: [PATCH 483/791] ARM: dts: imx6qdl-vicut1.dtsi: Remove conflicting pinctrl entry The function of DISP0_DAT9 is dependent on hardware revision of two particular variants. This setting should be done by the bootloader anyway, and is not needed in the kernel, so remove it from the DT. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index a93e7f8302aa..6c943ca950f4 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -655,10 +655,6 @@ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 /* DIP1_FB */ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - - /* New in UT2: FIXME: ISB PWM should start off, PD */ - /* ISB_LED_PWM */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0 >; }; From 4eef8cb7dd41a47da94191fc1d191167be07a077 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:16 +0200 Subject: [PATCH 484/791] ARM: dts: imx6q-vicut1.dts: remove sata node Only the prototype had the SATA interface. There are no existing products with SATA interface and no plans to add any. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-vicut1.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts index 0a4e251be162..e6c5d3cb48d7 100644 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ b/arch/arm/boot/dts/imx6q-vicut1.dts @@ -11,7 +11,3 @@ model = "Kverneland UT1Q Board"; compatible = "kvg,vicut1q", "fsl,imx6q"; }; - -&sata { - status = "okay"; -}; From deebb9ba3a64acb8dabcedcf2845f86b48f0e7b4 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:17 +0200 Subject: [PATCH 485/791] ARM: dts: imx6dl-victgo.dts: update gpio names Following changes was made: - Add MDIO signal names - Add missing ISB_IN2 name. Also correct ISB_nIN1. These two signals were used together in older HW revisions. Later ISB_IN2 was removed. Software should still be able to use both. - Add missing CAN1 and UART line names - Add missing ON1/2_CTRL line names - fix CPU_* line names. The real signal names are without the CPU_ prefix, like on imx6qdl-vicut1.dtsi - Fix ETH_INT signal name Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 41 ++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 9cf4df3eaeb0..7fc5bb499cbc 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -408,8 +408,8 @@ "CAM2_MIRROR", "", "", "SMBALERT", "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "", "", - "", "", "", "", "", "", "", ""; + "SD1_DATA3", "ETH_MDIO", "", + "", "", "", "", "", "", "", "ETH_MDC"; }; &gpio2 { @@ -417,7 +417,7 @@ "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", "", "LED_PWM", "", "", "", "", "", "", - "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", "POWER_LED", "", "", "", "", "", "", ""; }; @@ -426,18 +426,20 @@ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", + "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", "YACO_RESET"; }; &gpio4 { gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "", "", "", - "CPU_LIGHT_ON", "", "ETH_RESET", "CPU_CONTACT_IN", "BL_EN", - "BL_PWM", "ETH_INTRP", "ISB_LED"; + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "ETH_RESET", "CONTACT_IN", "BL_EN", + "BL_PWM", "ETH_INT", "ISB_LED"; }; &gpio5 { @@ -445,11 +447,30 @@ "", "", "", "", "", "", "", "", "TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO", "ECSPI2_SS0", "ECSPI2_SCLK", "", "", - "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; }; +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", + "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", + "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", + "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; From d380984764ad5c7c12d35f687aef843ea10f373c Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:18 +0200 Subject: [PATCH 486/791] ARM: dts: imx6dl-victgo.dts: Factor out common parts to imx6qdl-victgo.dtsi These parts are common to imx6qdl-vicut1.dtsi. This patch is preparation to unify victgo and vicut1 DTs. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 649 +------------------------ arch/arm/boot/dts/imx6qdl-victgo.dtsi | 658 ++++++++++++++++++++++++++ 2 files changed, 659 insertions(+), 648 deletions(-) create mode 100644 arch/arm/boot/dts/imx6qdl-victgo.dtsi diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 7fc5bb499cbc..6d61e87405f4 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -5,76 +5,13 @@ */ /dts-v1/; -#include -#include -#include -#include -#include -#include #include "imx6dl.dtsi" +#include "imx6qdl-victgo.dtsi" / { model = "Kverneland TGO"; compatible = "kvg,victgo", "fsl,imx6dl"; - chosen { - stdout-path = &uart4; - }; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - backlight_led: backlight_led { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - - counter-0 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter0>; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - - counter-1 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter1>; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - counter-2 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter2>; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -101,33 +38,6 @@ io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "debug1"; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-2 { - label = "power_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - panel { compatible = "lg,lb070wv8"; backlight = <&backlight_lcd>; @@ -146,29 +56,6 @@ clock-frequency = <50000000>; }; - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - rotary-encoder { compatible = "rotary-encoder"; pinctrl-0 = <&pinctrl_rotary_ch>; @@ -181,33 +68,6 @@ wakeup-source; }; - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - bitclock-master; - frame-master; - }; - }; - thermal-zones { chassis-thermal { polling-delay = <20000>; @@ -275,63 +135,6 @@ }; }; -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - termination-ohms = <150>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - &ecspi2 { cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -412,25 +215,6 @@ "", "", "", "", "", "", "", "ETH_MDC"; }; -&gpio2 { - gpio-line-names = - "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", - "", "LED_PWM", "", "", "", - "", "", "", - "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", - "POWER_LED", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", - "YACO_RESET"; -}; - &gpio4 { gpio-line-names = "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", @@ -462,55 +246,7 @@ "", "", "", "", "", "", "", ""; }; -&gpio7 { - gpio-line-names = - "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", - "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", - "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", - "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - &i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video-decoder@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; - keypad@70 { compatible = "holtek,ht16k33"; pinctrl-names = "default"; @@ -534,236 +270,9 @@ MATRIX_KEY(6, 1, KEY_F1) >; }; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsens0: temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - #thermal-sensor-cells = <0>; - }; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_counter0: counter0grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 - >; - }; - - pinctrl_counter1: counter1grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 - >; - }; - - pinctrl_counter2: counter2grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 @@ -802,102 +311,12 @@ >; }; - pinctrl_hog: hoggrp { - fsl,pins = < - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* CAM1_MIRROR */ - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 - /* CAM2_MIRROR */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 - /* CAM_nDETECT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* ISB_IN1 */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - /* ISB_nIN2 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - /* WARN_LIGHT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 - /* ON2_FB */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 - /* YACO_nIRQ */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - /* YACO_BOOT0 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 - /* YACO_nRESET */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - /* FORCE_ON1 */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - - /* New in HW revision 1 */ - /* ON1_FB */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 - /* DIP1_FB */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - pinctrl_keypad: keypadgrp { fsl,pins = < MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 >; }; - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG0 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 - /* DEBUG1 */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 - /* POWER_LED */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - >; - }; - pinctrl_rotary_ch: rotarychgrp { fsl,pins = < MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 @@ -911,70 +330,4 @@ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 >; }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* YaCO Touchscreen UART */ - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-victgo.dtsi b/arch/arm/boot/dts/imx6qdl-victgo.dtsi new file mode 100644 index 000000000000..386e2ca39424 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-victgo.dtsi @@ -0,0 +1,658 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +#include +#include +#include +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + + connector { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = ; + + port { + comp0_out: endpoint { + remote-endpoint = <&tvp5150_comp0_in>; + }; + }; + }; + + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "debug1"; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + + led-2 { + label = "power_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&gpio2 { + gpio-line-names = + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", + "", "LED_PWM", "", "", "", + "", "", "", + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", + "POWER_LED", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", + "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", + "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", + "YACO_RESET"; +}; + +&gpio7 { + gpio-line-names = + "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", + "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", + "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", + "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + video-decoder@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tvp5150_comp0_in: endpoint { + remote-endpoint = <&comp0_out>; + }; + }; + + /* Output port 2 is video output pad */ + port@2 { + reg = <2>; + + tvp5151_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tsens0: temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + #thermal-sensor-cells = <0>; + }; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 + >; + }; + + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* CAM1_MIRROR */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 + /* CAM2_MIRROR */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 + /* CAM_nDETECT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* ISB_IN1 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 + /* ISB_nIN2 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + /* WARN_LIGHT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 + /* ON2_FB */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 + /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 + /* YACO_nRESET */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + /* FORCE_ON1 */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + + /* New in HW revision 1 */ + /* ON1_FB */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 + /* DIP1_FB */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + /* DEBUG0 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 + /* DEBUG1 */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 + /* POWER_LED */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* YaCO Touchscreen UART */ + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; From 217390ad7423d65591745ec4957aaa30b62c3a7b Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:19 +0200 Subject: [PATCH 487/791] ARM: dts: imx6qdl-vicut1.dtsi: Move some node out to DTS files This commit will finally make this file identical to imx6qdl-victgo.dtsi. All nodes that are removed here are added as-is to the DTS files that include this file. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-vicut1.dts | 122 ++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q-vicut1.dts | 122 ++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 120 ------------------------- arch/arm/boot/dts/imx6qp-vicutp.dts | 122 ++++++++++++++++++++++++++ 4 files changed, 366 insertions(+), 120 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/imx6dl-vicut1.dts index 174fd913bf96..c6a904bbed01 100644 --- a/arch/arm/boot/dts/imx6dl-vicut1.dts +++ b/arch/arm/boot/dts/imx6dl-vicut1.dts @@ -10,4 +10,126 @@ / { model = "Kverneland UT1 Board"; compatible = "kvg,vicut1", "fsl,imx6dl"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts index e6c5d3cb48d7..8b228d5fc4a3 100644 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ b/arch/arm/boot/dts/imx6q-vicut1.dts @@ -10,4 +10,126 @@ / { model = "Kverneland UT1Q Board"; compatible = "kvg,vicut1q", "fsl,imx6q"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 6c943ca950f4..2a86136a04e8 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -70,20 +70,6 @@ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -111,18 +97,6 @@ }; }; - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - reg_1v8: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "1v8"; @@ -231,38 +205,6 @@ }; }; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - &gpio2 { gpio-line-names = "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", @@ -282,38 +224,6 @@ "YACO_RESET"; }; -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - &gpio7 { gpio-line-names = "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", @@ -589,36 +499,6 @@ >; }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; - pinctrl_hog: hoggrp { fsl,pins = < /* ITU656_nRESET */ diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/imx6qp-vicutp.dts index 7bad7ca6b12e..31c748e9d92f 100644 --- a/arch/arm/boot/dts/imx6qp-vicutp.dts +++ b/arch/arm/boot/dts/imx6qp-vicutp.dts @@ -10,4 +10,126 @@ / { model = "Kverneland UT1P Board"; compatible = "kvg,vicutp", "fsl,imx6qp"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; }; From 901e8f8f8b87a56e6bb6b974063e7bcb4d272e38 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:20 +0200 Subject: [PATCH 488/791] ARM: dts: Remove imx6qdl-victgo.dtsi The common base is now identical to imx6qdl-vicut1.dtsi, so we can remove one of both. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- arch/arm/boot/dts/imx6qdl-victgo.dtsi | 658 -------------------------- 2 files changed, 1 insertion(+), 659 deletions(-) delete mode 100644 arch/arm/boot/dts/imx6qdl-victgo.dtsi diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 6d61e87405f4..4f6100b2ce2d 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-victgo.dtsi" +#include "imx6qdl-vicut1.dtsi" / { model = "Kverneland TGO"; diff --git a/arch/arm/boot/dts/imx6qdl-victgo.dtsi b/arch/arm/boot/dts/imx6qdl-victgo.dtsi deleted file mode 100644 index 386e2ca39424..000000000000 --- a/arch/arm/boot/dts/imx6qdl-victgo.dtsi +++ /dev/null @@ -1,658 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -#include -#include -#include -#include -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - backlight_led: backlight_led { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - - counter-0 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter0>; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - - counter-1 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter1>; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - counter-2 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter2>; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "debug1"; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-2 { - label = "power_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - bitclock-master; - frame-master; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - termination-ohms = <150>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&gpio2 { - gpio-line-names = - "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", - "", "LED_PWM", "", "", "", - "", "", "", - "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", - "POWER_LED", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", - "YACO_RESET"; -}; - -&gpio7 { - gpio-line-names = - "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", - "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", - "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", - "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video-decoder@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsens0: temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - #thermal-sensor-cells = <0>; - }; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_counter0: counter0grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 - >; - }; - - pinctrl_counter1: counter1grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 - >; - }; - - pinctrl_counter2: counter2grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* CAM1_MIRROR */ - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 - /* CAM2_MIRROR */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 - /* CAM_nDETECT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* ISB_IN1 */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - /* ISB_nIN2 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - /* WARN_LIGHT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 - /* ON2_FB */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 - /* YACO_nIRQ */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - /* YACO_BOOT0 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 - /* YACO_nRESET */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - /* FORCE_ON1 */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - - /* New in HW revision 1 */ - /* ON1_FB */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 - /* DIP1_FB */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG0 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 - /* DEBUG1 */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 - /* POWER_LED */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - >; - }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* YaCO Touchscreen UART */ - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; From 6d8e96fbeb07fa0ac4d248cac5174e866320ce9c Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:21 +0200 Subject: [PATCH 489/791] ARM: dts: imx6qdl-vicut1: Factor out common parts of 12inch board variants Factor out common parts of vicut1 and vicutp to reduce maintenance overhead. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-vicut1.dts | 123 +----------------- arch/arm/boot/dts/imx6q-vicut1.dts | 123 +----------------- arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi | 128 +++++++++++++++++++ arch/arm/boot/dts/imx6qp-vicutp.dts | 123 +----------------- 4 files changed, 131 insertions(+), 366 deletions(-) create mode 100644 arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/imx6dl-vicut1.dts index c6a904bbed01..5035d303447d 100644 --- a/arch/arm/boot/dts/imx6dl-vicut1.dts +++ b/arch/arm/boot/dts/imx6dl-vicut1.dts @@ -6,130 +6,9 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1 Board"; compatible = "kvg,vicut1", "fsl,imx6dl"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts index 8b228d5fc4a3..dd91aff3f9e2 100644 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ b/arch/arm/boot/dts/imx6q-vicut1.dts @@ -6,130 +6,9 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1Q Board"; compatible = "kvg,vicut1q", "fsl,imx6q"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi new file mode 100644 index 000000000000..f505f2704530 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Protonic Holland + */ + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/imx6qp-vicutp.dts index 31c748e9d92f..49ff145fffe5 100644 --- a/arch/arm/boot/dts/imx6qp-vicutp.dts +++ b/arch/arm/boot/dts/imx6qp-vicutp.dts @@ -6,130 +6,9 @@ /dts-v1/; #include "imx6qp.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1P Board"; compatible = "kvg,vicutp", "fsl,imx6qp"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; }; From eac849a24e188adeecd0ba3b598ea861281da725 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:22 +0200 Subject: [PATCH 490/791] ARM: dts: imx6dl-victgo.dts: Remove touchscreen x axis inversion X axis is not inverted in hardware. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 4f6100b2ce2d..516ec915a911 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -94,7 +94,6 @@ <&adc_ts 5>; io-channel-names = "y", "z1", "z2", "x"; touchscreen-min-pressure = <64687>; - touchscreen-inverted-x; touchscreen-inverted-y; touchscreen-x-plate-ohms = <300>; touchscreen-y-plate-ohms = <800>; From b456aed07944b3048d68f7daad2fd6e1155dc4fe Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:23 +0200 Subject: [PATCH 491/791] ARM: dts: imx6qdl-vicut1.dtsi: Add missing ISB led node Add missing ISB led node. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 2a86136a04e8..c928bd854e92 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -95,6 +95,13 @@ gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; default-state = "on"; }; + + led-3 { + label = "isb_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; }; reg_1v8: regulator-1v8 { @@ -574,6 +581,8 @@ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 /* POWER_LED */ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + /* ISB_LED */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 >; }; From 7912bda4f60dbb86c5aaa41fc1d36e639780ac90 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 19 Apr 2022 06:48:24 +0200 Subject: [PATCH 492/791] ARM: dts: imx6qdl-vicut1.dtsi: add thermal zone and attach tmp103 to it. Latest version of ti,tmp103 driver supports thermal zone. So make use of it. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index c928bd854e92..a1676b5d2980 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -153,6 +153,14 @@ frame-master; }; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + }; }; &audmux { @@ -323,9 +331,10 @@ reg = <0x51>; }; - temperature-sensor@70 { + tsens0: temperature-sensor@70 { compatible = "ti,tmp103"; reg = <0x70>; + #thermal-sensor-cells = <0>; }; }; From 90715507cb899df6c726494c0225d30130ad0cc5 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 25 Apr 2022 15:41:55 +0900 Subject: [PATCH 493/791] dt-bindings: power: Add r8a779g0 SYSC power domain definitions Add power domain indices for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220425064201.459633-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/power/r8a779g0-sysc.h | 45 +++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/power/r8a779g0-sysc.h diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h new file mode 100644 index 000000000000..7daa70f1814e --- /dev/null +++ b/include/dt-bindings/power/r8a779g0-sysc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779G0_PD_A1E0D0C0 0 +#define R8A779G0_PD_A1E0D0C1 1 +#define R8A779G0_PD_A1E0D1C0 2 +#define R8A779G0_PD_A1E0D1C1 3 +#define R8A779G0_PD_A2E0D0 16 +#define R8A779G0_PD_A2E0D1 17 +#define R8A779G0_PD_A3E0 20 +#define R8A779G0_PD_A33DGA 24 +#define R8A779G0_PD_A23DGB 25 +#define R8A779G0_PD_A1DSP0 33 +#define R8A779G0_PD_A2IMP01 34 +#define R8A779G0_PD_A2PSC 35 +#define R8A779G0_PD_A2CV0 36 +#define R8A779G0_PD_A2CV1 37 +#define R8A779G0_PD_A1CNN0 41 +#define R8A779G0_PD_A2CN0 42 +#define R8A779G0_PD_A3IR 43 +#define R8A779G0_PD_A1DSP1 45 +#define R8A779G0_PD_A2IMP23 46 +#define R8A779G0_PD_A2DMA 47 +#define R8A779G0_PD_A2CV2 48 +#define R8A779G0_PD_A2CV3 49 +#define R8A779G0_PD_A1DSP2 53 +#define R8A779G0_PD_A1DSP3 54 +#define R8A779G0_PD_A3VIP0 56 +#define R8A779G0_PD_A3VIP1 57 +#define R8A779G0_PD_A3VIP2 58 +#define R8A779G0_PD_A3ISP0 60 +#define R8A779G0_PD_A3ISP1 61 + +/* Always-on power area */ +#define R8A779G0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/ From f2afa78d5a0c0b0b2461a5c532d7a84214a1b633 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 25 Apr 2022 15:41:56 +0900 Subject: [PATCH 494/791] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h new file mode 100644 index 000000000000..754c54a6eb06 --- /dev/null +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ + +#include + +/* r8a779g0 CPG Core Clocks */ + +#define R8A779G0_CLK_ZX 0 +#define R8A779G0_CLK_ZS 1 +#define R8A779G0_CLK_ZT 2 +#define R8A779G0_CLK_ZTR 3 +#define R8A779G0_CLK_S0D2 4 +#define R8A779G0_CLK_S0D3 5 +#define R8A779G0_CLK_S0D4 6 +#define R8A779G0_CLK_S0D1_VIO 7 +#define R8A779G0_CLK_S0D2_VIO 8 +#define R8A779G0_CLK_S0D4_VIO 9 +#define R8A779G0_CLK_S0D8_VIO 10 +#define R8A779G0_CLK_S0D1_VC 11 +#define R8A779G0_CLK_S0D2_VC 12 +#define R8A779G0_CLK_S0D4_VC 13 +#define R8A779G0_CLK_S0D2_MM 14 +#define R8A779G0_CLK_S0D4_MM 15 +#define R8A779G0_CLK_S0D2_U3DG 16 +#define R8A779G0_CLK_S0D4_U3DG 17 +#define R8A779G0_CLK_S0D2_RT 18 +#define R8A779G0_CLK_S0D3_RT 19 +#define R8A779G0_CLK_S0D4_RT 20 +#define R8A779G0_CLK_S0D6_RT 21 +#define R8A779G0_CLK_S0D24_RT 22 +#define R8A779G0_CLK_S0D2_PER 23 +#define R8A779G0_CLK_S0D3_PER 24 +#define R8A779G0_CLK_S0D4_PER 25 +#define R8A779G0_CLK_S0D6_PER 26 +#define R8A779G0_CLK_S0D12_PER 27 +#define R8A779G0_CLK_S0D24_PER 28 +#define R8A779G0_CLK_S0D1_HSC 29 +#define R8A779G0_CLK_S0D2_HSC 30 +#define R8A779G0_CLK_S0D4_HSC 31 +#define R8A779G0_CLK_S0D2_CC 32 +#define R8A779G0_CLK_SVD1_IR 33 +#define R8A779G0_CLK_SVD2_IR 34 +#define R8A779G0_CLK_SVD1_VIP 35 +#define R8A779G0_CLK_SVD2_VIP 36 +#define R8A779G0_CLK_CL 37 +#define R8A779G0_CLK_CL16M 38 +#define R8A779G0_CLK_CL16M_MM 39 +#define R8A779G0_CLK_CL16M_RT 40 +#define R8A779G0_CLK_CL16M_PER 41 +#define R8A779G0_CLK_CL16M_HSC 42 +#define R8A779G0_CLK_Z0 43 +#define R8A779G0_CLK_ZB3 44 +#define R8A779G0_CLK_ZB3D2 45 +#define R8A779G0_CLK_ZB3D4 46 +#define R8A779G0_CLK_ZG 47 +#define R8A779G0_CLK_SD0H 48 +#define R8A779G0_CLK_SD0 49 +#define R8A779G0_CLK_RPC 50 +#define R8A779G0_CLK_RPCD2 51 +#define R8A779G0_CLK_MSO 52 +#define R8A779G0_CLK_CANFD 53 +#define R8A779G0_CLK_CSI 54 +#define R8A779G0_CLK_FRAY 55 +#define R8A779G0_CLK_IPC 56 +#define R8A779G0_CLK_SASYNCRT 57 +#define R8A779G0_CLK_SASYNCPERD1 58 +#define R8A779G0_CLK_SASYNCPERD2 59 +#define R8A779G0_CLK_SASYNCPERD4 60 +#define R8A779G0_CLK_VIOBUS 61 +#define R8A779G0_CLK_VIOBUSD2 62 +#define R8A779G0_CLK_VCBUS 63 +#define R8A779G0_CLK_VCBUSD2 64 +#define R8A779G0_CLK_DSIEXT 65 +#define R8A779G0_CLK_DSIREF 66 +#define R8A779G0_CLK_ADGH 67 +#define R8A779G0_CLK_OSC 68 +#define R8A779G0_CLK_ZR0 69 +#define R8A779G0_CLK_ZR1 70 +#define R8A779G0_CLK_ZR2 71 +#define R8A779G0_CLK_IMPA 72 +#define R8A779G0_CLK_IMPAD4 73 +#define R8A779G0_CLK_CPEX 74 +#define R8A779G0_CLK_CBFUSA 75 +#define R8A779G0_CLK_R 76 + +#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ From 6cd3233242eebfd81c8eb83fa965959471a2cd97 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 20 Apr 2022 17:42:41 +0900 Subject: [PATCH 495/791] dt-bindings: arm: renesas: Document R-Car V4H White Hawk DT bindings Add device tree binding documentation for the Renesas R-Car V4H (r8a779g0) SoC and the Renesas White Hawk CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220420084255.375700-2-yoshihiro.shimoda.uh@renesas.com Link: https://lore.kernel.org/r/20220420084255.375700-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index f61807103867..5408b154d05e 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -327,6 +327,18 @@ properties: - const: renesas,spider-cpu - const: renesas,r8a779f0 + - description: R-Car V4H (R8A779G0) + items: + - enum: + - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000) + - const: renesas,r8a779g0 + + - items: + - enum: + - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) + - const: renesas,white-hawk-cpu + - const: renesas,r8a779g0 + - description: R-Car H3e (R8A779M0) items: - enum: From 8ff93be3259fda0f7b7667ee1717b1dc9c4c8d07 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 20 Apr 2022 17:42:43 +0900 Subject: [PATCH 496/791] dt-bindings: reset: renesas,rst: Document r8a779g0 reset module Document bindings for the R-Car V4H (R8A779G0) reset module. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220420084255.375700-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index bbe313bf1796..0d1b89e2fe9c 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -49,6 +49,7 @@ properties: - renesas,r8a77995-rst # R-Car D3 - renesas,r8a779a0-rst # R-Car V3U - renesas,r8a779f0-rst # R-Car S4-8 + - renesas,r8a779g0-rst # R-Car V4H reg: maxItems: 1 From 41e3958475ed3f9ad09facbe04cb8eafcee14546 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Fri, 8 Apr 2022 14:19:21 +0100 Subject: [PATCH 497/791] dt-bindings: Add Arm corstone1000 platform Add bindings to describe the FPGA in a prototyping board (MPS3) implementation and the Fixed Virtual Platform implementation of the ARM Corstone1000 platform. Link: https://lore.kernel.org/r/20220408131922.3864348-2-rui.silva@linaro.org Reviewed-by: Rob Herring Signed-off-by: Rui Miguel Silva Signed-off-by: Sudeep Holla --- .../bindings/arm/arm,corstone1000.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml new file mode 100644 index 000000000000..a77f88223801 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Corstone1000 Device Tree Bindings + +maintainers: + - Vishnu Banavath + - Rui Miguel Silva + +description: |+ + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M + processors. + + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion + systems for M-Class (or other) processors for adding sensors, connectivity, + video, audio and machine learning at the edge System and security IPs to build + a secure SoC for a range of rich IoT applications, for example gateways, smart + cameras and embedded systems. + + Integrated Secure Enclave providing hardware Root of Trust and supporting + seamless integration of the optional CryptoCell™-312 cryptographic + accelerator. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA + implementation of the Corstone1000 in the MPS3 prototyping board. See + ARM document DAI0550. + items: + - const: arm,corstone1000-mps3 + - description: Corstone1000 FVP is the Fixed Virtual Platform + implementation of this system. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-fvp + +additionalProperties: true + +... From a69d277460888c2bd99a6fa849f474a7197a3e16 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Fri, 8 Apr 2022 14:19:22 +0100 Subject: [PATCH 498/791] arm64: dts: Add Arm corstone1000 platform support Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Link: https://lore.kernel.org/r/20220408131922.3864348-3-rui.silva@linaro.org Reviewed-by: Rob Herring Signed-off-by: Rui Miguel Silva Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 51 ++++++ arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 32 ++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 164 ++++++++++++++++++ 4 files changed, 248 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 4382b73baef5..d908e96d7ddc 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts new file mode 100644 index 000000000000..26b0f1b3cea6 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-fvp"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + }; + + vmmc_v3_3d: fixed_v3_3d { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts new file mode 100644 index 000000000000..e3146747c2d9 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FPGA MPS3 board"; + compatible = "arm,corstone1000-mps3"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb_host: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts = ; + bus-width = <16>; + dr_mode = "host"; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi new file mode 100644 index 000000000000..4e46826f883a --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = ; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + timer@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <50000000>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = ; + reg = <0x1a230000 0x1000>; + }; + }; + + uart0: serial@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + mhu_hse1: mailbox@1b820000 { + compatible = "arm,mhuv2-tx", "arm,primecell"; + reg = <0x1b820000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + + mhu_seh1: mailbox@1b830000 { + compatible = "arm,mhuv2-rx", "arm,primecell"; + reg = <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + }; +}; From 5393158f009bdc5e9b55559ce4ad2b0700c46e73 Mon Sep 17 00:00:00 2001 From: Diego Sueiro Date: Thu, 21 Apr 2022 15:35:21 +0100 Subject: [PATCH 499/791] arm64: dts: fvp: Add virtio-rng support The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17, so add the devicetree node to support it. It is disabled by default to avoid any issues with models that doesn't support it. Link: https://lore.kernel.org/r/ac3be672c636091ee1e079cadce776b1fb7e0b2e.1650543392.git.diego.sueiro@arm.com Signed-off-by: Diego Sueiro Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 3 ++- arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 7 +++++++ arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 269b649934b5..a496e39e6204 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -241,6 +241,7 @@ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 33182d9e5826..1b6326514c97 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -21,6 +21,13 @@ reg = <0x150000 0x200>; interrupts = <44>; }; + + virtio-rng@200000 { + compatible = "virtio,mmio"; + reg = <0x200000 0x200>; + interrupts = <46>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index 5f6cab668aa0..a999e7f52d8b 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -110,7 +110,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 3 0 0x200000>; + ranges = <0 3 0 0x210000>; v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; From d7030edf32ad5196af61a8d88e557ed2951b94cd Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Mon, 25 Apr 2022 14:55:24 +0100 Subject: [PATCH 500/791] arm64: dts: fvp: Align virtio device node names with dtschema Align the virtio mmio device tree node names with the schema to avoid any schema warnings. Link: https://lore.kernel.org/r/20220425135524.1077986-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 2 +- arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 6 +++--- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index fbf13f7c2baf..83e3e7e3984f 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -220,7 +220,7 @@ clock-names = "uartclk", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 1b6326514c97..ec2d5280a30b 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -10,19 +10,19 @@ arm,v2m-memory-map = "rs2"; iofpga-bus@300000000 { - virtio-p9@140000 { + virtio@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; interrupts = <43>; }; - virtio-net@150000 { + virtio@150000 { compatible = "virtio,mmio"; reg = <0x150000 0x200>; interrupts = <44>; }; - virtio-rng@200000 { + virtio@200000 { compatible = "virtio,mmio"; reg = <0x200000 0x200>; interrupts = <46>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index a999e7f52d8b..ba8beef3fe99 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -222,7 +222,7 @@ clock-names = "timclken1", "timclken2", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; From 962c400d48e604438cfb3732016ad1b74bfc298c Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 5 Apr 2022 18:31:19 +0530 Subject: [PATCH 501/791] arm64: tegra: Add node for Tegra234 CCPLEX cluster Adding CCPLEX cluster node to represent Tegra234 cpufreq. Tegra234 uses some of the CRAB (Control Register Access Bus) registers for CPU frequency requests. These registers are memory mapped to the CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB registers is required only for CPU frequency info. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 448512af7dea..8767dbe2d066 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1286,6 +1286,13 @@ }; }; + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x80000>; From 6d9d19af3e34121a816757b4fae341a4d749e1a7 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 6 Apr 2022 16:26:55 +0100 Subject: [PATCH 502/791] arm64: tegra: Update PWM fan node name According to the device-tree binding document for PWM fans [0], the PWM fan node name should be 'pwm-fan'. Update the PWM fan node name to align with this. [0] Documentation/devicetree/bindings/hwmon/pwm-fan.txt Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 4631504c3c7a..7e9aad9ff177 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -349,7 +349,7 @@ status = "okay"; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm4 0 45334>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 2478ece9e67c..27d28626bf5b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -1989,7 +1989,7 @@ "p2u-5", "p2u-6", "p2u-7"; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm4 0 45334>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 32ce7904f44f..8033be098f34 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1993,7 +1993,7 @@ "p2u-5", "p2u-6", "p2u-7"; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm6 0 45334>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 72c2dc3c14ea..746bd52ea3f7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1657,7 +1657,7 @@ }; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm 3 45334>; From 4b9b8985f9697b5d26efe7784e4b9e51cb452020 Mon Sep 17 00:00:00 2001 From: Changming Huang Date: Wed, 20 Apr 2022 10:35:56 +0800 Subject: [PATCH 503/791] ARM: dts: Add initial LS1021A IoT board dts support The LS1021A-IoT gateway reference design is a purpose-built, small footprint hardware platform equipped with a wide array of both high-speed connectivity and low speed serial interfaces. CC: Li Yang Signed-off-by: Changming Huang Signed-off-by: Alison Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/ls1021a-iot.dts | 227 ++++++++++++++++++++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f0e5fc7e5274..32e9bbf0d13c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -753,6 +753,7 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \ dtb-$(CONFIG_SOC_LAN966) += \ lan966x-pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-iot.dtb \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ ls1021a-tsn.dtb \ diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/ls1021a-iot.dts new file mode 100644 index 000000000000..66bcdaf4b6f9 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-iot.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021-2022 NXP + * + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A-IOT Board"; + compatible = "fsl,ls1021a-iot", "fsl,ls1021a"; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator-3V3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2V5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + frame-master; + bitclock-master; + }; + }; +}; + +&can0{ + status = "disabled"; +}; + +&can1{ + status = "disabled"; +}; + +&can2{ + status = "disabled"; +}; + +&can3{ + status = "okay"; +}; + +&dcu { + display = <&display>; + status = "okay"; + + display: display@0 { + bits-per-pixel = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: mode0 { + clock-frequency = <25000000>; + hactive = <640>; + vactive = <480>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <12>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&enet0 { + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&phy3>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&esdhc{ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9555: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sgtl5000: audio-codec@2a { + #sound-dai-cells=<0x0>; + compatible = "fsl,sgtl5000"; + reg = <0x2a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_2p5v>; + clocks = <&sys_mclk>; + }; + + max1239: adc@35 { + compatible = "maxim,max1239"; + reg = <0x35>; + #io-channel-cells = <1>; + }; + + ina2201: core-monitor@44 { + compatible = "ti,ina220"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + ina2202: current-monitor@45 { + compatible = "ti,ina220"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + lm75b: thermal-monitor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + num-cs = <2>; + status = "okay"; + + s25fl128s: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sai2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; From 1f5985b6f5d2090897918b100cad223a74dce706 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:02 +0300 Subject: [PATCH 504/791] ARM: dts: imx51: Add generic DMA bindings for UART nodes Updates UART nodes to adopt generic DMA bindings. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 56c8d87864c3..1e20a6639e42 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -215,6 +215,8 @@ clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 43 5 1>, <&sdma 44 5 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -426,6 +428,8 @@ clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -436,6 +440,8 @@ clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 16 4 1>, <&sdma 17 4 2>; + dma-names = "rx", "tx"; status = "disabled"; }; From ae7ab0bb32bdf18b70be04c3f254caaa54187225 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:03 +0300 Subject: [PATCH 505/791] ARM: dts: i.MX51: digi-connectcore-som: Remove unused regulators VGEN1, VGEN2 and GPO1 regulators are not used on SOM. Let's remove these entries. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 7d4970417dce..20e89cc4c838 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -102,18 +102,6 @@ regulator-always-on; }; - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - vgen3_reg: vgen3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -124,8 +112,6 @@ regulator-always-on; }; - gpo1_reg: gpo1 { }; - gpo2_reg: gpo2 { }; gpo3_reg: gpo3 { }; From 12f9fa8880f2309abc0d344a19590c9e00b3ae91 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:04 +0300 Subject: [PATCH 506/791] ARM: dts: i.MX51: digi-connectcore-som: Update PMIC voltages This patch updates the PMIC voltages according to the module's datasheet to match both commercial and industrial variants of the module. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 20e89cc4c838..04a47200fc73 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -34,22 +34,22 @@ regulators { sw1_reg: sw1 { - regulator-min-microvolt = <1000000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; sw2_reg: sw2 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1275000>; regulator-boot-on; regulator-always-on; }; sw3_reg: sw3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; regulator-boot-on; regulator-always-on; }; From a65123d60d757255694e55d228c247fb6da5a4fb Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:05 +0300 Subject: [PATCH 507/791] ARM: dts: i.MX51: digi-connectcore-som: Setup usbotg vbus-supply The VBUS on usbotg is connected to the PMIC SWBST, let's reflect that in the bindings. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 04a47200fc73..f0809a16a2ce 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -184,6 +184,7 @@ &usbotg { phy_type = "utmi_wide"; disable-over-current; + vbus-supply = <&swbst_reg>; /* Device role is not known, keep status disabled */ }; From 4bb3894ae658d8d5217843f344dd6cd5a9388924 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:06 +0300 Subject: [PATCH 508/791] ARM: dts: i.MX51: digi-connectcore-jsk: Use usb-nop-xceiv usbphy for USB1 Add node describing the USB1 usbphy. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts index aab8d6f137c3..10cae7c3a879 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -13,6 +13,13 @@ chosen { stdout-path = &uart1; }; + + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; }; &esdhc1 { @@ -63,6 +70,7 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; phy_type = "ulpi"; disable-over-current; From 74a46891867bf18535250fa8771c10f0153856f3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:02:55 +0200 Subject: [PATCH 509/791] arm64: dts: mediatek: mt8183: align Google CROS EC PWM node name with dtschema dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220214081916.162014-3-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..2d7a193272ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,7 +92,7 @@ }; &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; status = "disabled"; From 6f117db4123931d3fbde9cfaf360b02fe550c8d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:05:30 +0200 Subject: [PATCH 510/791] arm64: dts: mediatek: align operating-points table name with dtschema Align the name of operating-points node to dtschema to fix warnings like: arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml: opp_table0: $nodename:0: 'opp_table0' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210820081616.83674-1-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 86579330a8bd..623eb3beabf2 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -19,7 +19,7 @@ #address-cells = <2>; #size-cells = <2>; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp00 { @@ -36,7 +36,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp00 { diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 042feaedda4a..785c98cf786b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -57,7 +57,7 @@ serial3 = &uart3; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-507000000 { @@ -94,7 +94,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-507000000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5d4a1dd55adc..05106d2a6b1d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -197,7 +197,7 @@ }; }; - gpu_opp_table: opp_table0 { + gpu_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; From 624f1806a7c3f8061641a1f3e7c0dfa73e82fb10 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:05:20 +0200 Subject: [PATCH 511/791] arm64: dts: mediatek: align thermal zone node names with dtschema Align the name of thermal zone node to dtschema to fix warnings like: arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml: thermal-zones: 'cpu_thermal' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210820081616.83674-2-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 785c98cf786b..848e3f39c8ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -273,7 +273,7 @@ }; thermal-zones { - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 05106d2a6b1d..d1448a0b86cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -823,7 +823,7 @@ }; thermal_zones: thermal-zones { - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <100>; polling-delay = <500>; thermal-sensors = <&thermal 0>; From d3ee03d81615a889824eca49d24d5c51d0481bd1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:21:43 +0200 Subject: [PATCH 512/791] arm64: dts: mt8183-kukui: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220407142143.293740-1-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..8d5bf73a9099 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -849,7 +849,7 @@ mediatek,pad-select = <0>; status = "okay"; - w25q64dw: spi-flash@0 { + w25q64dw: flash@0 { compatible = "winbond,w25q64dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; From bf01df06ddb1452c7b4d7d2b4f51ecfad6cc5b71 Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Thu, 21 Apr 2022 11:51:09 +0800 Subject: [PATCH 513/791] arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes After adding device_link between the IOMMU consumer and smi, the mediatek,larb is unnecessary now. CC: Matthias Brugger Signed-off-by: Yong Wu Signed-off-by: Allen-KH Cheng Reviewed-by: Evan Green Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220421035111.7267-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16 ---------------- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ------ 2 files changed, 22 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 848e3f39c8ef..10291b2690ab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1010,7 +1010,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,larb = <&larb0>; mediatek,vpu = <&vpu>; }; @@ -1021,7 +1020,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA1>; - mediatek,larb = <&larb4>; }; mdp_rsz0: rsz@14003000 { @@ -1051,7 +1049,6 @@ clocks = <&mmsys CLK_MM_MDP_WDMA>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WDMA>; - mediatek,larb = <&larb0>; }; mdp_wrot0: wrot@14007000 { @@ -1060,7 +1057,6 @@ clocks = <&mmsys CLK_MM_MDP_WROT0>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT0>; - mediatek,larb = <&larb0>; }; mdp_wrot1: wrot@14008000 { @@ -1069,7 +1065,6 @@ clocks = <&mmsys CLK_MM_MDP_WROT1>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT1>; - mediatek,larb = <&larb4>; }; ovl0: ovl@1400c000 { @@ -1079,7 +1074,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1090,7 +1084,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL1>; iommus = <&iommu M4U_PORT_DISP_OVL1>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; @@ -1101,7 +1094,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; @@ -1112,7 +1104,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; @@ -1123,7 +1114,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA2>; iommus = <&iommu M4U_PORT_DISP_RDMA2>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; @@ -1134,7 +1124,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA0>; iommus = <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; @@ -1145,7 +1134,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA1>; iommus = <&iommu M4U_PORT_DISP_WDMA1>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; @@ -1399,7 +1387,6 @@ <0 0x16027800 0 0x800>, /* VDEC_HWB */ <0 0x16028400 0 0x400>; /* VDEC_HWG */ interrupts = ; - mediatek,larb = <&larb1>; iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, <&iommu M4U_PORT_HW_VDEC_PP_EXT>, <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, @@ -1467,7 +1454,6 @@ compatible = "mediatek,mt8173-vcodec-enc"; reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ interrupts = ; - mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_VENC_RCPU>, <&iommu M4U_PORT_VENC_REC>, <&iommu M4U_PORT_VENC_BSDMA>, @@ -1495,7 +1481,6 @@ clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; - mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, <&iommu M4U_PORT_JPGDEC_BSDMA>; }; @@ -1529,7 +1514,6 @@ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,larb = <&larb5>; mediatek,vpu = <&vpu>; clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names = "venc_lt_sel"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index d1448a0b86cb..be9728526ed3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1396,7 +1396,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; @@ -1407,7 +1406,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; @@ -1418,7 +1416,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; @@ -1429,7 +1426,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; @@ -1441,7 +1437,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb0>; mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1598,7 +1593,6 @@ compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; reg = <0 0x17030000 0 0x1000>; interrupts = ; - mediatek,larb = <&larb4>; iommus = <&iommu M4U_PORT_JPGENC_RDMA>, <&iommu M4U_PORT_JPGENC_BSDMA>; power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; From dab2782be22c359dd1a14a118e9b1592a7f91db3 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 21 Apr 2022 11:51:10 +0800 Subject: [PATCH 514/791] arm64: dts: mediatek: mt8173: Add power domain to encoder nodes The power of encoder is not control by mediatek,larb, so we add power domain to encoder nodes for mt8173 SoC. Signed-off-by: Irui Wang Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220421035111.7267-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 10291b2690ab..eebc2d074254 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1470,6 +1470,7 @@ clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; }; jpegdec: jpegdec@18004000 { @@ -1520,6 +1521,7 @@ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; }; }; }; From 3b7d143be4b7cf09cf19b04e78669ce0c970cc76 Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Thu, 21 Apr 2022 09:26:23 +0800 Subject: [PATCH 515/791] arm64: dts: mt6359: add PMIC MT6359 related nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT6359 is the primary PMIC for MT8192. Add PMIC MT6359 related node which is used for MT8192 platform. Signed-off-by: Hui Liu Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220421012623.3446-2-hui.liu@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 298 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 1 + 2 files changed, 299 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6359.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi new file mode 100644 index 000000000000..df3e822232d3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ + +&pwrap { + pmic: pmic { + compatible = "mediatek,mt6359"; + interrupt-controller; + #interrupt-cells = <2>; + + mt6359codec: mt6359codec { + }; + + regulators { + mt6359_vs1_buck_reg: buck_vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + mt6359_vgpu11_buck_reg: buck_vgpu11 { + regulator-name = "vgpu11"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vmodem_buck_reg: buck_vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <10760>; + regulator-enable-ramp-delay = <200>; + }; + mt6359_vpu_buck_reg: buck_vpu { + regulator-name = "vpu"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vcore_buck_reg: buck_vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vs2_buck_reg: buck_vs2 { + regulator-name = "vs2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1600000>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + mt6359_vpa_buck_reg: buck_vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-enable-ramp-delay = <300>; + }; + mt6359_vproc2_buck_reg: buck_vproc2 { + regulator-name = "vproc2"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vproc1_buck_reg: buck_vproc1 { + regulator-name = "vproc1"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vcore_sshub_buck_reg: buck_vcore_sshub { + regulator-name = "vcore_sshub"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + }; + mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub { + regulator-name = "vgpu11_sshub"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + }; + mt6359_vaud18_ldo_reg: ldo_vaud18 { + regulator-name = "vaud18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vsim1_ldo_reg: ldo_vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6359_vibr_ldo_reg: ldo_vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vrf12_ldo_reg: ldo_vrf12 { + regulator-name = "vrf12"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + mt6359_vusb_ldo_reg: ldo_vusb { + regulator-name = "vusb"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <960>; + regulator-always-on; + }; + mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 { + regulator-name = "vsram_proc2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vio18_ldo_reg: ldo_vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <960>; + regulator-always-on; + }; + mt6359_vcamio_ldo_reg: ldo_vcamio { + regulator-name = "vcamio"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + mt6359_vcn18_ldo_reg: ldo_vcn18 { + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vfe28_ldo_reg: ldo_vfe28 { + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <120>; + }; + mt6359_vcn13_ldo_reg: ldo_vcn13 { + regulator-name = "vcn13"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + }; + mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { + regulator-name = "vcn33_1_bt"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { + regulator-name = "vcn33_1_wifi"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vaux18_ldo_reg: ldo_vaux18 { + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vsram_others_ldo_reg: ldo_vsram_others { + regulator-name = "vsram_others"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vefuse_ldo_reg: ldo_vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + }; + mt6359_vxo22_ldo_reg: ldo_vxo22 { + regulator-name = "vxo22"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + mt6359_vrfck_ldo_reg: ldo_vrfck { + regulator-name = "vrfck"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1700000>; + }; + mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 { + regulator-name = "vrfck"; + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1600000>; + }; + mt6359_vbif28_ldo_reg: ldo_vbif28 { + regulator-name = "vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vio28_ldo_reg: ldo_vio28 { + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + mt6359_vemc_ldo_reg: ldo_vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vemc_1_ldo_reg: ldo_vemc_1 { + regulator-name = "vemc"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { + regulator-name = "vcn33_2_bt"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { + regulator-name = "vcn33_2_wifi"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_va12_ldo_reg: ldo_va12 { + regulator-name = "va12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + mt6359_va09_ldo_reg: ldo_va09 { + regulator-name = "va09"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + }; + mt6359_vrf18_ldo_reg: ldo_vrf18 { + regulator-name = "vrf18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1810000>; + }; + mt6359_vsram_md_ldo_reg: ldo_vsram_md { + regulator-name = "vsram_md"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <10760>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vufs_ldo_reg: ldo_vufs { + regulator-name = "vufs"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + mt6359_vm18_ldo_reg: ldo_vm18 { + regulator-name = "vm18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-always-on; + }; + mt6359_vbbck_ldo_reg: ldo_vbbck { + regulator-name = "vbbck"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + }; + mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 { + regulator-name = "vsram_proc1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vsim2_ldo_reg: ldo_vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { + regulator-name = "vsram_others_sshub"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + }; + }; + + mt6359rtc: mt6359rtc { + compatible = "mediatek,mt6358-rtc"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts index 0205837fa698..808be492e970 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8192.dtsi" +#include "mt6359.dtsi" / { model = "MediaTek MT8192 evaluation board"; From b59add5e6e5a66ae3f6a42a573b6e56b6dbaee41 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 19 Apr 2022 17:20:30 +0800 Subject: [PATCH 516/791] dt-bindings: arm: Add compatible for Mediatek MT8192 This commit adds dt-binding documentation for the Mediatek MT8192 reference board. Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220419092030.30519-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index ab0593c77321..3a9b92ee915b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -131,6 +131,10 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8192-evb + - const: mediatek,mt8192 - items: - enum: - mediatek,mt8195-evb From a8bbcf703cf3c5cb63dd8516abc87262ad86b635 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 19 Apr 2022 14:32:26 +0800 Subject: [PATCH 517/791] arm64: dts: mt8192: Add spmi node Add spmi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220419063226.15958-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a6da7b04b9d4..164fae36a3d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -537,6 +537,21 @@ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; }; + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; From 1afd9b62f95f51d68d38a006100a392b7761c53f Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 19 Apr 2022 10:55:57 +0800 Subject: [PATCH 518/791] arm64: dts: mt8192: Add audio-related nodes Add audio-related nodes in audsys for mt8192 SoC. - Move audsys node in ascending order. - Increase the address range's length from 0x1000 to 0x2000. Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220419025557.22262-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++- 1 file changed, 129 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 164fae36a3d8..9a8310f907b3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -731,6 +731,135 @@ status = "disabled"; }; + audsys: syscon@11210000 { + compatible = "mediatek,mt8192-audsys", "syscon"; + reg = <0 0x11210000 0 0x2000>; + #clock-cells = <1>; + + afe: mt8192-afe-pcm { + compatible = "mediatek,mt8192-audio"; + interrupts = ; + resets = <&watchdog 17>; + reset-names = "audiosys"; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg>; + mediatek,topckgen = <&topckgen>; + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; + clocks = <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&audsys CLK_AUD_ADC>, + <&audsys CLK_AUD_ADDA6_ADC>, + <&audsys CLK_AUD_22M>, + <&audsys CLK_AUD_24M>, + <&audsys CLK_AUD_APLL_TUNER>, + <&audsys CLK_AUD_APLL2_TUNER>, + <&audsys CLK_AUD_TDM>, + <&audsys CLK_AUD_TML>, + <&audsys CLK_AUD_NLE>, + <&audsys CLK_AUD_DAC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES_TML>, + <&audsys CLK_AUD_ADDA6_ADC_HIRES>, + <&audsys CLK_AUD_3RD_DAC>, + <&audsys CLK_AUD_3RD_DAC_PREDIS>, + <&audsys CLK_AUD_3RD_DAC_TML>, + <&audsys CLK_AUD_3RD_DAC_HIRES>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_MAINPLL_D4_D4>, + <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_AUD_2_SEL>, + <&topckgen CLK_TOP_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, + <&topckgen CLK_TOP_APLL1_D4>, + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + <&topckgen CLK_TOP_APLL12_DIV5>, + <&topckgen CLK_TOP_APLL12_DIV6>, + <&topckgen CLK_TOP_APLL12_DIV7>, + <&topckgen CLK_TOP_APLL12_DIV8>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_AUDIO_H_SEL>, + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adda6_adc_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_tdm_clk", + "aud_tml_clk", + "aud_nle", + "aud_dac_hires_clk", + "aud_adc_hires_clk", + "aud_adc_hires_tml", + "aud_adda6_adc_hires_clk", + "aud_3rd_dac_clk", + "aud_3rd_dac_predis_clk", + "aud_3rd_dac_tml", + "aud_3rd_dac_hires_clk", + "aud_infra_clk", + "aud_infra_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d4_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d4", + "top_mux_aud_eng2", + "top_apll2_d4", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_i2s6_m_sel", + "top_i2s7_m_sel", + "top_i2s8_m_sel", + "top_i2s9_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + "top_apll12_div5", + "top_apll12_div6", + "top_apll12_div7", + "top_apll12_div8", + "top_apll12_div9", + "top_mux_audio_h", + "top_clk26m_clk"; + }; + }; + pcie: pcie@11230000 { compatible = "mediatek,mt8192-pcie"; device_type = "pci"; @@ -781,12 +910,6 @@ status = "disabled"; }; - audsys: clock-controller@11210000 { - compatible = "mediatek,mt8192-audsys", "syscon"; - reg = <0 0x11210000 0 0x1000>; - #clock-cells = <1>; - }; - efuse: efuse@11c10000 { compatible = "mediatek,efuse"; reg = <0 0x11c10000 0 0x1000>; From 71b946e9505510bdf2f84241205635c2f2da3e66 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Mon, 11 Apr 2022 11:58:42 +0800 Subject: [PATCH 519/791] arm64: dts: mt8183: Update disp_aal node compatible The driver data of MT8183 and MT8173 are different. The value of has_gamma for MT8173 is true while the value of MT8183 is false. Therefore, the compatible of disp_aal for MT8183 is not suitable for the compatible for MT8173. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220411035843.19847-3-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index be9728526ed3..01e650251928 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1461,8 +1461,7 @@ }; aal0: aal@14010000 { - compatible = "mediatek,mt8183-disp-aal", - "mediatek,mt8173-disp-aal"; + compatible = "mediatek,mt8183-disp-aal"; reg = <0 0x14010000 0 0x1000>; interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; From db61337e49a8324d3e7cae3450db22cf2bf87369 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 7 Apr 2022 19:37:03 +0800 Subject: [PATCH 520/791] arm64: dts: mt8192: Add mmc device nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In mt8192 SoC, mmc driver dose not use the MSDC module to control clock. It will read/write register to enable/disable clock. Also there is no other device of mt8192 using MSDC controller. We add mmc nodes for mt8192 SoC and remove the clock-controller in dts for avoid a duplicate unit-address(11f60000) warning. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220407113703.26423-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 9a8310f907b3..26dbe9ecc528 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1123,10 +1123,36 @@ #clock-cells = <1>; }; - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0 0x11f60000 0 0x1000>; - #clock-cells = <1>; + mmc0: mmc@11f60000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; }; mfgcfg: clock-controller@13fbf000 { From 37f2582883be7218dc69f9af135959a8e93de223 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Mon, 11 Apr 2022 10:27:24 +0800 Subject: [PATCH 521/791] arm64: dts: Add mediatek SoC mt8195 and evaluation board Add basic chip support for mediatek mt8195. Signed-off-by: Seiya Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220411022724.11005-3-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 181 ++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++++ 3 files changed, 1227 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 8c1e18032f9f..5da29e7223e4 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -38,4 +38,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts new file mode 100644 index 000000000000..db25a515e420 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8195.dtsi" + +/ { + model = "MediaTek MT8195 evaluation board"; + compatible = "mediatek,mt8195-evb", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&auxadc { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pin>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&nor_flash { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&pio { + i2c0_pin: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <0>; + drive-strength = <6>; + }; + }; + + i2c1_pin: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <0>; + drive-strength = <6>; + }; + }; + + i2c4_pin: i2c4-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c6_pin: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + }; + }; + + i2c7_pin: i2c7-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + }; + }; + + nor_pins_default: nor-pins { + pins0 { + pinmux = , + , + ; + bias-pull-down; + }; + + pins1 { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + uart0_pin: uart0-pins { + pins { + pinmux = , + ; + }; + }; +}; + +&u3phy0 { + status="okay"; +}; + +&u3phy1 { + status="okay"; +}; + +&u3phy2 { + status="okay"; +}; + +&u3phy3 { + status="okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pin>; + status = "okay"; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci1 { + status = "okay"; +}; + +&xhci2 { + status = "okay"; +}; + +&xhci3 { + /* This controller is connected with a BT device. + * Disable usb2 lpm to prevent known issues. + */ + usb2-lpm-disable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi new file mode 100644 index 000000000000..b57e620c2c72 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -0,0 +1,1045 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Seiya Wang + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8195"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <95>; + min-residency-us = <580>; + }; + + cpu_off_b: cpu-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <45>; + exit-latency-us = <140>; + min-residency-us = <740>; + }; + + cluster_off_l: cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <55>; + exit-latency-us = <155>; + min-residency-us = <840>; + }; + + cluster_off_b: cluster-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + dsu-pmu { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8195-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ + 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ + >; + }; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8195-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8195-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11eb0000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 144>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8195-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8195-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8195-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CLK26M_D2>; + }; + + pwrap: pwrap@10024000 { + compatible = "mediatek,mt8195-pwrap", "syscon"; + reg = <0 0x10024000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + }; + + scp_adsp: clock-controller@10720000 { + compatible = "mediatek,mt8195-scp_adsp"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11001100 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001100 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11001200 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001200 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11001300 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001300 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11001400 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001400 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart4: serial@11001500 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001500 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart5: serial@11001600 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001600 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + auxadc: auxadc@11002000 { + compatible = "mediatek,mt8195-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11002000 0 0x1000>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + pericfg_ao: syscon@11003000 { + compatible = "mediatek,mt8195-pericfg_ao", "syscon"; + reg = <0 0x11003000 0 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spis0: spi@1101d000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101d000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + + spis1: spi@1101e000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101e000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + + xhci0: usb@11200000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, + <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&topckgen CLK_TOP_SSUSB_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11e60000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_2>, + <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, + <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + xhci1: usb@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&topckgen CLK_TOP_SSUSB_P1_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; + status = "disabled"; + }; + + xhci2: usb@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&topckgen CLK_TOP_SSUSB_P2_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names = "sys_ck", "ref_ck", "xhci_ck"; + status = "disabled"; + }; + + xhci3: usb@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port3 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&topckgen CLK_TOP_SSUSB_P3_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names = "sys_ck", "ref_ck", "xhci_ck"; + status = "disabled"; + }; + + nor_flash: spi@1132c000 { + compatible = "mediatek,mt8195-nor", + "mediatek,mt8173-nor"; + reg = <0 0x1132c000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SPINOR>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; + clock-names = "spi", "sf", "axi"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + u3phy2: t-phy@11c40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy3: t-phy@11c50000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + i2c5: i2c@11d00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x10220580 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@11d01000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d01000 0 0x1000>, + <0 0x10220600 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11d02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d02000 0 0x1000>, + <0 0x10220680 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_s: clock-controller@11d03000 { + compatible = "mediatek,mt8195-imp_iic_wrap_s"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + + i2c0: i2c@11e00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e00000 0 0x1000>, + <0 0x10220080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + i2c1: i2c@11e01000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e01000 0 0x1000>, + <0 0x10220200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11e02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e02000 0 0x1000>, + <0 0x10220380 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11e03000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e03000 0 0x1000>, + <0 0x10220480 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11e04000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e04000 0 0x1000>, + <0 0x10220500 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_w: clock-controller@11e05000 { + compatible = "mediatek,mt8195-imp_iic_wrap_w"; + reg = <0 0x11e05000 0 0x1000>; + #clock-cells = <1>; + }; + + u3phy1: t-phy@11e30000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0xe00>; + status = "disabled"; + + u2port1: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port1: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + u3phy0: t-phy@11e40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0xe00>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + ufsphy: ufs-phy@11fa0000 { + compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; + reg = <0 0x11fa0000 0 0xc000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "unipro", "mp"; + #phy-cells = <0>; + status = "disabled"; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt8195-mfgcfg"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys: clock-controller@14e00000 { + compatible = "mediatek,mt8195-wpesys"; + reg = <0 0x14e00000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp0: clock-controller@14e02000 { + compatible = "mediatek,mt8195-wpesys_vpp0"; + reg = <0 0x14e02000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp1: clock-controller@14e03000 { + compatible = "mediatek,mt8195-wpesys_vpp1"; + reg = <0 0x14e03000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8195-imgsys"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_dip_top: clock-controller@15110000 { + compatible = "mediatek,mt8195-imgsys1_dip_top"; + reg = <0 0x15110000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_dip_nr: clock-controller@15130000 { + compatible = "mediatek,mt8195-imgsys1_dip_nr"; + reg = <0 0x15130000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_wpe: clock-controller@15220000 { + compatible = "mediatek,mt8195-imgsys1_wpe"; + reg = <0 0x15220000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@15330000 { + compatible = "mediatek,mt8195-ipesys"; + reg = <0 0x15330000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@16000000 { + compatible = "mediatek,mt8195-camsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: clock-controller@1604f000 { + compatible = "mediatek,mt8195-camsys_rawa"; + reg = <0 0x1604f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuva: clock-controller@1606f000 { + compatible = "mediatek,mt8195-camsys_yuva"; + reg = <0 0x1606f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1608f000 { + compatible = "mediatek,mt8195-camsys_rawb"; + reg = <0 0x1608f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuvb: clock-controller@160af000 { + compatible = "mediatek,mt8195-camsys_yuvb"; + reg = <0 0x160af000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_mraw: clock-controller@16140000 { + compatible = "mediatek,mt8195-camsys_mraw"; + reg = <0 0x16140000 0 0x1000>; + #clock-cells = <1>; + }; + + ccusys: clock-controller@17200000 { + compatible = "mediatek,mt8195-ccusys"; + reg = <0 0x17200000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_soc: clock-controller@1800f000 { + compatible = "mediatek,mt8195-vdecsys_soc"; + reg = <0 0x1800f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@1802f000 { + compatible = "mediatek,mt8195-vdecsys"; + reg = <0 0x1802f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_core1: clock-controller@1803f000 { + compatible = "mediatek,mt8195-vdecsys_core1"; + reg = <0 0x1803f000 0 0x1000>; + #clock-cells = <1>; + }; + + apusys_pll: clock-controller@190f3000 { + compatible = "mediatek,mt8195-apusys_pll"; + reg = <0 0x190f3000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@1a000000 { + compatible = "mediatek,mt8195-vencsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys_core1: clock-controller@1b000000 { + compatible = "mediatek,mt8195-vencsys_core1"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; From cc9d1e59f47562a3b9c812c29d84996e36234308 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 15 Apr 2022 17:00:00 +0200 Subject: [PATCH 522/791] dt-bindings: arm64: dts: mediatek: Add mt8195-demo board Add bindings for the MediaTek mt8195-demo board. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220415150003.1793063-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 3a9b92ee915b..4a2bd9759c47 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -137,6 +137,7 @@ properties: - const: mediatek,mt8192 - items: - enum: + - mediatek,mt8195-demo - mediatek,mt8195-evb - const: mediatek,mt8195 - description: Google Burnet (HP Chromebook x360 11MK G3 EE) From 6147314aeedc24ecf70ea5656884b03cba836782 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 15 Apr 2022 17:00:01 +0200 Subject: [PATCH 523/791] arm64: dts: mediatek: Add device-tree for MT8195 Demo board Add basic device-tree for the MT8195 Demo board. The Demo board is made by MediaTek and has a MT8195 SoC, associated with the MT6359 and MT6360 PMICs, and the MT7921 connectivity chip. The IOs available on that board are: * 1 USB Type-C connector with DP aux mode support * 1 USB Type-A connector * 1 full size HDMI RX and 1 full size HDMI TX connector * 1 uSD slot * 40 pins header * SPI interface header * 1 M.2 slot * 1 audio jack * 1 micro-USB port for serial debug * 2 connectors for DSI displays * 3 connectors for CSI cameras * 1 connector for a eDP panel * 1 MMC storage This commit adds basic support in order to be able to boot. Signed-off-by: Fabien Parent Tested-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220415150003.1793063-3-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 445 +++++++++++++++++++ 2 files changed, 446 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-demo.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 5da29e7223e4..c7d4636a2cb7 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -38,5 +38,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts new file mode 100644 index 000000000000..def3fc26cb99 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 BayLibre, SAS. + * Author: Fabien Parent + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +#include +#include +#include +#include + +/ { + model = "MediaTek MT8195 demo board"; + compatible = "mediatek,mt8195-demo", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-0 { + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x30000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-compatible = "usb-otg-vbus"; + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "mt6360,buck1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "mt6360,buck2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "mt6360,ldo1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo2: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "mt6360,ldo2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "mt6360,ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "mt6360,ldo5"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo6: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "mt6360,ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "mt6360,ldo7"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x14c11>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-always-on; +}; + +&pio { + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = ; + input-enable; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; +}; + + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&xhci0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&otg_vbus_regulator>; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; From caaff77ffb3f186c2f2df61fa91fb409ea2d929b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 28 Feb 2022 12:03:29 +0100 Subject: [PATCH 524/791] arm64: dts: mediatek: mt8173: Add gce-client-reg handle to disp-mutex Add a gce client reg handle to the disp mutex to enable MT8173 platforms to use MediaTek's CMDQ for extra performance. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220228110329.245366-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index eebc2d074254..40d7b47fc52e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1278,6 +1278,7 @@ interrupts = ; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_MUTEX_32K>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; mediatek,gce-events = , ; }; From 402eb8ec54b36f8fc0649768c01abb57062d6f8b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:23 +0200 Subject: [PATCH 525/791] arm64: dts: microchip: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20220407143223.295344-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/microchip/sparx5_nand.dtsi | 2 +- arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 4 ++-- arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 4 ++-- arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi index 03f107e427d7..ce0747fd6444 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi @@ -19,7 +19,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <14>; /* CS14 */ - spi-flash@6 { + flash@6 { compatible = "spi-nand"; pinctrl-0 = <&cs14_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 9baa085d7861..dbf8c1d48a02 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ @@ -59,7 +59,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CS1 */ - spi-flash@9 { + flash@9 { compatible = "spi-nand"; pinctrl-0 = <&cs1_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 33faf1f3264f..699256f1b9d8 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -274,7 +274,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0>; @@ -289,7 +289,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index ef96e6d8c6b3..d10a9172b529 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -89,7 +89,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0>; @@ -104,7 +104,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ From 2f00bb4a69c770b7957b9b4621323c2f84fc6538 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:34 +0200 Subject: [PATCH 526/791] arm64: dts: marvell: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220407143234.295426-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 2 +- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ++-- arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts | 2 +- arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 +- arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ++-- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts | 2 +- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 2 +- arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +- arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 2 +- 12 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 3e5789f37206..bd4e61d5448e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -164,7 +164,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <108000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 1cee26479bfe..d665f742a7d5 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -211,7 +211,7 @@ assigned-clock-parents = <&tbg 1>; assigned-clock-rates = <20000000>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts index 95d46e8d081c..a4de8d00cf46 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <54000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index cd326fe224ce..5e5baf6beea4 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -83,7 +83,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -186,7 +186,7 @@ &cp0_spi1 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index f3b0d57a24a3..39a8e5e99d79 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -155,7 +155,7 @@ pinctrl-names = "default"; pinctrl-0 = <&cp0_spi1_pins>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 8729c6467303..871f84b4a6ed 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -589,7 +589,7 @@ pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index f2e8e0df8865..92897bd7e6cf 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -72,7 +72,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -238,7 +238,7 @@ &cp1_spi1 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index adbfecc678b5..779cf167c33e 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -360,7 +360,7 @@ pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts index dac85fa748de..74bed79e4f5e 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -185,7 +185,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index d9f9f2c19740..1acd746284dc 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -175,7 +175,7 @@ <0x2000000 0x1000000>; /* CS0 */ status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index c00b69b88bd2..7e20987253a3 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -310,7 +310,7 @@ pinctrl-0 = <&cp0_spi0_pins>; reg = <0x700680 0x50>; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index f995b1bcda01..b7fc241a228c 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -137,7 +137,7 @@ pinctrl-0 = <&cp1_spi0_pins>; reg = <0x700680 0x50>; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; From 47a08153f32dc7d38953c84e3f2c07059411ce66 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 31 Mar 2022 19:33:31 +0530 Subject: [PATCH 527/791] arm64: tegra: Add ASRC device on Tegra186 and later Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is present on Tegra186 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 8 ++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index e9b40f5d79ec..2e7faa1e0b9c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -516,6 +516,13 @@ sound-name-prefix = "MIXER1"; status = "disabled"; }; + + tegra_asrc: asrc@2910000 { + compatible = "nvidia,tegra186-asrc"; + reg = <0x2910000 0x2000>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 1d6be5774fac..f9d343b24597 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -569,6 +569,14 @@ sound-name-prefix = "MIXER1"; status = "disabled"; }; + + tegra_asrc: asrc@2910000 { + compatible = "nvidia,tegra194-asrc", + "nvidia,tegra186-asrc"; + reg = <0x2910000 0x2000>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8767dbe2d066..71c21d7d0551 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -378,6 +378,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_APE>; status = "disabled"; }; + + tegra_asrc: asrc@2910000 { + compatible = "nvidia,tegra234-asrc", + "nvidia,tegra186-asrc"; + reg = <0x2910000 0x2000>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; }; adma: dma-controller@2930000 { From 261a46a977c6babde207d5e979fe5cf779b067b9 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 31 Mar 2022 19:33:32 +0530 Subject: [PATCH 528/791] arm64: tegra: Enable ASRC on various platforms Enable ASRC module usage on various Jetson Platforms. This can be plugged into an audio path using ALSA mixer controls. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 223 ++++++++++++++++++ .../boot/dts/nvidia/tegra194-p2972-0000.dts | 223 ++++++++++++++++++ .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 223 ++++++++++++++++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 223 ++++++++++++++++++ 4 files changed, 892 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index c4dee05f330c..70737a09a9b8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -811,6 +811,110 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; admaif@290f000 { @@ -1935,6 +2039,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; }; @@ -2331,6 +2548,10 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2348,6 +2569,8 @@ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* I/O */ <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 27d28626bf5b..bce518ace6a0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -764,6 +764,110 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; admaif@290f000 { @@ -1734,6 +1838,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; }; @@ -2052,6 +2269,10 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2068,6 +2289,8 @@ <&adx4_out3_port>, <&adx4_out4_port>, <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* BE I/O Ports */ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 8033be098f34..7acc32dd290a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -774,6 +774,110 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; admaif@290f000 { @@ -1794,6 +1898,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; }; @@ -2102,6 +2319,10 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2119,6 +2340,8 @@ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* BE I/O Ports */ <&i2s3_port>, <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic4_port>, diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 34d6a01ee1c6..eaf1994abb04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -763,6 +763,110 @@ remote-endpoint = <&mix_out5>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; i2s@2901000 { @@ -1733,6 +1837,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; dma-controller@2930000 { @@ -1823,6 +2040,10 @@ <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -1839,6 +2060,8 @@ <&adx4_out3_port>, <&adx4_out4_port>, <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* BE I/O Ports */ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; From 49148f4c39f04cb7bcfc1f42c3051d9ef8655fba Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 Apr 2022 23:40:16 +0200 Subject: [PATCH 529/791] ARM: dts: ux500: Add GPS to the Codina The Codina has a Broadcom BCM4751 GPS chip. Signed-off-by: Linus Walleij --- .../arm/boot/dts/ste-ux500-samsung-codina.dts | 32 ++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 0b7bb54aa24d..b6746ac167bc 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -480,10 +480,20 @@ uart@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; - /* CTS/RTS is not used, CTS is repurposed as GPIO */ - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + compatible = "brcm,bcm4751"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + enable-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&bcm4751_codina_default>; + }; }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ @@ -883,6 +893,20 @@ }; }; }; + bcm4751 { + bcm4751_codina_default: bcm4751_codina { + /* Reset line, start out asserted */ + codina_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + codina_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; vibrator { vibrator_default: vibrator_default { codina_cfg1 { From 439677d416b17dd39964d5f7d64b742a2e51da5b Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 19 Apr 2022 09:51:57 +0200 Subject: [PATCH 530/791] arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates We found that (at least some versions of) the sci-fw set the base clock rate for UARTs in the MCU domain to 96 MHz instead of the expected 48 MHz, leading to incorrect baud rates when used from Linux. As the 8250_omap driver will query the actual clock rate from the clk driver when clock-frequency is unset, removing the incorrect property is sufficient to fix the baud rate. Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by: Matthias Schiffer Signed-off-by: Vignesh Raghavendra Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20220419075157.189347-1-matthias.schiffer@ew.tq-group.com --- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 2bb5c9ff172c..02d4285acbb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -10,7 +10,6 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; interrupts = ; - clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; @@ -21,7 +20,6 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; interrupts = ; - clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; From 065d62612e264e228c153afe9aa31d85aeea3d17 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 14 Apr 2022 19:06:12 +0530 Subject: [PATCH 531/791] arm64: dts: ti: k3-am642-sk: Enable WLAN connected to SDHCI0 WL1837 module is connected to SDHCI0 in AM642 SK. Enable it here. This will enable the WiFi functionaliy on the board. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Vignesh Raghavendra Signed-off-by: Nikhil Devshatwar Signed-off-by: Aparna M Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220414133612.13365-1-a-m1@ti.com --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 62 ++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 1d7db8bf3a5c..59f506cbd275 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -125,6 +125,31 @@ vin-supply = <&vcc_3v3_sys>; gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; + + com8_ls_en: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "com8_ls_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + pinctrl-0 = <&main_com8_ls_en_pins_default>; + pinctrl-names = "default"; + gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; + }; + + wlan_en: regulator-2 { + /* output of SN74AVC4T245RSVR */ + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&main_wlan_en_pins_default>; + pinctrl-names = "default"; + vin-supply = <&com8_ls_en>; + gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; + }; }; &main_pmx0 { @@ -216,6 +241,23 @@ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; + main_wlan_en_pins_default: main-wlan-en-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ + >; + }; + + main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ + >; + }; + + main_wlan_pins_default: main-wlan-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ + >; + }; }; &mcu_uart0 { @@ -293,6 +335,26 @@ status = "reserved"; }; +&sdhci0 { + vmmc-supply = <&wlan_en>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + pinctrl-0 = <&main_wlan_pins_default>; + pinctrl-names = "default"; + interrupt-parent = <&main_gpio0>; + interrupts = <46 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; From c37c58fdeb8a9ddaff2ae512bf738ac7a5d3cd2e Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 27 Apr 2022 12:59:53 +0530 Subject: [PATCH 532/791] arm64: dts: ti: k3-am62: Add more peripheral nodes Add nodes for McSPI, OSPI, DMA, CPSW, MMC and On Chip SRAM nodes. Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220427072954.8821-2-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 266 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 20 ++ 2 files changed, 286 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index c68472c692f4..eec8dae65e7c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -6,6 +6,14 @@ */ &cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x70000000 0x10000>; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -40,6 +48,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; }; dmss: bus@48000000 { @@ -61,6 +75,69 @@ interrupt-names = "rx_012"; interrupts = ; }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <4 68 36>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; }; dmsc: system-controller@44043000 { @@ -203,6 +280,36 @@ clock-names = "fck"; }; + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 174 0>; + }; + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; @@ -249,6 +356,165 @@ clock-names = "gpio"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + ti,trm-icp = <0x2>; + bus-width = <8>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x9>; + ti,otap-del-sel-hs200 = <0x6>; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + bus-width = <4>; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x08000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&wkup_conf 0x200>; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 13 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 9d210d55fc71..d103824c963f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -33,4 +33,24 @@ clocks = <&k3_clks 106 2>; clock-names = "fck"; }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + }; }; From d19a66ae488afe23398090b5dbe5483b26863e13 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 27 Apr 2022 12:59:54 +0530 Subject: [PATCH 533/791] arm64: dts: ti: k3-am625-sk: Enable on board peripherals Add nodes for I2C IO expander, OSPI Flash, Eth PHYs, SD and eMMC that are present on AM625 SK board. Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220427072954.8821-3-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 273 +++++++++++++++++++++++++ 1 file changed, 273 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 0de4113ccd5d..5c38ee5ff9b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -9,6 +9,7 @@ #include #include +#include #include "k3-am625.dtsi" / { @@ -17,6 +18,12 @@ aliases { serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; chosen { @@ -87,6 +94,33 @@ regulator-boot-on; }; + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-4 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -124,11 +158,114 @@ >; }; + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; + usr_led_pins_default: usr-led-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; }; &wkup_uart0 { @@ -188,6 +325,33 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "WL_LT_EN", + "GPIO_HDMI_RSTn", "CSI_GPIO1", + "CSI_GPIO2", "PRU_3V3_EN", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "TSINT#", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; }; &main_i2c2 { @@ -198,9 +362,118 @@ status = "disabled"; }; +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default + &main_rgmii1_pins_default + &main_rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + &mailbox0_cluster0 { mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; }; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; From bd67e1be98ddb884ff3f3df95c2382e6e70930b6 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Tue, 19 Apr 2022 11:59:02 +0530 Subject: [PATCH 534/791] arm64: dts: ti: k3-am625-sk: Add ECAP APWM nodes AM62 has 3 ECAP instances with 1 APWM each. Add DT nodes for the same. Keep them disabled in am625-sk dts as these pins can be repurposed in user exp connector. Signed-off-by: Vignesh Raghavendra Reviewed-by: Aswath Govindraju Link: https://lore.kernel.org/r/20220419062902.196526-1-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 27 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-sk.dts | 12 +++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index eec8dae65e7c..9f32b6dad8a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -530,4 +530,31 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 5c38ee5ff9b2..3b6a20e342ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -477,3 +477,15 @@ }; }; }; + +&ecap0 { + status = "disabled"; +}; + +&ecap1 { + status = "disabled"; +}; + +&ecap2 { + status = "disabled"; +}; From d196d2a98d62c505ab71caf2630575e448dc417c Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 21 Apr 2022 11:49:38 +0530 Subject: [PATCH 535/791] arm64: dts: ti: k3-am62-mcu: Enable MCU GPIO module AM62 has x1 GPIO module and associated interrupt router in MCU Domain. Add DT nodes for the same. Signed-off-by: Vignesh Raghavendra Reviewed-by: Aswath Govindraju Link: https://lore.kernel.org/r/20220421061938.122317-1-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index d103824c963f..f56c803560f2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -53,4 +53,32 @@ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x4201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; }; From 2492a974022081935fbcb0f1bf8a80fc39812806 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 18 Apr 2022 17:28:01 +0530 Subject: [PATCH 536/791] arm64: dts: ti: k3-am62: Add support for MCAN AM62 SoC has one instance of MCAN in main domain. However, its corresponding CAN signals are not brought out through a transceiver, on the SK board. Therefore, add the device tree node in the main dt file and set the status to disabled in the SK board dts file. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220418115802.5672-1-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-sk.dts | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 9f32b6dad8a9..d08abad0bcf4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -557,4 +557,18 @@ clocks = <&k3_clks 53 0>; clock-names = "fck"; }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 3b6a20e342ed..39fb1d763037 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -489,3 +489,7 @@ &ecap2 { status = "disabled"; }; + +&main_mcan0 { + status = "disabled"; +}; From 7a5ae564198d536a53bb11ed0eb6679ee0fced10 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 20 Apr 2022 17:42:44 +0900 Subject: [PATCH 537/791] dt-bindings: power: renesas,rcar-sysc: Document r8a779g0 SYSC bindings Document bindings for the R-Car V4H (aka R8A779G0) SYSC block. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220420084255.375700-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 62a49ca319ec..72039401af3d 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -42,6 +42,7 @@ properties: - renesas,r8a77995-sysc # R-Car D3 - renesas,r8a779a0-sysc # R-Car V3U - renesas,r8a779f0-sysc # R-Car S4-8 + - renesas,r8a779g0-sysc # R-Car V4H reg: maxItems: 1 From 358d1cef2a88f590a183a0357b944674097ec0ab Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 30 Mar 2022 16:40:12 +0100 Subject: [PATCH 538/791] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output The RZ/V2M Evaluation Kit (V2MEVK) consists of the RZ/V2M Main Board, RZ/V2M Base Board, and CIS IMX415 Board (CIS). Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220330154024.112270-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 5408b154d05e..ff80152f092f 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -444,6 +444,12 @@ properties: - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L - const: renesas,r9a07g054 + - description: RZ/V2M (R9A09G011) + items: + - enum: + - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 + - const: renesas,r9a09g011 + additionalProperties: true ... From ed66b37f916ee23b308c3f50288131d51a2682e9 Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Fri, 22 Apr 2022 14:08:47 +0200 Subject: [PATCH 539/791] ARM: dts: r9a06g032: Add missing '#power-domain-cells' Without '#power-domain-cells' property, power-domains cannot be used. This property is noted required in the device-tree binding. Add '#power-domain-cells' as needed. Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20220422120850.769480-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 2257706ce84f..cd9dc815089f 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -87,6 +87,7 @@ reg = <0x4000c000 0x1000>; status = "okay"; #clock-cells = <1>; + #power-domain-cells = <0>; clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, <&ext_rgmii_ref>; From bc9e1dbb175706242a7160675b4f52d0380ae4ea Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:18 +0100 Subject: [PATCH 540/791] arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub nodes Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 73 +++++++++++++++++++++- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c8aadbe55278..2025224d71ab 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -220,22 +220,89 @@ i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { From 559f2b0708c70c49ae3143d481ee10351089e590 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:19 +0100 Subject: [PATCH 541/791] arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 80 +++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 2025224d71ab..ef8550a2de09 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -75,9 +75,87 @@ ranges; ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; #sound-dai-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; }; spi1: spi@1004b000 { From f52e14095e56ab6470d959f08e40aa2e45cb85cd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:20 +0100 Subject: [PATCH 542/791] arm64: dts: renesas: r9a07g043: Add USB2.0 support Add USB2.0 host and device support by filling usb phy control, phy, device and host stub nodes in RZ/G2UL SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 90 ++++++++++++++++++++-- 1 file changed, 82 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index ef8550a2de09..8bcda969d130 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -551,43 +551,117 @@ }; phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g043-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; reg = <0 0x11c40000 0 0x10000>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; + resets = <&cpg R9A07G043_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; }; ohci0: usb@11c50000 { + compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ohci1: usb@11c70000 { + compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G043_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ehci0: usb@11c50100 { + compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; }; ehci1: usb@11c70100 { + compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G043_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g043", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g043", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g043", + "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; wdt0: watchdog@12800800 { From 1de1b44833e394e63119fcff37e458a94c244799 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:21 +0100 Subject: [PATCH 543/791] arm64: dts: renesas: r9a07g043: Fillup the CANFD stub node Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 31 +++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 8bcda969d130..60db9b02e0a7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -291,8 +291,37 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G043_CANFD_RSTP_N>, + <&cpg R9A07G043_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { From e42faad1ef822e186c20e60576b198e1ac9866c4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:22 +0100 Subject: [PATCH 544/791] arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodes Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 24 +++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 60db9b02e0a7..d161600495aa 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -704,18 +704,36 @@ }; ostm0: timer@12801000 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; + resets = <&cpg R9A07G043_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm1: timer@12801400 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; + resets = <&cpg R9A07G043_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm2: timer@12801800 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; + resets = <&cpg R9A07G043_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; }; From a8352a5158ed032fa6c0d433fefc63285fdac8b0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:23 +0100 Subject: [PATCH 545/791] arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodes Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 24 ++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index d161600495aa..15335e9ca06b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -694,13 +694,33 @@ }; wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g043-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800800 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G043_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G043_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g043-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800400 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G043_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G043_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; ostm0: timer@12801000 { From 3237f21824165b41ef0bbdd3f784579c931b2a21 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 21 Apr 2022 23:19:33 +0200 Subject: [PATCH 546/791] ARM: dts: qcom: msm8974-FP2: We're msm8974pro Fairphone 2 always uses Snapdragon 801, a.k.a msm8974pro so change the include and filename to that. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421211936.345168-1-luca@z3ntu.xyz --- arch/arm/boot/dts/Makefile | 2 +- ...8974-fairphone-fp2.dts => qcom-msm8974pro-fairphone-fp2.dts} | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/boot/dts/{qcom-msm8974-fairphone-fp2.dts => qcom-msm8974pro-fairphone-fp2.dts} (99%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 56aa6fc4d3a4..b1e9ed1c8393 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1001,10 +1001,10 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8660-surf.dtb \ qcom-msm8916-samsung-serranove.dtb \ qcom-msm8960-cdp.dtb \ - qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ qcom-msm8974-sony-xperia-rhine-amami.dtb \ qcom-msm8974-sony-xperia-rhine-honami.dtb \ + qcom-msm8974pro-fairphone-fp2.dtb \ qcom-msm8974pro-samsung-klte.dtb \ qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts similarity index 99% rename from arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts rename to arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 2b9c5a87b014..1856d56085ec 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -1,4 +1,4 @@ -#include "qcom-msm8974.dtsi" +#include "qcom-msm8974pro.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" #include From 9c5537723429b82561087f8eb8179d065355443c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 21 Apr 2022 23:19:34 +0200 Subject: [PATCH 547/791] ARM: dts: qcom: msm8974-FP2: Add mmc* aliases Add aliases for internal storage and SD card so they don't randomly switch around. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421211936.345168-2-luca@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 1856d56085ec..2a1cdd006836 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -9,6 +9,8 @@ compatible = "fairphone,fp2", "qcom,msm8974"; aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; serial0 = &blsp1_uart2; }; From 3912e74c576a56920cde1d5591125cdd5560caae Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 21 Apr 2022 23:19:35 +0200 Subject: [PATCH 548/791] ARM: dts: qcom: msm8974: Add missing license headers All other msm8974 dts files are licensed as GPL-2.0 so add the same header to the files where it's missing. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421211936.345168-3-luca@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts | 1 + arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 1 + arch/arm/boot/dts/qcom-msm8974pro.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 2a1cdd006836..26fc2002e5c3 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 34aed41856a6..9bd8faea61a5 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi index 973bd1dafbfe..1e882e16a221 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974.dtsi" &gcc { From c024c46fe13bb9e9a70d044fd2d63dbee82bbb59 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 12 Apr 2022 13:20:08 +0530 Subject: [PATCH 549/791] arm64: dts: ti: k3-am62: Add SA3UL ranges in cbass_main Add the address space for SA3UL to the ranges property of the cbass_main node. Signed-off-by: Jayesh Choudhary Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220412075008.10553-1-j-choudhary@ti.com --- arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index bc2997b18556..37fcbe7a3c33 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -66,6 +66,7 @@ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ From 97fab2004d11577dfe17aaaacdbf02093194dbb9 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 27 Apr 2022 11:19:13 +0300 Subject: [PATCH 550/791] ARM: dts: am335x-myirtech: Add an external clock oscillator for CPU RTC The CPU RTC has an external crystal, so to keep time, let's define it for devicetree. Signed-off-by: Alexander Shiyan Message-Id: <20220427081914.6773-1-eagle.alexander923@gmail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-myirtech-myc.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index 245c35f41cdf..d94e096983c7 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -27,6 +27,13 @@ reg = <0x80000000 0x10000000>; }; + clk32k: clk32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + + #clock-cells = <0>; + }; + vdd_mod: vdd_mod_reg { compatible = "regulator-fixed"; regulator-name = "vdd-mod"; @@ -149,6 +156,8 @@ }; &rtc { + clocks = <&clk32k>; + clock-names = "ext-clk"; system-power-controller; }; From 165c79da163f9909aba8fad68b897148399a1ba5 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 27 Apr 2022 11:19:14 +0300 Subject: [PATCH 551/791] ARM: dts: am335x-myirtech: Update NAND default partition table layout This patch replaces the legacy partition table layout with a modern style. As an additional change, we are reserving space for three backup MLO entries and increasing space for the main bootloader. Signed-off-by: Alexander Shiyan Message-Id: <20220427081914.6773-2-eagle.alexander923@gmail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-myirtech-myc.dtsi | 3 --- arch/arm/boot/dts/am335x-myirtech-myd.dts | 20 +++++++++++++------- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index d94e096983c7..6eea18b29355 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -131,9 +131,6 @@ gpmc,wr-data-mux-bus-ns = <0>; ti,elm-id = <&elm>; ti,nand-ecc-opt = "bch8"; - - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts index 1479fd95dec2..9d81d4cc6890 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/am335x-myirtech-myd.dts @@ -227,14 +227,20 @@ }; &nand0 { - partition@0 { - label = "MLO"; - reg = <0x00000 0x20000>; - }; + nand_parts: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@20000 { - label = "boot"; - reg = <0x20000 0x80000>; + partition@0 { + label = "MLO"; + reg = <0x00000 0x20000>; + }; + + partition@80000 { + label = "boot"; + reg = <0x80000 0x100000>; + }; }; }; From b0fa698b834f0f8b4a0c9c5c086d88787f1124a0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:24 +0100 Subject: [PATCH 552/791] arm64: dts: renesas: rzg2ul-smarc: Enable i2c{0,1} and wm8978 Enable i2c{0,1} on RZ/G2UL SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable wm8978 audio codec. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a07g043u11-smarc.dts | 18 ------------------ .../dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 10 ++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 8 ++++++++ 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 08a0404c6f0b..2bf4a3b62438 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -38,24 +38,6 @@ status = "disabled"; }; -&i2c0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - &ohci0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index b515748e6a9a..94106095c66a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -12,6 +12,16 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 056a77369c8d..a580b04987ec 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -19,6 +19,14 @@ #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" +&i2c1 { + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + &vccq_sdhi1 { gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; }; From 820e976909c2b286d1ef259ea524979540475ba6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:28 +0100 Subject: [PATCH 553/791] arm64: dts: renesas: rzg2ul-smarc: Enable CANFD Enable CANFD on RZ/G2UL SMARC platform. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a07g043u11-smarc.dts | 6 ---- .../dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 28 +++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 8 ++++++ 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 2bf4a3b62438..df27b63f0465 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -14,12 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; }; -&canfd { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &ehci0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 94106095c66a..17527184ff2a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -12,6 +12,34 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; + can0_pins: can0 { + pinmux = , /* TX */ + ; /* RX */ + }; + +#if (SW_ET0_EN_N) + can0-stb-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "can0_stb"; + }; +#endif + + can1_pins: can1 { + pinmux = , /* TX */ + ; /* RX */ + }; + +#if (SW_ET0_EN_N) + can1-stb-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; +#endif + i2c0_pins: i2c0 { pins = "RIIC0_SDA", "RIIC0_SCL"; input-enable; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index a580b04987ec..d75ad79ba804 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -19,6 +19,14 @@ #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" +#if (!SW_ET0_EN_N) +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + &i2c1 { wm8978: codec@1a { compatible = "wlf,wm8978"; From 0b3e18dbcdf6ec80d22d76d4c8099968704f7cf9 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:29 +0100 Subject: [PATCH 554/791] arm64: dts: renesas: rzg2ul-smarc-som: Enable OSTM Enable OSTM{1, 2} interfaces on RZ/G2UL SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index b0822679a55b..4c4cd7f2f17b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -115,6 +115,14 @@ clock-frequency = <24000000>; }; +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { eth0_pins: eth0 { pinmux = , /* ET0_LINKSTA */ From 3f67af66e65baf88da482b6327c53c742b949d15 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:30 +0100 Subject: [PATCH 555/791] arm64: dts: renesas: rzg2ul-smarc-som: Enable watchdog Enable watchdog{0,2} interfaces on RZ/G2UL SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-14-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 4c4cd7f2f17b..a663115f5aae 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -239,3 +239,13 @@ status = "okay"; }; #endif + +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; From e2ab93e59bc3c029b61a7091825f193f1a66a1a1 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 26 Apr 2022 13:08:26 +0530 Subject: [PATCH 556/791] dt-bindings: memory: tegra: Update validation for reg and reg-names From Tegra186 onwards, memory controller support multiple channels. "reg" items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and Tegra234 have overall 17 memory controller channels each. There is one "reg" entry for memory controller stream-ID registers. So update the "reg" property's "minItems" and "maxItems" accordingly in the Tegra186 devicetree documentation. Also update validation for "reg-names" added for these corresponding "reg" items. ABI change due to new bindings is intended but backward compatibility is preserved in driver. Reviewed-by: Rob Herring Signed-off-by: Ashish Mhetre Signed-off-by: Thierry Reding --- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 13c4c82fd0d3..c7cfa6c2cd81 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6 + maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items: @@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties: @@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties: @@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-names - interrupts - "#address-cells" - "#size-cells" @@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = ; #address-cells = <2>; From 000b99e5ed1c9e33c14f3582474ae55cd739ae8d Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 26 Apr 2022 13:08:27 +0530 Subject: [PATCH 557/791] arm64: tegra: Add memory controller channels From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping. Signed-off-by: Ashish Mhetre Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 +++++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 +++++++++++++++++++++--- 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2e7faa1e0b9c..0e9afc3e2f26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -528,7 +528,13 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = ; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f9d343b24597..d1f8248c00f4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -612,9 +612,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = ; #interconnect-cells = <1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 71c21d7d0551..cb3af539e477 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -515,9 +515,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = ; #interconnect-cells = <1>; status = "okay"; From a2fe0f97fd4a5e482123fc207a48bde844b161a1 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Mon, 25 Apr 2022 19:45:09 +0100 Subject: [PATCH 558/791] arm64: dts: rockchip: Rename vdec_mmu node for RK3328 All other rockchip devices which have vdec nodes do not have an rk prefix. Remove the prefix from the (currently unused) rkvdec_mmu node for consistency with other devices. Signed-off-by: Christopher Obbard Reviewed-by: Ezequiel Garcia Link: https://lore.kernel.org/r/20220425184510.1138446-3-chris.obbard@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b822533dc7f1..f8ef149fedad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -660,7 +660,7 @@ power-domains = <&power RK3328_PD_VPU>; }; - rkvdec_mmu: iommu@ff360480 { + vdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; interrupts = ; From 17408c9b119de4edef9ea57ade7e97d4a1b8b632 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Mon, 25 Apr 2022 19:45:10 +0100 Subject: [PATCH 559/791] arm64: dts: rockchip: Add vdec support for RK3328 The RK3328 has an vdec device with dedicated iommu. Describe the vdec device, the required power-domains and enable the iommu in the devicetree. Signed-off-by: Christopher Obbard Link: https://lore.kernel.org/r/20220425184510.1138446-4-chris.obbard@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index f8ef149fedad..49ae15708a0b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -306,6 +306,10 @@ }; power-domain@RK3328_PD_VIDEO { reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; #power-domain-cells = <0>; }; power-domain@RK3328_PD_VPU { @@ -660,6 +664,20 @@ power-domains = <&power RK3328_PD_VPU>; }; + vdec: video-codec@ff360000 { + compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; + reg = <0x0 0xff360000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + }; + vdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; @@ -667,7 +685,7 @@ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3328_PD_VIDEO>; }; vop: vop@ff370000 { From ec48c3e82ca36a66ae37ba8b1fdb9a7561dcab14 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Mon, 28 Mar 2022 01:50:05 +0100 Subject: [PATCH 560/791] arm64: dts: rockchip: add an input enable pinconf to rk3399 Add a pinconf to configure pins as input-enable. Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20220328005005.72492-5-kc@postmarketos.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a90beec50f6a..8db8b2dba12d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -2211,6 +2211,22 @@ output-low; }; + pcfg_input_enable: pcfg-input-enable { + input-enable; + }; + + pcfg_input_pull_up: pcfg-input-pull-up { + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_input_pull_down: pcfg-input-pull-down { + input-enable; + bias-pull-down; + drive-strength = <2>; + }; + clock { clk_32k: clk-32k { rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; From 8d411bebd4538a9750db175c030d6083d5210d7c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 12 Apr 2022 22:56:13 -0500 Subject: [PATCH 561/791] arm64: dts: rockchip: Add accelerometer to rk3566-pinenote PineNote has an SC7A20 accelerometer connected via I2C. Enable it. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220413035614.31045-2-samuel@sholland.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3566-pinenote.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index fea748adfa90..adc0e7d39fb3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -468,6 +468,22 @@ }; }; +&i2c5 { + status = "okay"; + + accelerometer@18 { + compatible = "silan,sc7a20"; + reg = <0x18>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-0 = <&accelerometer_int_l>; + pinctrl-names = "default"; + st,drdy-int-pin = <1>; + vdd-supply = <&vcc_3v3>; + vddio-supply = <&vcc_3v3>; + }; +}; + &i2s1_8ch { pinctrl-0 = <&i2s1m0_lrcktx>, <&i2s1m0_sclktx>, <&i2s1m0_sdi0>, <&i2s1m0_sdo0>; rockchip,trcm-sync-tx-only; @@ -482,6 +498,12 @@ }; &pinctrl { + accelerometer { + accelerometer_int_l: accelerometer-int-l { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + audio-amplifier { spk_amp_enable_h: spk-amp-enable-h { rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; From 87a267b4af09477721e9d2bad63555f0dc49d08a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 12 Apr 2022 22:56:14 -0500 Subject: [PATCH 562/791] arm64: dts: rockchip: Add USB and TCPC to rk3566-pinenote PineNote has a USB Type-C port connected to the first USB 2.0 OTG PHY and XHCI controller via a Willsemi WUSB3801 Type-C port controller. Add support for it. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220413035614.31045-3-samuel@sholland.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3566-pinenote.dtsi | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index adc0e7d39fb3..e01668e6e5f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -466,6 +466,39 @@ default-brightness = <0>; }; }; + + wusb3801: tcpc@60 { + compatible = "willsemi,wusb3801"; + reg = <0x60>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&tcpc_int_l>; + pinctrl-names = "default"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + vbus-supply = <&otg_switch>; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + typec_hs_usb2phy0: endpoint { + remote-endpoint = <&usb2phy0_typec_hs>; + }; + }; + }; + }; + }; }; &i2c5 { @@ -572,6 +605,12 @@ }; }; + tcpc { + tcpc_int_l: tcpc-int-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + vcc-wl { vcc_wl_pin: vcc-wl-pin { rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -659,3 +698,22 @@ &uart2 { status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "otg"; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; + + port { + usb2phy0_typec_hs: endpoint { + remote-endpoint = <&typec_hs_usb2phy0>; + }; + }; +}; From 13e0ee34f39c01948a7bbaab0b3c225d9b00a5bb Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:49 -0400 Subject: [PATCH 563/791] arm64: dts: rockchip: add rk356x sfc support Add the sfc node to the rk356x device tree. This enables spi flash support for this soc. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-5-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 55e6dcb948cc..3f0e11af738d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -778,6 +778,17 @@ status = "disabled"; }; + sfc: spi@fe300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe300000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + sdhci: mmc@fe310000 { compatible = "rockchip,rk3568-dwcmshc"; reg = <0x0 0xfe310000 0x0 0x10000>; From 254a1f6a29e7a273adb1a1d032305ec58ef83a69 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Apr 2022 15:35:01 +0200 Subject: [PATCH 564/791] arm64: dts: rockchip: add usb3 support to the radxa rock3 model a The Radxa ROCK3 Model A features one USB 3.0 host port and one USB 3.0 OTG/DRD port. Enable them in the device tree. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220425133502.405512-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-rock-3a.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 53cf444ecb04..4169f8a85ecd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -96,6 +96,26 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_usb>; }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; }; &cpu0 { @@ -416,6 +436,9 @@ vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; @@ -479,6 +502,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; @@ -487,6 +515,24 @@ status = "okay"; }; +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + vbus-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + &usb2phy1 { status = "okay"; }; From 160f126b89e10bd58491e10067a44c7e3f85fa2c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Apr 2022 15:35:02 +0200 Subject: [PATCH 565/791] arm64: dts: rockchip: enable usb hub on the radxa rock3 model a One USB 2.0 host port on the Radxa ROCK3 Model A is connected to the SoC via a hub. Introduce a voltage regulator to enable this USB hub. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220425133502.405512-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 4169f8a85ecd..0813c0c5abde 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -97,6 +97,17 @@ vin-supply = <&vcc5v0_usb>; }; + vcc5v0_usb_hub: vcc5v0-usb-hub-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_hub_en>; + regulator-name = "vcc5v0_usb_hub"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -436,6 +447,9 @@ vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; From b30ae5638dac6c5e640c47f59707d5b1e2c493e2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:57 +0200 Subject: [PATCH 566/791] arm64: dts: juno: Drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Another reason is that the number of requests also does not seem right (should be 8). Link: https://lore.kernel.org/r/20220430121902.59895-5-krzysztof.kozlowski@linaro.org Reported-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 4f40a5c8f565..065381c1cbf5 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -829,8 +829,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x7ff00000 0 0x1000>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; interrupts = , , , From c37415f55bdadffe5b4c0e7981e9fc7e8b96beea Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:46 -0400 Subject: [PATCH 567/791] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B The Quartz64 Model B is a compact single board computer from Pine64 based on the rk3566 SoC. It outputs on uart2 for the debug console. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220429115252.2360496-2-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index efb0a9c4347b..6fa95ff92a98 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -502,9 +502,11 @@ properties: - const: pine64,rockpro64 - const: rockchip,rk3399 - - description: Pine64 Quartz64 Model A + - description: Pine64 Quartz64 Model A/B items: - - const: pine64,quartz64-a + - enum: + - pine64,quartz64-a + - pine64,quartz64-b - const: rockchip,rk3566 - description: Radxa Rock From c466828fb3ba8cb7f5c3bf28766da9b70bf9745e Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:47 -0400 Subject: [PATCH 568/791] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM The SoQuartz system on module is designed to be pin compatible with the RPi CM4 SoM. It is based on the rk3566 SoC and outputs on uart2 for debug and console. The first carrier board supported is the CM4IO board from RPi. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220429115252.2360496-3-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 6fa95ff92a98..ea8dcbc5106f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -509,6 +509,13 @@ properties: - pine64,quartz64-b - const: rockchip,rk3566 + - description: Pine64 SoQuartz SoM + items: + - enum: + - pine64,soquartz-cm4io + - const: pine64,soquartz + - const: rockchip,rk3566 + - description: Radxa Rock items: - const: radxa,rock From e52ded5543708e0382f236ce35372a63f4568341 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:48 -0400 Subject: [PATCH 569/791] dt-bindings: arm: rockchip: Add Firefly Station M2 The Station M2 is a compact single board computer based on the rk3566 SoC. It outputs on uart2 for debug and console purposes. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220429115252.2360496-4-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ea8dcbc5106f..cf9eb1e8326a 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -133,6 +133,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 + - description: Firefly Station M2 + items: + - const: firefly,rk3566-roc-pc + - const: rockchip,rk3566 + - description: FriendlyElec NanoPi R2S items: - const: friendlyarm,nanopi-r2s From dcc8c66bef79befa6c9ebe7d7d62b0ce66983c20 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:50 -0400 Subject: [PATCH 570/791] arm64: dts: rockchip: add Pine64 Quartz64-B device tree Add a device tree for the Pine64 Quartz64 Model B single board computer. This board ouputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 x2 (one port otg capable) USB3 PCIe/SATA M2 HDMI DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI Flash PI-40 compatible pin header Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-6-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++ 2 files changed, 616 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 99941e9dbba1..1093146d33ee 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts new file mode 100644 index 000000000000..7bdcecc0dfe4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 Quartz64-B Board"; + compatible = "pine64,quartz64-b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "user-led"; + default-state = "on"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + + vcc5v0_in: vcc5v0-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_in>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x24>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc_3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + }; + }; + }; +}; + +/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; +}; + +/* + * i2c4_m0 is exposed on PI40, pulled up to vcc_3v3 + * pin 27 - i2c4_sda_m0 + * pin 28 - i2c4_scl_m0 + */ +&i2c4 { + status = "okay"; +}; + +/* + * i2c5_m0 is exposed on PI40 + * pin 29 - i2c5_scl_m0 + * pin 31 - i2c5_sda_m0 + */ +&i2c5 { + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2_m0 is exposed on PI40 + * pin 8 - uart2_tx_m0 + * pin 10 - uart2_rx_m0 + */ +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; From 5859b5a9c3ac92d831bed164374cb837519524ad Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:51 -0400 Subject: [PATCH 571/791] arm64: dts: rockchip: add SoQuartz CM4IO dts This is the initial SoQuartz SoM device tree on a CM4IO carrier board. This board outputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 (OTG/Host shared) PCIe 2.0 x1 HDMI (HDMI Port 0) eDP (HDMI Port 1) DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI NOR Flash (Not placed) PI-40 compatible pin header Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-7-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 177 +++++ .../boot/dts/rockchip/rk3566-soquartz.dtsi | 616 ++++++++++++++++++ 3 files changed, 794 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1093146d33ee..107fab18cacd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts new file mode 100644 index 000000000000..e00568a6be5c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; + compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&sdmmc_pwr>; + status = "okay"; +}; + +&sdmmc_pwr { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc_5v>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc_5v>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi new file mode 100644 index 000000000000..5bcd4be32964 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz SOM"; + compatible = "pine64,soquartz", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led_diy: led-diy { + label = "diy-led"; + default-state = "on"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&diy_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + + led_work: led-work { + label = "work-led"; + default-state = "off"; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + vbus: vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* sourced from vbus, vbus is provided by the carrier board */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdmmc_pwr: sdmmc-pwr-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr_h>; + regulator-name = "sdmmc_pwr"; + status = "disabled"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + status = "disabled"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + }; + }; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "disabled"; +}; + +/* + * i2c2 is exposed on CM1 / Module1A + * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A + * pin 35 - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B + * pin 45 - i2c4_scl_m1 + * pin 47 - i2c4_sda_m1 + */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A + * pin 24 - i2s1_sdi1_m1 + * pin 25 - i2s1_sdo0_m1 + * pin 26 - i2s1_lrck_tx_m1 + * pin 27 - i2s1_sdi0_m1 + * pin 29 - i2s1_sdi3_m1 + * pin 30 - i2s1_sdi2_m1 + * pin 40 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - i2s1_sdo2_m1 + * pin 49 - i2s1_sclk_tx_m1 + * pin 50 - i2s1_mclk_m1 + * pin 56 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx + &i2s1m1_lrcktx &i2s1m1_lrckrx + &i2s1m1_sdi0 &i2s1m1_sdi1 + &i2s1m1_sdi2 &i2s1m1_sdi3 + &i2s1m1_sdo0 &i2s1m1_sdo1 + &i2s1m1_sdo2 &i2s1m1_sdo3>; + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + status = "disabled"; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc-pwr { + sdmmc_pwr_h: sdmmc-pwr-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A + * pin 94 - saradc_vin3 + * pin 96 - saradc_vin2 + */ +&saradc { + vref-supply = <&vcca_1v8>; + status = "disabled"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vqmmc-supply = <&vccio_sd>; + status = "disabled"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A + * pin 37 - spi3_cs1_m0 + * pin 38 - spi3_clk_m0 + * pin 39 - spi3_cs0_m0 + * pin 40 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2 is exposed on CM1 / Module1A + * pin 51 - uart2_rx_m0 + * pin 55 - uart2_tx_m0 + */ +&uart2 { + status = "disabled"; +}; + +/* + * uart7 is exposed on CM1 / Module1A + * pin 46 - uart7_tx_m2 + * pin 47 - uart7_rx_m2 + */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +/* dwc3_otg is the only usb port available */ +&usb2phy0 { + status = "disabled"; +}; + +&usb2phy0_otg { + status = "disabled"; +}; + +&usb_host0_xhci { + status = "disabled"; +}; From 30ac9b4e25d8cece00d32c7419f9d919f55421fe Mon Sep 17 00:00:00 2001 From: Furkan Kardame Date: Fri, 29 Apr 2022 07:52:52 -0400 Subject: [PATCH 572/791] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566 Add dts for Firefly Station M2. Working IO: * UART * LED * LAN * Wifi * SD Card * eMMC * USB2 Signed-off-by: Furkan Kardame Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-8-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 579 ++++++++++++++++++ 2 files changed, 580 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 107fab18cacd..18d00eae3072 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts new file mode 100644 index 000000000000..57759b66d44d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Firefly Station M2"; + compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566"; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "user-led"; + default-state = "on"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + usb_5v: usb-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&usb_5v>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x24>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcca1v8_pmu>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; From bb419dc67bb51d15740df5a775da1de057e4b2fb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Apr 2022 16:04:35 +0200 Subject: [PATCH 573/791] dt-bindings: arm: stm32: narrow DH STM32MP1 SoM boards The bindings for DH STM32MP1 SoM boards allows invalid combinations, e.g. st,stm32mp153 SoC on a dh,stm32mp157c-dhcom-som SoM. Split the enums to properly match valid setups. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/arm/stm32/stm32.yaml | 37 +++++++++++-------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index fa0a1b84122e..2f83f2760e6a 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -14,21 +14,6 @@ properties: const: "/" compatible: oneOf: - - description: DH STM32MP1 SoM based Boards - items: - - enum: - - arrow,stm32mp157a-avenger96 # Avenger96 - - dh,stm32mp153c-dhcom-drc02 - - dh,stm32mp157c-dhcom-pdk2 - - dh,stm32mp157c-dhcom-picoitx - - enum: - - dh,stm32mp153c-dhcom-som - - dh,stm32mp157a-dhcor-som - - dh,stm32mp157c-dhcom-som - - enum: - - st,stm32mp153 - - st,stm32mp157 - - description: emtrion STM32MP1 Argon based Boards items: - const: emtrion,stm32mp157c-emsbc-argon @@ -65,6 +50,13 @@ properties: - enum: - st,stm32mp135f-dk - const: st,stm32mp135 + + - description: DH STM32MP153 SoM based Boards + items: + - const: dh,stm32mp153c-dhcom-drc02 + - const: dh,stm32mp153c-dhcom-som + - const: st,stm32mp153 + - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box @@ -79,6 +71,21 @@ properties: - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - const: dh,stm32mp157a-dhcor-som + - const: st,stm32mp157 + + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - dh,stm32mp157c-dhcom-pdk2 + - dh,stm32mp157c-dhcom-picoitx + - const: dh,stm32mp157c-dhcom-som + - const: st,stm32mp157 + - description: Engicam i.Core STM32MP1 SoM based Boards items: - enum: From 5d68f9798d7da8a1004d3d09e56dc7b379700016 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Apr 2022 16:04:36 +0200 Subject: [PATCH 574/791] dt-bindings: arm: stm32: correct blank lines Correct blank lines to precesily separate entries. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 2f83f2760e6a..80b29f6903f0 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -64,8 +64,8 @@ properties: - st,stm32mp157c-ed1 - st,stm32mp157a-dk1 - st,stm32mp157c-dk2 - - const: st,stm32mp157 + - items: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 @@ -110,6 +110,7 @@ properties: - const: oct,stm32mp15xx-osd32 - enum: - st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards items: - enum: From c70bb467fb211fadd2c1360892a498330d8a94a6 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:08 +0200 Subject: [PATCH 575/791] dt-bindings: arm: stm32: Add compatible strings for Protonic T1L boards This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 80b29f6903f0..a93c60241f28 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -51,6 +51,14 @@ properties: - st,stm32mp135f-dk - const: st,stm32mp135 + - description: ST STM32MP151 based Boards + items: + - enum: + - prt,prtt1a # Protonic PRTT1A + - prt,prtt1c # Protonic PRTT1C + - prt,prtt1s # Protonic PRTT1S + - const: st,stm32mp151 + - description: DH STM32MP153 SoM based Boards items: - const: dh,stm32mp153c-dhcom-drc02 From 94de07e5565be51d91dd91dcae6ede54c0f9be27 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:09 +0200 Subject: [PATCH 576/791] dt-bindings: net: silabs,wfx: add prt,prtt1c-wfm200 antenna variant Add compatible for wfm200 antenna configuration variant for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/staging/net/wireless/silabs,wfx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml index 105725a127ab..ce107fe45d7c 100644 --- a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml @@ -39,6 +39,7 @@ properties: compatible: items: - enum: + - prt,prtt1c-wfm200 # Protonic PRTT1C Board - silabs,brd4001a # WGM160P Evaluation Board - silabs,brd8022a # WF200 Evaluation Board - silabs,brd8023a # WFM200 Evaluation Board From 9ad65d245b7b918353d4b1279e7d3190a0e087fd Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:10 +0200 Subject: [PATCH 577/791] ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group Add spi1-1 pingroup as preparation for Protonic PRTT1C board. Signed-off-by: Oleksij Rempel Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 3c44a04c13fb..6052243ad81c 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2261,4 +2261,19 @@ bias-disable; }; }; + + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; }; From 1a43e9b281c6eaadf788c3bfff3062860ced8e87 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 26 Apr 2022 09:35:11 +0200 Subject: [PATCH 578/791] ARM: dts: stm32: add support for Protonic PRTT1x boards This boards are based on STM32MP151AAD3 and use 10BaseT1L for communication. - PRTT1C - 10BaseT1L switch - PRTT1S - 10BaseT1L CO2 sensor board - PRTT1A - 10BaseT1L multi functional controller Signed-off-by: Oleksij Rempel Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/stm32mp151a-prtt1a.dts | 52 ++++ arch/arm/boot/dts/stm32mp151a-prtt1c.dts | 304 ++++++++++++++++++++++ arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi | 229 ++++++++++++++++ arch/arm/boot/dts/stm32mp151a-prtt1s.dts | 63 +++++ 5 files changed, 651 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1a.dts create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1c.dts create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi create mode 100644 arch/arm/boot/dts/stm32mp151a-prtt1s.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..2585ba8e1293 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1156,6 +1156,9 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ stm32mp135f-dk.dtb \ + stm32mp151a-prtt1a.dtb \ + stm32mp151a-prtt1c.dtb \ + stm32mp151a-prtt1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts new file mode 100644 index 000000000000..75874eafde11 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1A"; + compatible = "prt,prtt1a", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; + +&pwm5_pins_a { + pins { + pinmux = ; /* TIM5_CH1 */ + }; +}; + +&pwm5_sleep_pins_a { + pins { + pinmux = ; /* TIM5_CH1 */ + }; +}; + +&timers5 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts new file mode 100644 index 000000000000..7ecf31263abc --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1C"; + compatible = "prt,prtt1c", "st,stm32mp151"; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + }; +}; + +ðernet0 { + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "", + "", "", "", "", "", "", "", "SPI1_nSS"; +}; + +&gpiod { + gpio-line-names = + "", "", "", "", "", "", "", "", + "WFM_RESET", "", "", "", "", "", "", ""; +}; + +&gpioe { + gpio-line-names = + "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "", + "", "", "", "", "WFM_nIRQ", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "PHY3_nINT", + "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET", + "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", ""; +}; + +&mdio0 { + /* All this DP83TD510E PHYs can't be probed before switch@0 is + * probed so we need to use compatible with PHYid + */ + /* TI DP83TD510E */ + t1l0_phy: ethernet-phy@6 { + compatible = "ethernet-phy-id2000.0181"; + reg = <6>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l1_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.0181"; + reg = <7>; + interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l2_phy: ethernet-phy@10 { + compatible = "ethernet-phy-id2000.0181"; + reg = <10>; + interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* Micrel KSZ9031 */ + rj45_phy: ethernet-phy@2 { + reg = <2>; + interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; +}; + +&qspi { + status = "disabled"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc2_b4_od_pins_a { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + }; +}; + +&sdmmc2_b4_pins_a { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_b4_sleep_pins_a { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_d47_pins_a { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; +}; + +&sdmmc2_d47_sleep_pins_a { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + non-removable; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmc@1 { + compatible = "prt,prtt1c-wfm200", "silabs,wf200"; + reg = <1>; + }; +}; + +&sdmmc3_b4_od_pins_b { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + }; +}; + +&sdmmc3_b4_pins_b { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + }; +}; + +&sdmmc3_b4_sleep_pins_b { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins_b>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "t1l0"; + phy-mode = "rmii"; + phy-handle = <&t1l0_phy>; + }; + + port@1 { + reg = <1>; + label = "t1l1"; + phy-mode = "rmii"; + phy-handle = <&t1l1_phy>; + }; + + port@2 { + reg = <2>; + label = "t1l2"; + phy-mode = "rmii"; + phy-handle = <&t1l2_phy>; + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rj45_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <ðernet0>; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi new file mode 100644 index 000000000000..d865ab5d866b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxad-pinctrl.dtsi" +#include +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + mdio-gpio0 = &mdio0; + serial0 = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + status = "okay"; +}; + +ðernet0_rmii_pins_a { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + ; /* ETH1_RMII_TX_EN */ + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK input */ + ; /* ETH1_RMII_CRS_DV */ + }; +}; + +ðernet0_rmii_sleep_pins_a { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; +}; + +&iwdg2 { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <104000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&qspi_bk1_pins_a { + pins1 { + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_od_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&sdmmc1_b4_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart4_idle_pins_a { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_pins_a { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_sleep_pins_a { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <®_3v3>; +}; + +&usbphyc_port1 { + phy-supply = <®_3v3>; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts new file mode 100644 index 000000000000..ad25929e64e6 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1S"; + compatible = "prt,prtt1s", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + humidity-sensor@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + }; +}; + +&i2c1_pins_a { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; +}; + +&i2c1_sleep_pins_a { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; From e348101bbaed4a0263ccc37e9b6c68f686465588 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Sun, 1 May 2022 19:15:07 -0700 Subject: [PATCH 579/791] ARM: dts: am437x-gp-evm: Enable wkup_m3 control of IO isolation With this flag wkup_m3 is able to control IO isolation during suspend on the board. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Drew Fustini Message-Id: <20220502021508.1342869-2-dfustini@baylibre.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 4416ddb559e4..91b67b428a06 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1127,6 +1127,10 @@ cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + ti,set-io-isolation; +}; + &pruss1_mdio { status = "disabled"; }; From d480ecc9752d2b5a46f6f590e5853337bf4754f6 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Sun, 1 May 2022 19:15:08 -0700 Subject: [PATCH 580/791] ARM: dts: am33xx: Add i2c voltage scaling firmware to wkup_m3_ipc Add appropriate firmware-name property for all am33xx platforms. Signed-off-by: Dave Gerlach [dfustini: change property from 'ti,scale-data-fw' to 'firmware-name'] Signed-off-by: Drew Fustini Message-Id: <20220502021508.1342869-3-dfustini@baylibre.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++++ arch/arm/boot/dts/am335x-evm.dts | 4 ++++ arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 56ae5095a5b8..02e04a12a270 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -405,3 +405,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-bone-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 659e99eabe66..b9745a2f0e4d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -782,3 +782,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index a2db65538e51..9c458e5a95b7 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -719,3 +719,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; From 392ab2e2af060962ee1e37a5e2aa358f878a8f77 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Sun, 1 May 2022 19:15:09 -0700 Subject: [PATCH 581/791] ARM: dts: am43xx: Add i2c voltage scaling firmware to wkup_m3_ipc Add appropriate firmware-name property for all am43xx platforms. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy [dfustini: change property from 'ti,scale-data-fw' to 'firmware-name'] Signed-off-by: Drew Fustini Message-Id: <20220502021508.1342869-4-dfustini@baylibre.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 1 + arch/arm/boot/dts/am437x-sk-evm.dts | 4 ++++ arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 91b67b428a06..46d5361fe876 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1129,6 +1129,7 @@ &wkup_m3_ipc { ti,set-io-isolation; + firmware-name = "am43x-evm-scale-data.bin"; }; &pruss1_mdio { diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 20a34d2d85df..e5a825a525f9 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -893,6 +893,10 @@ }; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 4f9a7251a107..50c33418703a 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -1019,6 +1019,10 @@ cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; From 24a3db53ec9cac80b71e14b3c489b98e7537cdae Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 582/791] ARM: dts: Group omap3 CONTROL_DEVCONF0 clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 36 ++++++++++++++++---------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 0656c32439d2..b40832103dd6 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -92,12 +92,28 @@ clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; }; - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x04>; + /* CONTROL_DEVCONF0 */ + clock@4 { + compatible = "ti,clksel"; + reg = <0x4>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp1_mux_fck: clock-mcbsp1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp1_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + + mcbsp2_mux_fck: clock-mcbsp2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp2_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + }; }; mcbsp1_fck: mcbsp1_fck { @@ -106,14 +122,6 @@ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; }; - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x04>; - }; - mcbsp2_fck: mcbsp2_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 1e7079d32e6ae9ec8caae2a4e7d9696b97307b7a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 583/791] ARM: dts: Group omap3 CONTROL_DEVCONF1 clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 48 +++++++++++++++----------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index b40832103dd6..7518fd57f9dc 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -78,12 +78,35 @@ }; &scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; + /* CONTROL_DEVCONF1 */ + clock@68 { + compatible = "ti,clksel"; reg = <0x68>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp5_mux_fck: clock-mcbsp5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp5_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + }; + + mcbsp3_mux_fck: clock-mcbsp3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp3_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + }; + + mcbsp4_mux_fck: clock-mcbsp4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp4_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; }; mcbsp5_fck: mcbsp5_fck { @@ -128,27 +151,12 @@ clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; }; - mcbsp3_mux_fck: mcbsp3_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x68>; - }; - mcbsp3_fck: mcbsp3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; }; - mcbsp4_mux_fck: mcbsp4_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x68>; - }; - mcbsp4_fck: mcbsp4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 3408a95f213e71fae8a9530872ecd2a77be78926 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 584/791] ARM: dts: Group omap3 CM_FCLKEN1_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am35xx-clocks.dtsi | 19 +- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 47 ++-- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 35 ++- ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 19 +- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 19 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 260 +++++++++--------- 6 files changed, 221 insertions(+), 178 deletions(-) diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index 220d0a52797e..93a12ddf4b7e 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -90,12 +90,19 @@ ti,bit-shift = <23>; }; - uart4_fck_am35xx: uart4_fck_am35xx@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck_am35xx: clock-uart4-fck-am35xx { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck_am35xx"; + clocks = <&core_48m_fck>; + ti,bit-shift = <23>; + }; }; }; diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 2ec3628d3315..6509ae0b036c 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -46,28 +46,35 @@ ti,bit-shift = <2>; }; - d2d_26m_fck: d2d_26m_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <3>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; - fshostusb_fck: fshostusb_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <5>; - }; + d2d_26m_fck: clock-d2d-26m-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "d2d_26m_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; + fshostusb_fck: clock-fshostusb-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "fshostusb_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <5>; + }; + + ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; }; ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 21079cdf2663..37556b464f79 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -187,14 +187,28 @@ ti,bit-shift = <0>; }; - modem_fck: modem_fck@a00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <31>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + modem_fck: clock-modem-fck { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "modem_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <31>; + }; + + mspro_fck: clock-mspro-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mspro_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <23>; + }; + }; sad2d_ick: sad2d_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; @@ -211,13 +225,6 @@ ti,bit-shift = <3>; }; - mspro_fck: mspro_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; }; &cm_clockdomains { diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 9974d5226971..d698b05b742d 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -149,12 +149,19 @@ ti,bit-shift = <30>; }; - mmchs3_fck: mmchs3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <30>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_fck: clock-mmchs3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <30>; + }; }; dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 945537aee3ca..247236326da5 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -5,12 +5,19 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; }; ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 7518fd57f9dc..20b855959f1a 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -603,12 +603,140 @@ ti,index-starts-at-one; }; - gpt10_gate_fck: gpt10_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <11>; - reg = <0x0a00>; + /* CM_FCLKEN1_CORE */ + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt10_gate_fck: clock-gpt10-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt10_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <11>; + }; + + gpt11_gate_fck: clock-gpt11-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt11_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <12>; + }; + + mmchs2_fck: clock-mmchs2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <25>; + }; + + mmchs1_fck: clock-mmchs1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <24>; + }; + + i2c3_fck: clock-i2c3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <17>; + }; + + i2c2_fck: clock-i2c2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <16>; + }; + + i2c1_fck: clock-i2c1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <15>; + }; + + mcbsp5_gate_fck: clock-mcbsp5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp5_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <10>; + }; + + mcbsp1_gate_fck: clock-mcbsp1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp1_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <9>; + }; + + mcspi4_fck: clock-mcspi4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi4_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <21>; + }; + + mcspi3_fck: clock-mcspi3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi3_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <20>; + }; + + mcspi2_fck: clock-mcspi2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <19>; + }; + + mcspi1_fck: clock-mcspi1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <18>; + }; + + uart2_fck: clock-uart2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <14>; + }; + + uart1_fck: clock-uart1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <13>; + }; + + hdq_fck: clock-hdq-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "hdq_fck"; + clocks = <&core_12m_fck>; + ti,bit-shift = <22>; + }; }; gpt10_mux_fck: gpt10_mux_fck@a40 { @@ -625,14 +753,6 @@ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_gate_fck: gpt11_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <12>; - reg = <0x0a00>; - }; - gpt11_mux_fck: gpt11_mux_fck@a40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -655,62 +775,6 @@ clock-div = <1>; }; - mmchs2_fck: mmchs2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <25>; - }; - - mmchs1_fck: mmchs1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <24>; - }; - - i2c3_fck: i2c3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <17>; - }; - - i2c2_fck: i2c2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <16>; - }; - - i2c1_fck: i2c1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <15>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; - reg = <0x0a00>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; - reg = <0x0a00>; - }; - core_48m_fck: core_48m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -719,54 +783,6 @@ clock-div = <1>; }; - mcspi4_fck: mcspi4_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <21>; - }; - - mcspi3_fck: mcspi3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <20>; - }; - - mcspi2_fck: mcspi2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <19>; - }; - - mcspi1_fck: mcspi1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <18>; - }; - - uart2_fck: uart2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <14>; - }; - - uart1_fck: uart1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <13>; - }; - core_12m_fck: core_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -775,14 +791,6 @@ clock-div = <1>; }; - hdq_fck: hdq_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_12m_fck>; - reg = <0x0a00>; - ti,bit-shift = <22>; - }; - core_l3_ick: core_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; From aeb4dcf2c2bf0f8b0ae354ea37cf55fd0e17de65 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 585/791] ARM: dts: Group omap3 crypto accelerator clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 77 ++++++++++--------- 1 file changed, 42 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 37556b464f79..518eb7d60bcf 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -13,36 +13,51 @@ clock-div = <1>; }; - aes1_ick: aes1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; - reg = <0x0a14>; - }; + clock@a14 { + compatible = "ti,clksel"; + reg = <0xa14>; + #clock-cells = <2>; + #address-cells = <0>; - rng_ick: rng_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <2>; - }; + aes1_ick: clock-aes1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <3>; + }; - sha11_ick: sha11_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <1>; - }; + rng_ick: clock-rng-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "rng_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <2>; + }; - des1_ick: des1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <0>; + sha11_ick: clock-sha11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha11_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <1>; + }; + + des1_ick: clock-des1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <0>; + }; + + pka_ick: clock-pka-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "pka_ick"; + clocks = <&security_l3_ick>; + ti,bit-shift = <4>; + }; }; cam_mclk: cam_mclk@f00 { @@ -78,14 +93,6 @@ clock-div = <1>; }; - pka_ick: pka_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l3_ick>; - reg = <0x0a14>; - ti,bit-shift = <4>; - }; - icr_ick: icr_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; From eea4b03528410bc893b031860885e25e4f856bf3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 586/791] ARM: dts: Group omap3 CM_ICLKEN1_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am35xx-clocks.dtsi | 35 +- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 65 ++-- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 77 +++-- ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 19 +- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 35 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 324 +++++++++--------- 6 files changed, 299 insertions(+), 256 deletions(-) diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index 93a12ddf4b7e..0ee7afaa0e8e 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -62,12 +62,27 @@ }; }; &cm_clocks { - ipss_ick: ipss_ick@a10 { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + ipss_ick: clock-ipss-ick { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clock-output-names = "ipss_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + uart4_ick_am35xx: clock-uart4-ick-am35xx { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick_am35xx"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; }; rmii_ck: rmii_ck { @@ -82,14 +97,6 @@ clock-frequency = <27000000>; }; - uart4_ick_am35xx: uart4_ick_am35xx@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; - clock@a00 { compatible = "ti,clksel"; reg = <0xa00>; diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 6509ae0b036c..984e1385723e 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -100,20 +100,43 @@ clock-div = <2>; }; - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; - fac_ick: fac_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <8>; + hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es1"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + fac_ick: clock-fac-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "fac_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <8>; + }; + + ssi_ick: clock-ssi-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "ssi_ick_3430es1"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; + + usb_l4_gate_ick: clock-usb-l4-gate-ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clock-output-names = "usb_l4_gate_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -124,22 +147,6 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@a10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - reg = <0x0a10>; - }; - usb_l4_div_ick: usb_l4_div_ick@a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 518eb7d60bcf..eca6b2513f41 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -93,36 +93,51 @@ clock-div = <1>; }; - icr_ick: icr_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <29>; - }; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; - des2_ick: des2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <26>; - }; + icr_ick: clock-icr-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "icr_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <29>; + }; - mspro_ick: mspro_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; + des2_ick: clock-des2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <26>; + }; - mailboxes_ick: mailboxes_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <7>; + mspro_ick: clock-mspro-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mspro_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; + + mailboxes_ick: clock-mailboxes-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mailboxes_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <7>; + }; + + sad2d_ick: clock-sad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -216,14 +231,6 @@ ti,bit-shift = <23>; }; }; - sad2d_ick: sad2d_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <3>; - }; - mad2d_ick: mad2d_ick@a18 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index d698b05b742d..f8583bb66796 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -141,12 +141,19 @@ ti,bit-shift = <2>; }; - mmchs3_ick: mmchs3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <30>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_ick: clock-mmchs3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <30>; + }; }; clock@a00 { diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 247236326da5..c74566ff1f22 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -43,12 +43,27 @@ clock-div = <2>; }; - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-hsotgusb-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-hsotgusb-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es2"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + ssi_ick: clock-ssi-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clock-output-names = "ssi_ick_3430es2"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -59,14 +74,6 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - usim_gate_fck: usim_gate_fck@c00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 20b855959f1a..60e603127a0c 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -799,12 +799,172 @@ clock-div = <1>; }; - sdrc_ick: sdrc_ick@a10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <1>; + /* CM_ICLKEN1_CORE */ + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + sdrc_ick: clock-sdrc-ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sdrc_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <1>; + }; + + mmchs2_ick: clock-mmchs2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <25>; + }; + + mmchs1_ick: clock-mmchs1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <24>; + }; + + hdq_ick: clock-hdq-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "hdq_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <22>; + }; + + mcspi4_ick: clock-mcspi4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi4_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <21>; + }; + + mcspi3_ick: clock-mcspi3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <20>; + }; + + mcspi2_ick: clock-mcspi2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <19>; + }; + + mcspi1_ick: clock-mcspi1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <18>; + }; + + i2c3_ick: clock-i2c3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <17>; + }; + + i2c2_ick: clock-i2c2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <16>; + }; + + i2c1_ick: clock-i2c1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <15>; + }; + + uart2_ick: clock-uart2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <14>; + }; + + uart1_ick: clock-uart1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <13>; + }; + + gpt11_ick: clock-gpt11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt11_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <12>; + }; + + gpt10_ick: clock-gpt10-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt10_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <11>; + }; + + mcbsp5_ick: clock-mcbsp5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp5_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <10>; + }; + + mcbsp1_ick: clock-mcbsp1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <9>; + }; + + omapctrl_ick: clock-omapctrl-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omapctrl_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <6>; + }; + + aes2_ick: clock-aes2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <28>; + }; + + sha12_ick: clock-sha12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha12_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <27>; + }; }; gpmc_fck: gpmc_fck { @@ -823,142 +983,6 @@ clock-div = <1>; }; - mmchs2_ick: mmchs2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <25>; - }; - - mmchs1_ick: mmchs1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <24>; - }; - - hdq_ick: hdq_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <22>; - }; - - mcspi4_ick: mcspi4_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <21>; - }; - - mcspi3_ick: mcspi3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <20>; - }; - - mcspi2_ick: mcspi2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <19>; - }; - - mcspi1_ick: mcspi1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <18>; - }; - - i2c3_ick: i2c3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <17>; - }; - - i2c2_ick: i2c2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <16>; - }; - - i2c1_ick: i2c1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <15>; - }; - - uart2_ick: uart2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <14>; - }; - - uart1_ick: uart1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <13>; - }; - - gpt11_ick: gpt11_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <12>; - }; - - gpt10_ick: gpt10_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <11>; - }; - - mcbsp5_ick: mcbsp5_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <10>; - }; - - mcbsp1_ick: mcbsp1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <9>; - }; - - omapctrl_ick: omapctrl_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <6>; - }; - dss_tv_fck: dss_tv_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -1010,14 +1034,6 @@ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; }; - aes2_ick: aes2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - ti,bit-shift = <28>; - reg = <0x0a10>; - }; - wkup_32k_fck: wkup_32k_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1034,14 +1050,6 @@ ti,bit-shift = <3>; }; - sha12_ick: sha12_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <27>; - }; - wdt2_fck: wdt2_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; From 4e28ab96e311e4cf07f064f3bbe78e92ef013b15 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 587/791] ARM: dts: Group omap3 CM_ICLKEN3_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 21 +++++++++++++------ ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 20 ++++++++++++------ 2 files changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index eca6b2513f41..b6316be894ce 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -231,12 +231,21 @@ ti,bit-shift = <23>; }; }; - mad2d_ick: mad2d_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a18>; - ti,bit-shift = <3>; + + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + mad2d_ick: clock-mad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index f8583bb66796..1c41530cc16a 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -133,12 +133,20 @@ ti,bit-shift = <2>; }; - usbtll_ick: usbtll_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a18>; - ti,bit-shift = <2>; + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + usbtll_ick: clock-usbtll-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usbtll_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <2>; + }; }; clock@a10 { From b0985e02787759d99a8e921215b6dee0a2980c8c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 588/791] ARM: dts: Group omap3 CM_CLKSEL_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 41 ++++++----- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 21 ++++-- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 72 ++++++++++--------- 3 files changed, 78 insertions(+), 56 deletions(-) diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 984e1385723e..7dbab6eb2e6d 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -77,13 +77,30 @@ }; }; - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + usb_l4_div_ick: clock-usb-l4-div-ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "usb_l4_div_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + ti,index-starts-at-one; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es1 { @@ -147,16 +164,6 @@ clock-div = <1>; }; - usb_l4_div_ick: usb_l4_div_ick@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - usb_l4_ick: usb_l4_ick { #clock-cells = <0>; compatible = "ti,composite-clock"; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index c74566ff1f22..c6ab51a36f39 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -20,13 +20,20 @@ }; }; - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es2 { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 60e603127a0c..430dca208dc8 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -574,23 +574,47 @@ clock-div = <1>; }; - l3_ick: l3_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; + /* CM_CLKSEL_CORE */ + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; - l4_ick: l4_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,bit-shift = <2>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; + l3_ick: clock-l3-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_ick"; + clocks = <&core_ck>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + l4_ick: clock-l4-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l4_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <2>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt10_mux_fck: clock-gpt10-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt10_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt11_mux_fck: clock-gpt11-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt11_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; }; rm_ick: rm_ick@c40 { @@ -739,28 +763,12 @@ }; }; - gpt10_mux_fck: gpt10_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0a40>; - }; - gpt10_fck: gpt10_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_mux_fck: gpt11_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x0a40>; - }; - gpt11_fck: gpt11_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 05891b43bee70e026bcf11028936cabd3cc1eb08 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 589/791] ARM: dts: Group omap3 CM_FCLKEN_WKUP clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 33 +++++++----- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 19 ++++--- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 52 +++++++++++-------- 3 files changed, 63 insertions(+), 41 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index b6316be894ce..edc28654d158 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -148,20 +148,27 @@ clock-div = <1>; }; - sr1_fck: sr1_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <6>; - }; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; - sr2_fck: sr2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <7>; + sr1_fck: clock-sr1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr1_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + sr2_fck: clock-sr2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr2_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; }; sr_l4_ick: sr_l4_ick { diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index c6ab51a36f39..7c25739d5612 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -81,12 +81,19 @@ clock-div = <1>; }; - usim_gate_fck: usim_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; - reg = <0x0c00>; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_gate_fck: clock-usim-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "usim_gate_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <9>; + }; }; sys_d2_ck: sys_d2_ck { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 430dca208dc8..2cb77eb15eae 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1021,12 +1021,36 @@ clock-frequency = <0>; }; - gpt1_gate_fck: gpt1_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0c00>; + /* CM_FCLKEN_WKUP */ + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt1_gate_fck: clock-gpt1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt1_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + }; + + gpio1_dbck: clock-gpio1-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio1_dbck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <3>; + }; + + wdt2_fck: clock-wdt2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt2_fck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <5>; + }; }; gpt1_mux_fck: gpt1_mux_fck@c40 { @@ -1050,22 +1074,6 @@ clock-div = <1>; }; - gpio1_dbck: gpio1_dbck@c00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <3>; - }; - - wdt2_fck: wdt2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <5>; - }; - wdt2_ick: wdt2_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; From 23347c90e2329b88fab5b8fad6bfe94471ca1514 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 590/791] ARM: dts: Group omap3 CM_ICLKEN_WKUP clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 19 ++-- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 90 ++++++++++--------- 2 files changed, 62 insertions(+), 47 deletions(-) diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 7c25739d5612..b177eebcbae6 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -183,12 +183,19 @@ clocks = <&usim_gate_fck>, <&usim_mux_fck>; }; - usim_ick: usim_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <9>; + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_ick: clock-usim-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usim_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <9>; + }; }; }; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 2cb77eb15eae..5d8fff6d37fb 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1074,52 +1074,60 @@ clock-div = <1>; }; - wdt2_ick: wdt2_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <5>; - }; + /* CM_ICLKEN_WKUP */ + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; - wdt1_ick: wdt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <4>; - }; + wdt2_ick: clock-wdt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt2_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <5>; + }; - gpio1_ick: gpio1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <3>; - }; + wdt1_ick: clock-wdt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <4>; + }; - omap_32ksync_ick: omap_32ksync_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <2>; - }; + gpio1_ick: clock-gpio1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <3>; + }; - gpt12_ick: gpt12_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <1>; - }; + omap_32ksync_ick: clock-omap-32ksync-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omap_32ksync_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <2>; + }; - gpt1_ick: gpt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <0>; + gpt12_ick: clock-gpt12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt12_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <1>; + }; + + gpt1_ick: clock-gpt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <0>; + }; }; per_96m_fck: per_96m_fck { From 2f7c426df6f63447a65af770a07539051bc8c868 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 591/791] ARM: dts: Group omap3 CM_CLKSEL_WKUP clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 21 ++++++---- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 38 +++++++++++-------- 2 files changed, 37 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index b177eebcbae6..c94eb86d3da7 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -168,13 +168,20 @@ clock-div = <20>; }; - usim_mux_fck: usim_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_mux_fck: clock-usim-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "usim_mux_fck"; + clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; + ti,bit-shift = <3>; + ti,index-starts-at-one; + }; }; usim_fck: usim_fck { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 5d8fff6d37fb..80e63f185427 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -617,14 +617,29 @@ }; }; - rm_ick: rm_ick@c40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <1>; - ti,max-div = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; + /* CM_CLKSEL_WKUP */ + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + rm_ick: clock-rm-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "rm_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <1>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt1_mux_fck: clock-gpt1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt1_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; }; /* CM_FCLKEN1_CORE */ @@ -1053,13 +1068,6 @@ }; }; - gpt1_mux_fck: gpt1_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x0c40>; - }; - gpt1_fck: gpt1_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 173e215b7f8632c62db2dc713e51a998038bb8ac Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 592/791] ARM: dts: Group omap3 CM_CLKSEL1_PLL clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 72 ++++++++++++++------------ 1 file changed, 40 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 80e63f185427..d101f0a40502 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -301,16 +301,6 @@ clock-frequency = <0x0>; }; - dpll3_m2_ck: dpll3_m2_ck@d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <27>; - ti,max-div = <31>; - reg = <0x0d40>; - ti,index-starts-at-one; - }; - core_ck: core_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -361,12 +351,46 @@ clock-div = <1>; }; - omap_96m_fck: omap_96m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0d40>; + /* CM_CLKSEL1_PLL */ + clock@d40 { + compatible = "ti,clksel"; + reg = <0xd40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m2_ck: clock-dpll3-m2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m2_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <27>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + omap_96m_fck: clock-omap-96m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_96m_fck"; + clocks = <&cm_96m_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + omap_54m_fck: clock-omap-54m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_54m_fck"; + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; + ti,bit-shift = <5>; + }; + + omap_48m_fck: clock-omap-48m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_48m_fck"; + clocks = <&cm_96m_d2_fck>, <&sys_altclk>; + ti,bit-shift = <3>; + }; }; dpll4_m3_ck: dpll4_m3_ck@e40 { @@ -396,14 +420,6 @@ ti,set-bit-to-disable; }; - omap_54m_fck: omap_54m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; - reg = <0x0d40>; - }; - cm_96m_d2_fck: cm_96m_d2_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -412,14 +428,6 @@ clock-div = <2>; }; - omap_48m_fck: omap_48m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; - reg = <0x0d40>; - }; - omap_12m_fck: omap_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; From 0019a9543a71995304bf2c2aa493d8242f387587 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 593/791] ARM: dts: Group omap3 CM_CLKOUT_CTRL clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 52 +++++++++++++++----------- 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index d101f0a40502..01c4b312c89a 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -527,19 +527,37 @@ clock-div = <1>; }; - clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0d70>; - }; + /* CM_CLKOUT_CTRL */ + clock@d70 { + compatible = "ti,clksel"; + reg = <0xd70>; + #clock-cells = <2>; + #address-cells = <0>; - clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; - reg = <0x0d70>; + clkout2_src_gate_ck: clock-clkout2-src-gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "clkout2_src_gate_ck"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + }; + + clkout2_src_mux_ck: clock-clkout2-src-mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "clkout2_src_mux_ck"; + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; + }; + + sys_clkout2: clock-sys-clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sys_clkout2"; + clocks = <&clkout2_src_ck>; + ti,bit-shift = <3>; + ti,max-div = <64>; + ti,index-power-of-two; + }; }; clkout2_src_ck: clkout2_src_ck { @@ -548,16 +566,6 @@ clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; }; - sys_clkout2: sys_clkout2@d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0d70>; - ti,index-power-of-two; - }; - mpu_ck: mpu_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; From 89953638a83cb5b55193f720653de931fa92347c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 594/791] ARM: dts: Group omap3 CM_FCLKEN_DSS clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 21 +++++--- ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 21 +++++--- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 48 +++++++++++-------- 3 files changed, 56 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 7dbab6eb2e6d..24adfac26be0 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -170,13 +170,20 @@ clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es1"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es1@e10 { diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 1c41530cc16a..dcc5cfcd1fe6 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -179,13 +179,20 @@ }; }; - dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es2"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es2@e10 { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 01c4b312c89a..5a192fc149c0 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1022,28 +1022,36 @@ clock-div = <1>; }; - dss_tv_fck: dss_tv_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_54m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; + /* CM_FCLKEN_DSS */ + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; - dss_96m_fck: dss_96m_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_96m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; + dss_tv_fck: clock-dss-tv-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_tv_fck"; + clocks = <&omap_54m_fck>; + ti,bit-shift = <2>; + }; - dss2_alwon_fck: dss2_alwon_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0e00>; - ti,bit-shift = <1>; + dss_96m_fck: clock-dss-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_96m_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <2>; + }; + + dss2_alwon_fck: clock-dss2-alwon-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss2_alwon_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <1>; + }; }; dummy_ck: dummy_ck { From 2d09a2a9d13163b9b401cc0d88c1166c6dd18b1c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 595/791] ARM: dts: Group omap3 CM_CLKSEL_DSS clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 42 +++++++++++++++----------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 5a192fc149c0..30f6847ef65e 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -393,14 +393,31 @@ }; }; - dpll4_m3_ck: dpll4_m3_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; + /* CM_CLKSEL_DSS */ + clock@e40 { + compatible = "ti,clksel"; + reg = <0xe40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll4_m3_ck: clock-dpll4-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m3_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-starts-at-one; + }; + + dpll4_m4_ck: clock-dpll4-m4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m4_ck"; + clocks = <&dpll4_ck>; + ti,max-div = <16>; + ti,index-starts-at-one; + }; }; dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { @@ -436,15 +453,6 @@ clock-div = <4>; }; - dpll4_m4_ck: dpll4_m4_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <16>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; From 32169e7ef4be5cb3af7c2c32fde9e07171b4c80b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 596/791] ARM: dts: Group omap3 CM_FCLKEN_CAM clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 38 +++++++++++-------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index edc28654d158..8374532f20e2 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -60,13 +60,29 @@ }; }; - cam_mclk: cam_mclk@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; - reg = <0x0f00>; - ti,set-rate-parent; + /* CM_FCLKEN_CAM */ + clock@f00 { + compatible = "ti,clksel"; + reg = <0xf00>; + #clock-cells = <2>; + #address-cells = <0>; + + cam_mclk: clock-cam-mclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "cam_mclk"; + clocks = <&dpll4_m5x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; + + csi2_96m_fck: clock-csi2-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "csi2_96m_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <1>; + }; }; cam_ick: cam_ick@f10 { @@ -77,14 +93,6 @@ ti,bit-shift = <0>; }; - csi2_96m_fck: csi2_96m_fck@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0f00>; - ti,bit-shift = <1>; - }; - security_l3_ick: security_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; From b508079bf2dca43995eb2cfa2aef5a4e7d82d2e6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 597/791] ARM: dts: Group omap3 CM_FCLKEN_PER clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap36xx-clocks.dtsi | 17 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 288 +++++++++++++------------ 2 files changed, 160 insertions(+), 145 deletions(-) diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 4e9cc9003594..c5fdb2bd765d 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -58,12 +58,19 @@ ti,set-bit-to-disable; }; - uart4_fck: uart4_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - ti,bit-shift = <18>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck: clock-uart4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <18>; + }; }; }; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 30f6847ef65e..fa5b5756545c 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1186,20 +1186,156 @@ clock-div = <1>; }; - uart3_fck: uart3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; + /* CM_FCLKEN_PER */ + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - ti,bit-shift = <11>; - }; + #clock-cells = <2>; + #address-cells = <0>; - gpt2_gate_fck: gpt2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1000>; + uart3_fck: clock-uart3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart3_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <11>; + }; + + gpt2_gate_fck: clock-gpt2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt2_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt3_gate_fck: clock-gpt3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt3_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt4_gate_fck: clock-gpt4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt4_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt5_gate_fck: clock-gpt5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt5_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt6_gate_fck: clock-gpt6-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt6_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; + + gpt7_gate_fck: clock-gpt7-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt7_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <8>; + }; + + gpt8_gate_fck: clock-gpt8-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt8_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <9>; + }; + + gpt9_gate_fck: clock-gpt9-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt9_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <10>; + }; + + gpio6_dbck: clock-gpio6-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio6_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <17>; + }; + + gpio5_dbck: clock-gpio5-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio5_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <16>; + }; + + gpio4_dbck: clock-gpio4-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio4_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <15>; + }; + + gpio3_dbck: clock-gpio3-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio3_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <14>; + }; + + gpio2_dbck: clock-gpio2-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio2_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <13>; + }; + + wdt3_fck: clock-wdt3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt3_fck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <12>; + }; + + mcbsp2_gate_fck: clock-mcbsp2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp2_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <0>; + }; + + mcbsp3_gate_fck: clock-mcbsp3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp3_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <1>; + }; + + mcbsp4_gate_fck: clock-mcbsp4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp4_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <2>; + }; }; gpt2_mux_fck: gpt2_mux_fck@1040 { @@ -1215,14 +1351,6 @@ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_gate_fck: gpt3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1000>; - }; - gpt3_mux_fck: gpt3_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1237,14 +1365,6 @@ clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_gate_fck: gpt4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1000>; - }; - gpt4_mux_fck: gpt4_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1259,14 +1379,6 @@ clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_gate_fck: gpt5_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1000>; - }; - gpt5_mux_fck: gpt5_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1281,14 +1393,6 @@ clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_gate_fck: gpt6_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1000>; - }; - gpt6_mux_fck: gpt6_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1303,14 +1407,6 @@ clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_gate_fck: gpt7_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <8>; - reg = <0x1000>; - }; - gpt7_mux_fck: gpt7_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1325,14 +1421,6 @@ clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_gate_fck: gpt8_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <9>; - reg = <0x1000>; - }; - gpt8_mux_fck: gpt8_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1347,14 +1435,6 @@ clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_gate_fck: gpt9_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <10>; - reg = <0x1000>; - }; - gpt9_mux_fck: gpt9_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1377,54 +1457,6 @@ clock-div = <1>; }; - gpio6_dbck: gpio6_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <17>; - }; - - gpio5_dbck: gpio5_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <16>; - }; - - gpio4_dbck: gpio4_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <15>; - }; - - gpio3_dbck: gpio3_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <14>; - }; - - gpio2_dbck: gpio2_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <13>; - }; - - wdt3_fck: wdt3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <12>; - }; - per_l4_ick: per_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1585,30 +1617,6 @@ ti,bit-shift = <2>; }; - mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; - reg = <0x1000>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; - reg = <0x1000>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x1000>; - }; - emu_src_mux_ck: emu_src_mux_ck@1140 { #clock-cells = <0>; compatible = "ti,mux-clock"; From cab3db1b8d15a4daccda72f94397192bc6e4d298 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 598/791] ARM: dts: Group omap3 CM_ICLKEN_PER clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 270 +++++++++++++------------ 1 file changed, 139 insertions(+), 131 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index fa5b5756545c..05e5d50fa022 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1465,156 +1465,164 @@ clock-div = <1>; }; - gpio6_ick: gpio6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; + /* CM_ICLKEN_PER */ + clock@1010 { + compatible = "ti,clksel"; reg = <0x1010>; - ti,bit-shift = <17>; - }; + #clock-cells = <2>; + #address-cells = <0>; - gpio5_ick: gpio5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <16>; - }; + gpio6_ick: clock-gpio6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <17>; + }; - gpio4_ick: gpio4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <15>; - }; + gpio5_ick: clock-gpio5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <16>; + }; - gpio3_ick: gpio3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <14>; - }; + gpio4_ick: clock-gpio4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <15>; + }; - gpio2_ick: gpio2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <13>; - }; + gpio3_ick: clock-gpio3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <14>; + }; - wdt3_ick: wdt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <12>; - }; + gpio2_ick: clock-gpio2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <13>; + }; - uart3_ick: uart3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <11>; - }; + wdt3_ick: clock-wdt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <12>; + }; - uart4_ick: uart4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <18>; - }; + uart3_ick: clock-uart3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <11>; + }; - gpt9_ick: gpt9_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <10>; - }; + uart4_ick: clock-uart4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <18>; + }; - gpt8_ick: gpt8_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <9>; - }; + gpt9_ick: clock-gpt9-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt9_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <10>; + }; - gpt7_ick: gpt7_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <8>; - }; + gpt8_ick: clock-gpt8-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt8_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <9>; + }; - gpt6_ick: gpt6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <7>; - }; + gpt7_ick: clock-gpt7-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt7_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <8>; + }; - gpt5_ick: gpt5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <6>; - }; + gpt6_ick: clock-gpt6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <7>; + }; - gpt4_ick: gpt4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <5>; - }; + gpt5_ick: clock-gpt5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <6>; + }; - gpt3_ick: gpt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <4>; - }; + gpt4_ick: clock-gpt4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <5>; + }; - gpt2_ick: gpt2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <3>; - }; + gpt3_ick: clock-gpt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <4>; + }; - mcbsp2_ick: mcbsp2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <0>; - }; + gpt2_ick: clock-gpt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <3>; + }; - mcbsp3_ick: mcbsp3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <1>; - }; + mcbsp2_ick: clock-mcbsp2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <0>; + }; - mcbsp4_ick: mcbsp4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <2>; + mcbsp3_ick: clock-mcbsp3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <1>; + }; + + mcbsp4_ick: clock-mcbsp4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <2>; + }; }; emu_src_mux_ck: emu_src_mux_ck@1140 { From c22a3d8cad504f18efb437a6998f8948e7dc992f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 599/791] ARM: dts: Group omap3 CM_CLKSEL_PER clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 128 +++++++++++++------------ 1 file changed, 68 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 05e5d50fa022..8a16e49fdf24 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1338,11 +1338,75 @@ }; }; - gpt2_mux_fck: gpt2_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; + /* CM_CLKSEL_PER */ + clock@1040 { + compatible = "ti,clksel"; reg = <0x1040>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt2_mux_fck: clock-gpt2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt2_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + + gpt3_mux_fck: clock-gpt3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt3_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <1>; + }; + + gpt4_mux_fck: clock-gpt4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt4_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <2>; + }; + + gpt5_mux_fck: clock-gpt5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt5_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt6_mux_fck: clock-gpt6-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt6_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt7_mux_fck: clock-gpt7-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt7_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt8_mux_fck: clock-gpt8-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt8_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt9_mux_fck: clock-gpt9-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt9_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; }; gpt2_fck: gpt2_fck { @@ -1351,98 +1415,42 @@ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_mux_fck: gpt3_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x1040>; - }; - gpt3_fck: gpt3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_mux_fck: gpt4_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x1040>; - }; - gpt4_fck: gpt4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_mux_fck: gpt5_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1040>; - }; - gpt5_fck: gpt5_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_mux_fck: gpt6_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1040>; - }; - gpt6_fck: gpt6_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_mux_fck: gpt7_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1040>; - }; - gpt7_fck: gpt7_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_mux_fck: gpt8_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1040>; - }; - gpt8_fck: gpt8_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_mux_fck: gpt9_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1040>; - }; - gpt9_fck: gpt9_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 29a5f5f0b08af1bac5c3d2c0948ed7f56ba4d255 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 600/791] ARM: dts: Group omap3 CM_CLKSEL1_EMU clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 152 +++++++++++++------------ 1 file changed, 80 insertions(+), 72 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 8a16e49fdf24..2e13ca11ceea 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -254,14 +254,87 @@ reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; }; - dpll3_m3_ck: dpll3_m3_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; + /* CM_CLKSEL1_EMU */ + clock@1140 { + compatible = "ti,clksel"; reg = <0x1140>; - ti,index-starts-at-one; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m3_ck: clock-dpll3-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m3_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + dpll4_m6_ck: clock-dpll4-m6 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m6_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + ti,index-starts-at-one; + }; + + emu_src_mux_ck: clock-emu-src-mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "emu_src_mux_ck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + }; + + pclk_fck: clock-pclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; + + pclkx2_fck: clock-pclkx2-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclkx2_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + atclk_fck: clock-atclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "atclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: clock-traceclk-src-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "traceclk_src_fck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + }; + + traceclk_fck: clock-traceclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "traceclk_fck"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; }; dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { @@ -500,16 +573,6 @@ ti,set-rate-parent; }; - dpll4_m6_ck: dpll4_m6_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1633,67 +1696,12 @@ }; }; - emu_src_mux_ck: emu_src_mux_ck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - reg = <0x1140>; - }; - emu_src_ck: emu_src_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; clocks = <&emu_src_mux_ck>; }; - pclk_fck: pclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - pclkx2_fck: pclkx2_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - atclk_fck: atclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: traceclk_src_fck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - reg = <0x1140>; - }; - - traceclk_fck: traceclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - secure_32k_fck: secure_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; From f960b54b6f195817f5a9c62257edfd602f026725 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2022 08:51:59 +0200 Subject: [PATCH 601/791] ARM: dts: am33xx: use new 'dma-channels/requests' properties The '#dma-channels' and '#dma-requests' properties were deprecated in favor of these defined by generic dma-common DT bindings. Add new properties while keeping old ones for backwards compatibility. Signed-off-by: Krzysztof Kozlowski Message-Id: <20220503065201.51818-5-krzysztof.kozlowski@linaro.org> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f6ec85d58dd1..9a8698bd2852 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -461,8 +461,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; From e4edfeaf6b585fac340071ea9845970ab528c6ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2022 08:52:01 +0200 Subject: [PATCH 602/791] ARM: dts: dm81xx: use new 'dma-channels/requests' properties The '#dma-channels' and '#dma-requests' properties were deprecated in favor of these defined by generic dma-common DT bindings. Add new properties while keeping old ones for backwards compatibility. Signed-off-by: Krzysztof Kozlowski Message-Id: <20220503065201.51818-7-krzysztof.kozlowski@linaro.org> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 3 +++ arch/arm/boot/dts/dm816x.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 7702e048e110..a92630113f57 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -167,8 +167,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index a9e7274806f4..eb0a95da94b2 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -655,8 +655,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; From bd820bc5e77087a71a42c36f2660b8a35d2c01a5 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 22 Apr 2022 09:28:23 +0200 Subject: [PATCH 603/791] arm64: dts: rockchip: rename HDMI ref clock to 'ref' on rk3399 The reference clock for the HDMI controller has been renamed to 'ref', the previous 'vpll' name is only left for compatibility in the driver. Rename the clock to the new name. Signed-off-by: Sascha Hauer Tested-by: Michael Riesch Link: https://lore.kernel.org/r/20220422072841.2206452-7-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 8db8b2dba12d..fbd0346624e6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1907,7 +1907,7 @@ <&cru SCLK_HDMI_CEC>, <&cru PCLK_VIO_GRF>, <&cru PLL_VPLL>; - clock-names = "iahb", "isfr", "cec", "grf", "vpll"; + clock-names = "iahb", "isfr", "cec", "grf", "ref"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; From 6e82a968b77c7f16a33173485eff2e9a6ae0c6d1 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 3 May 2022 11:06:21 +0200 Subject: [PATCH 604/791] ARM: dts: stm32: add EXTI interrupt-parent to pinctrl node on stm32mp131 Add interrupt-parent property in pinctrl node to use GPIO as IRQ. Signed-off-by: Amelie Delaunay Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 58647396704f..f9ebc47e6421 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -259,6 +259,8 @@ #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; pins-are-numbered; gpioa: gpio@50002000 { From fd91c36fd349f5117cf51c1c9b75f60ac5a7a4fe Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 3 May 2022 11:41:24 +0200 Subject: [PATCH 605/791] ARM: dts: stm32: add blue led (Linux heartbeat) on stm32mp135f-dk The blue led (Linux heartbeat) is connected to the PA14 pin of the stm32mp135f-dk board. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index aefa25ee897d..65acee0f68b7 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include +#include #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -23,6 +25,18 @@ reg = <0xc0000000 0x20000000>; }; + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; From 57012d79fefd56499da681ecd0f94642e8b59992 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 3 May 2022 11:41:33 +0200 Subject: [PATCH 606/791] ARM: dts: stm32: add UserPA13 button on stm32mp135f-dk The PA13 user button is connected to the PA13 pin of the stm32mp135f-dk board. It requires an internal pull-up configuration. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 65acee0f68b7..09d6226d598f 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" @@ -25,6 +26,16 @@ reg = <0xc0000000 0x20000000>; }; + gpio-keys { + compatible = "gpio-keys"; + + user-pa13 { + label = "User-PA13"; + linux,code = ; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + leds { compatible = "gpio-leds"; From f038e8186fbc5723d7d38c6fa1d342945107347e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 26 Apr 2022 20:34:43 +0200 Subject: [PATCH 607/791] ARM: dts: exynos: add atmel,24c128 fallback to Samsung EEPROM The Samsung s524ad0xd1 EEPROM should use atmel,24c128 fallback, according to the AT24 EEPROM bindings. Reported-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220426183443.243113-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 21fbbf3d8684..71293749ac48 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -129,7 +129,7 @@ samsung,i2c-max-bus-freq = <20000>; eeprom@50 { - compatible = "samsung,s524ad0xd1"; + compatible = "samsung,s524ad0xd1", "atmel,24c128"; reg = <0x50>; }; @@ -289,7 +289,7 @@ samsung,i2c-max-bus-freq = <20000>; eeprom@51 { - compatible = "samsung,s524ad0xd1"; + compatible = "samsung,s524ad0xd1", "atmel,24c128"; reg = <0x51>; }; From 50612cf9e05d111c21e84096e50a31d0c35d5825 Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Sat, 30 Apr 2022 19:10:09 +0000 Subject: [PATCH 608/791] arm64: dts: allwinner: teres-i: Add GPIO port regulators Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. Signed-off-by: Harald Geyer Reviewed-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220430191009.73946-1-harald@ccbib.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index aff0660b899c..1128030e4c25 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -197,6 +197,14 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dldo2>; + vcc-pe-supply = <®_aldo1>; + vcc-pf-supply = <®_dcdc1>; /* No dedicated supply-pin for this */ + vcc-pg-supply = <®_aldo2>; +}; + &pwm { status = "okay"; }; From 067bc653b85e466048914c48e46659a50a907fa6 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 14 Apr 2022 17:58:26 -0700 Subject: [PATCH 609/791] arm64: dts: qcom: sc7180: Remove ipa interconnect node This device node is unused now that we've removed the driver that consumed it in the kernel. Drop the unused node to save some space. Cc: Alex Elder Cc: Taniya Das Cc: Mike Tipton Cc: Georgi Djakov Signed-off-by: Stephen Boyd Acked-by: Georgi Djakov Reviewed-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415005828.1980055-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 86175d257b1e..82fa009e540f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1421,13 +1421,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sc7180-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; From 02fbeb1649534d564b100a994b05d4eaa167ea19 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 14 Apr 2022 17:58:27 -0700 Subject: [PATCH 610/791] ARM: dts: qcom: sdx55: Remove ipa interconnect node This device node is unused now that we've removed the driver that consumed it in the kernel. Drop the unused node to save some space. Cc: Alex Elder Cc: Taniya Das Cc: Mike Tipton Cc: Georgi Djakov Signed-off-by: Stephen Boyd Reviewed-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415005828.1980055-2-swboyd@chromium.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 4d45be049613..123390721b7f 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -275,13 +275,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sdx55-ipa-virt"; - reg = <0x01e00000 0x100000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - qpic_bam: dma-controller@1b04000 { compatible = "qcom,bam-v1.7.0"; reg = <0x01b04000 0x1c000>; From 497b272759986af1aa5a25b5e903d082c67bd8f6 Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Thu, 21 Apr 2022 21:26:06 +0530 Subject: [PATCH 611/791] arm64: dts: qcom: sc7280-idp: Configure CTS pin to bias-bus-hold for bluetooth WLAN rail was leaking power during RBSC/sleep even after turning BT off. Change active and sleep pinctrl configurations to handle same. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1650556567-4995-2-git-send-email-quic_vnivarth@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 6a14259b93c4..5eb668991e24 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -408,10 +408,13 @@ &qup_uart7_cts { /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. */ - bias-pull-down; + bias-bus-hold; }; &qup_uart7_rts { @@ -503,10 +506,13 @@ pins = "gpio28"; function = "gpio"; /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. */ - bias-pull-down; + bias-bus-hold; }; qup_uart7_sleep_rts: qup-uart7-sleep-rts { From 3d0e375bae55c2dfa6dd0762f45ad71f0b192f71 Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Thu, 21 Apr 2022 21:26:07 +0530 Subject: [PATCH 612/791] arm64: dts: qcom: sc7280-qcard: Configure CTS pin to bias-bus-hold for bluetooth WLAN rail was leaking power during RBSC/sleep even after turning BT off. Change active and sleep pinctrl configurations to handle same. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1650556567-4995-3-git-send-email-quic_vnivarth@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index b833ba1e8f4a..98b5cd70bca5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -398,8 +398,14 @@ mos_bt_uart: &uart7 { /* For mos_bt_uart */ &qup_uart7_cts { - /* Configure a pull-down on CTS to match the pull of the Bluetooth module. */ - bias-pull-down; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; }; /* For mos_bt_uart */ @@ -490,10 +496,13 @@ mos_bt_uart: &uart7 { pins = "gpio28"; function = "gpio"; /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. */ - bias-pull-down; + bias-bus-hold; }; /* For mos_bt_uart */ From 88044abcde58ebf810f4be49ee2555ecc333bad4 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 21 Apr 2022 23:42:41 +0200 Subject: [PATCH 613/791] ARM: dts: qcom: msm8974-FP2: Add support for touchscreen Configure the touchscreen found on the new display module of the FP2. To add some detail, FP2 has two different screen/touchscreen variants ("display module"), the old module has Synaptics touchscreen, the new one this Ilitek touchscreen. We're only supporting the new display module for now. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421214243.352469-1-luca@z3ntu.xyz --- .../boot/dts/qcom-msm8974pro-fairphone-fp2.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 26fc2002e5c3..d0ae19a9874e 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -57,6 +57,21 @@ }; }; +&blsp1_i2c2 { + status = "okay"; + + touchscreen@41 { + compatible = "ilitek,ili2120"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + &blsp1_uart2 { status = "okay"; }; From da281bf9345a8bcde224976b83d6ad7899830e97 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 21 Apr 2022 23:42:42 +0200 Subject: [PATCH 614/791] ARM: dts: qcom: msm8974-FP2: Configure charger Set the relevant properties on the smbb charger to allow the device to charge properly. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421214243.352469-2-luca@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index d0ae19a9874e..a52ffae62edf 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -354,6 +354,16 @@ pinctrl-1 = <&sdc2_off>; }; +&smbb { + usb-charge-current-limit = <1500000>; + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,fast-charge-safe-voltage = <4380000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4240000>; + qcom,minimum-input-voltage = <4450000>; +}; + &tlmm { sdc1_on: sdc1-on { clk { From fb5e339fb1bc9eb7f34b341d995e4ab39c03588e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 21 Apr 2022 23:42:43 +0200 Subject: [PATCH 615/791] ARM: dts: qcom: msm8974-FP2: Add supplies for remoteprocs Those were removed from msm8974.dtsi as part of a recent cleanup commit, so add them back for FP2. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421214243.352469-3-luca@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index a52ffae62edf..58cb2ce1e4df 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -146,6 +146,17 @@ }; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + &rpm_requests { pm8841-regulators { compatible = "qcom,rpm-pm8841-regulators"; From 417aea4436bb658d8c5c4dcd0e3c255931d0ee96 Mon Sep 17 00:00:00 2001 From: SHIMAMOTO Takayoshi Date: Fri, 22 Apr 2022 00:10:54 +0900 Subject: [PATCH 616/791] ARM: dts: BCM5301X: Add DT for WZR-1166DHP,DHP2 Buffalo WZR-1166DHP/WZR-1166DHP2 wireless router with - BCM4708A0 - 128MiB NAND flash - 2T2R 11ac/a/b/g/n Wi-Fi - 4x 10/100/1000M ethernet switch - 1x USB 3.0 port WZR-1166DHP and WZR-1166DHP2 have different memory capacity. WZR-1166DHP - 512 MiB DDR2 SDRAM WZR-1166DHP2 - 256 MiB DDR2 SDRAM These hardware components are very similar to the WZR-1750DHP except for the number of antennas. Signed-off-by: SHIMAMOTO Takayoshi Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 2 + .../bcm4708-buffalo-wzr-1166dhp-common.dtsi | 192 ++++++++++++++++++ .../boot/dts/bcm4708-buffalo-wzr-1166dhp.dts | 26 +++ .../boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts | 26 +++ 4 files changed, 246 insertions(+) create mode 100644 arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi create mode 100644 arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts create mode 100644 arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ff0054d55590..e2e7c08fd166 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -103,6 +103,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac68u.dtb \ bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp2.dtb \ bcm4708-linksys-ea6300-v1.dtb \ bcm4708-linksys-ea6500-v2.dtb \ bcm4708-luxul-xap-1510.dtb \ diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi new file mode 100644 index 000000000000..d659e409a17e --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2 + * + * Copyright (C) 2014 Rafał Miłecki + * Copyright (C) 2022 SHIMAMOTO Takayoshi + */ + + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include + +/ { + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + gpio-sck = <&chipcommon 7 0>; + gpio-mosi = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + usb { + /* label = "bcm53xx:blue:usb"; */ + function = LED_FUNCTION_USB; + color = ; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>, <&ohci_port2>, + <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + power0 { + /* label = "bcm53xx:red:power"; */ + function = LED_FUNCTION_FAULT; + color = ; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + }; + + power1 { + /* label = "bcm53xx:white:power"; */ + function = LED_FUNCTION_POWER; + color = ; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router0 { + /* label = "bcm53xx:blue:router"; */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router1 { + /* label = "bcm53xx:amber:router"; */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + wan { + /* label = "bcm53xx:blue:wan"; */ + function = LED_FUNCTION_WAN; + color = ; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + wireless0 { + /* label = "bcm53xx:blue:wireless"; */ + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + wireless1 { + /* label = "bcm53xx:amber:wireless"; */ + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + aoss { + label = "AOSS"; + linux,code = ; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + mode { + label = "Mode"; + linux,code = ; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + sw_ap { + label = "AP"; + linux,code = ; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + eject { + label = "USB eject"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts new file mode 100644 index 000000000000..8e506269fa1a --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts new file mode 100644 index 000000000000..596129027074 --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP2 + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP2"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + +}; From f223095c6e1d20aac831e75016b58ca8adbbf122 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2022 11:26:31 +0200 Subject: [PATCH 617/791] arm64: dts: exynos: move XTCXO clock frequency to board in Exynos Auto v9 The external oscillator - XTCXO - is an input to the SoC. It is defined in the Exynos Auto v9 SoC DTSI, because all boards will provide it and clock controller bindings expect it, however the actual frequency of the clock should be determined by the board. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Chanho Park Link: https://lore.kernel.org/r/20220503092631.174713-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts | 4 ++++ arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index 57518cb5e8c4..17e568853eb6 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -58,3 +58,7 @@ &usi_0 { status = "okay"; }; + +&xtcxo { + clock-frequency = <26000000>; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 807d500d6022..68d087ed0459 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -153,7 +153,6 @@ xtcxo: clock { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <26000000>; clock-output-names = "oscclk"; }; From 03e1d34d27a5e8065c5ef691648ee8a519e3c1b0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:19:01 +0200 Subject: [PATCH 618/791] arm64: dts: exynos: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 6 ------ arch/arm64/boot/dts/exynos/exynos7.dtsi | 4 ---- 2 files changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 017ccc2f4650..75b548e495a0 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1866,8 +1866,6 @@ clocks = <&cmu_fsys CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@15600000 { @@ -1877,8 +1875,6 @@ clocks = <&cmu_fsys CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; audio-subsystem@11400000 { @@ -1898,8 +1894,6 @@ clocks = <&cmu_aud CLK_ACLK_DMAC>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; power-domains = <&pd_aud>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index e38bb02a2152..1cd771c90b47 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -149,8 +149,6 @@ clocks = <&clock_fsys0 ACLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@10eb0000 { @@ -160,8 +158,6 @@ clocks = <&clock_fsys0 ACLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; clock_topc: clock-controller@10570000 { From 6745dbc73112819529d776275b4e76dae5c12680 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:19:02 +0200 Subject: [PATCH 619/791] arm64: dts: fsd: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/tesla/fsd.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 10c217a57a7d..af39655331de 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -432,8 +432,6 @@ reg = <0x0 0x10100000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_imem 0x800 0x0>; @@ -444,8 +442,6 @@ reg = <0x0 0x10110000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_imem 0x801 0x0>; @@ -456,8 +452,6 @@ reg = <0x0 0x14280000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_peric 0x2 0x0>; @@ -468,8 +462,6 @@ reg = <0x0 0x14290000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_peric 0x1 0x0>; From d0b05d3820fa1b688b192699017f95f8a565523b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:59 +0200 Subject: [PATCH 620/791] ARM: dts: s5pv210: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-7-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/s5pv210.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index ac281f42e8f5..f1b85aae8842 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -125,8 +125,6 @@ clocks = <&clocks CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@e0a00000 { @@ -137,8 +135,6 @@ clocks = <&clocks CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; adc: adc@e1700000 { @@ -526,8 +522,6 @@ clocks = <&clocks CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; rotator: rotator@fa300000 { From d414b7a3f370d640cff544a3aa3a41abf34fd5d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:19:00 +0200 Subject: [PATCH 621/791] ARM: dts: exynos: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-8-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/exynos3250.dtsi | 4 ---- arch/arm/boot/dts/exynos4.dtsi | 6 ------ arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 -- arch/arm/boot/dts/exynos5250.dtsi | 8 -------- arch/arm/boot/dts/exynos5410.dtsi | 4 ---- arch/arm/boot/dts/exynos5420.dtsi | 10 ---------- 6 files changed, 34 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 41bb421e67c2..78dad233ff34 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -429,8 +429,6 @@ clocks = <&cmu CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@12690000 { @@ -440,8 +438,6 @@ clocks = <&cmu CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; adc: adc@126c0000 { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 5fd17bc52321..6f0ca3354e39 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -676,8 +676,6 @@ clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@12690000 { @@ -687,8 +685,6 @@ clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; mdma1: dma-controller@12850000 { @@ -698,8 +694,6 @@ clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; fimd: fimd@11c00000 { diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 138d606d58a5..62bf335d5bed 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -666,8 +666,6 @@ clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; power-domains = <&pd_lcd0>; }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index df80ddfada2d..4708dcd575a7 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -700,8 +700,6 @@ clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@121b0000 { @@ -711,8 +709,6 @@ clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; mdma0: dma-controller@10800000 { @@ -722,8 +718,6 @@ clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; mdma1: dma-controller@11c10000 { @@ -733,8 +727,6 @@ clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; gsc_0: gsc@13e00000 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 4d797a9abba4..8a6b890fb8f7 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -196,8 +196,6 @@ clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@121b0000 { @@ -207,8 +205,6 @@ clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; audi2s0: i2s@3830000 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 21b608705049..9f2523a873d9 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -437,8 +437,6 @@ clocks = <&clock_audss EXYNOS_ADMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <6>; - #dma-requests = <16>; power-domains = <&mau_pd>; }; @@ -449,8 +447,6 @@ clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@121b0000 { @@ -460,8 +456,6 @@ clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; mdma0: dma-controller@10800000 { @@ -471,8 +465,6 @@ clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; mdma1: dma-controller@11c10000 { @@ -482,8 +474,6 @@ clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; /* * MDMA1 can support both secure and non-secure * AXI transactions. When this is enabled in From 0501eeca5aedab16a0dc4fd25135eb18d9408f80 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:54 +0200 Subject: [PATCH 622/791] ARM: dts: zynq-7000: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Acked-by: Michal Simek Link: https://lore.kernel.org/r/20220430121902.59895-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/zynq-7000.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 47c2a4b14c06..c193264a86ff 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -343,8 +343,6 @@ <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; From 361736cf495ccc49df5ae66d0f9f10a55976d2da Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:55 +0200 Subject: [PATCH 623/791] ARM: dts: socfpga: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-3-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/socfpga.dtsi | 2 -- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b8c5dd7860cb..bfaef45bdd04 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -80,8 +80,6 @@ <0 110 4>, <0 111 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index f1e50d2e623a..26bda2557fe8 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -73,8 +73,6 @@ <0 90 IRQ_TYPE_LEVEL_HIGH>, <0 91 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; From a93fbb002310ef04fce504dbf1510f6eb8265188 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:56 +0200 Subject: [PATCH 624/791] arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 -- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 884bda106399..aa2bba75265f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -346,8 +346,6 @@ <0 88 4>, <0 89 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index c78371703e76..caccb0334ada 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -350,8 +350,6 @@ , ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; reset-names = "dma", "dma-ocp"; clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; From 8dba791a7280542bc125b68b3547bfa2680bc1af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:58 +0200 Subject: [PATCH 625/791] arm64: dts: broadcom: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 -- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index f59fa3979a04..fda97c47f4e9 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -289,8 +289,6 @@ , ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&iprocslow>; clock-names = "apb_pclk"; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 7f1b8efd0883..09d4aa8ae1d6 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -556,8 +556,6 @@ , ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&hsls_div2_clk>; clock-names = "apb_pclk"; iommus = <&smmu 0x6000 0x0000>; From 6e5b6ce2053c3a7ba94d93962e66b5240e286279 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 11 Apr 2022 00:05:14 +0200 Subject: [PATCH 626/791] dt-bindings: rcc: Add optional external ethernet RX clock properties Describe optional external ethernet RX clock in the DT binding to fix dtbs_check warnings like: arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dt.yaml: rcc@50000000: 'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Gabriel Fernandez Cc: Rob Herring To: devicetree@vger.kernel.org Acked-by: Gabriel Fernandez Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220410220514.21779-1-marex@denx.de Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index a0ae4867ed27..7a251264582d 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -59,6 +59,14 @@ properties: - st,stm32mp1-rcc - const: syscon + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + reg: maxItems: 1 From 35de4b4b82bcfaa5a33fd02e74a453fc67b3b1ec Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:46 +0200 Subject: [PATCH 627/791] dt-bindings: clock: stm32mp1: describes clocks if "st,stm32mp1-rcc-secure" In case of "st,stm32mp1-rcc-secure" (stm32mp1 clock driver with RCC security support hardened), "clocks" and "clock-names" describe oscillators and are required. Signed-off-by: Alexandre Torgue Reviewed-by: Rob Herring --- .../bindings/clock/st,stm32mp1-rcc.yaml | 42 +++++++++++++++---- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index 7a251264582d..bb0e0b92e907 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -58,14 +58,8 @@ properties: - st,stm32mp1-rcc-secure - st,stm32mp1-rcc - const: syscon - - clocks: - description: - Specifies the external RX clock for ethernet MAC. - maxItems: 1 - - clock-names: - const: ETH_RX_CLK/ETH_REF_CLK + clocks: true + clock-names: true reg: maxItems: 1 @@ -76,6 +70,38 @@ required: - compatible - reg +if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-rcc-secure +then: + properties: + clocks: + description: Specifies oscillators. + maxItems: 5 + + clock-names: + items: + - const: hse + - const: hsi + - const: csi + - const: lse + - const: lsi + required: + - clocks + - clock-names +else: + properties: + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + additionalProperties: false examples: From 9b0df592522c6f86283679436f2eac49bd23cdce Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:47 +0200 Subject: [PATCH 628/791] dt-bindings: clock: stm32mp15: rename CK_SCMI define As we only have one SCMI instance, it's not necessary to add an index to the name. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- include/dt-bindings/clock/stm32mp1-clks.h | 46 +++++++++++------------ 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index e02770b98e6c..25e8cfd43459 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -249,30 +249,26 @@ #define STM32MP1_LAST_CLK 232 /* SCMI clock identifiers */ -#define CK_SCMI0_HSE 0 -#define CK_SCMI0_HSI 1 -#define CK_SCMI0_CSI 2 -#define CK_SCMI0_LSE 3 -#define CK_SCMI0_LSI 4 -#define CK_SCMI0_PLL2_Q 5 -#define CK_SCMI0_PLL2_R 6 -#define CK_SCMI0_MPU 7 -#define CK_SCMI0_AXI 8 -#define CK_SCMI0_BSEC 9 -#define CK_SCMI0_CRYP1 10 -#define CK_SCMI0_GPIOZ 11 -#define CK_SCMI0_HASH1 12 -#define CK_SCMI0_I2C4 13 -#define CK_SCMI0_I2C6 14 -#define CK_SCMI0_IWDG1 15 -#define CK_SCMI0_RNG1 16 -#define CK_SCMI0_RTC 17 -#define CK_SCMI0_RTCAPB 18 -#define CK_SCMI0_SPI6 19 -#define CK_SCMI0_USART1 20 - -#define CK_SCMI1_PLL3_Q 0 -#define CK_SCMI1_PLL3_R 1 -#define CK_SCMI1_MCU 2 +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_PLL2_Q 5 +#define CK_SCMI_PLL2_R 6 +#define CK_SCMI_MPU 7 +#define CK_SCMI_AXI 8 +#define CK_SCMI_BSEC 9 +#define CK_SCMI_CRYP1 10 +#define CK_SCMI_GPIOZ 11 +#define CK_SCMI_HASH1 12 +#define CK_SCMI_I2C4 13 +#define CK_SCMI_I2C6 14 +#define CK_SCMI_IWDG1 15 +#define CK_SCMI_RNG1 16 +#define CK_SCMI_RTC 17 +#define CK_SCMI_RTCAPB 18 +#define CK_SCMI_SPI6 19 +#define CK_SCMI_USART1 20 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ From 5f5d7decf046557876794c5686ee0ccf5907bfde Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:48 +0200 Subject: [PATCH 629/791] dt-bindings: reset: stm32mp15: rename RST_SCMI define As we only have one SCMI instance, it's not necessary to add an index to the name. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- include/dt-bindings/reset/stm32mp1-resets.h | 24 ++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index f3a0ed317835..4ffa7c3612e6 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -107,17 +107,17 @@ #define GPIOK_R 19786 /* SCMI reset domain identifiers */ -#define RST_SCMI0_SPI6 0 -#define RST_SCMI0_I2C4 1 -#define RST_SCMI0_I2C6 2 -#define RST_SCMI0_USART1 3 -#define RST_SCMI0_STGEN 4 -#define RST_SCMI0_GPIOZ 5 -#define RST_SCMI0_CRYP1 6 -#define RST_SCMI0_HASH1 7 -#define RST_SCMI0_RNG1 8 -#define RST_SCMI0_MDMA 9 -#define RST_SCMI0_MCU 10 -#define RST_SCMI0_MCU_HOLD_BOOT 11 +#define RST_SCMI_SPI6 0 +#define RST_SCMI_I2C4 1 +#define RST_SCMI_I2C6 2 +#define RST_SCMI_USART1 3 +#define RST_SCMI_STGEN 4 +#define RST_SCMI_GPIOZ 5 +#define RST_SCMI_CRYP1 6 +#define RST_SCMI_HASH1 7 +#define RST_SCMI_RNG1 8 +#define RST_SCMI_MDMA 9 +#define RST_SCMI_MCU 10 +#define RST_SCMI_MCU_HOLD_BOOT 11 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ From 40b4157dbd8cfecbfafdf64aaa562c140a4a5ef1 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:50 +0200 Subject: [PATCH 630/791] ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 Enable optee and SCMI clocks/reset protocols support. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 7fdc324b3cf9..1b2fd3426a81 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -115,6 +115,33 @@ status = "disabled"; }; + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + status = "disabled"; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -122,6 +149,20 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + status = "disabled"; + }; + }; + timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; From 8e14ebb1f08f036539c8cd362a9fd173c4befa2a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:51 +0200 Subject: [PATCH 631/791] dt-bindings: arm: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) Add a "secure" version based on SCMI of STM32 boards. Only boards provided by STMicroelectronics are concerned: -STM32MP157A-DK1 -STM32MP157C-DK2 -STM32MP157C-ED1 -STM32MP157C-EV1 Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- .../devicetree/bindings/arm/stm32/stm32.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index a93c60241f28..8b31565fee59 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -75,6 +75,23 @@ properties: - const: st,stm32mp157 - items: + - const: st,stm32mp157a-dk1-scmi + - const: st,stm32mp157a-dk1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-dk2-scmi + - const: st,stm32mp157c-dk2 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ed1-scmi + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1-scmi - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 From 5b7e58313a77e951850586cfaa9f5d60122f908f Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 22 Apr 2022 17:09:52 +0200 Subject: [PATCH 632/791] ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) Add a "secure" version based on SCMI of STM32 boards. Only boards provided by STMicroelectronics are concerned: -STM32MP157A-DK1 -STM32MP157C-DK2 -STM32MP157C-ED1 -STM32MP157C-EV1 Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 4 + arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 86 ++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 95 ++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 91 +++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 100 +++++++++++++++++++++ 5 files changed, 376 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2585ba8e1293..11bedf200a86 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1163,6 +1163,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ stm32mp157a-iot-box.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ @@ -1173,9 +1174,12 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ stm32mp157c-emsbc-argon.dtb \ stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts new file mode 100644 index 000000000000..e3d3f3f30c7d --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; + compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts new file mode 100644 index 000000000000..45dcd299aa9e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; + compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts new file mode 100644 index 000000000000..458e0ca3cded --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ed1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; + compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts new file mode 100644 index 000000000000..df9c113edb4b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", + "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m_can1 { + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; From 0017f2c856e21bb900be88469e15dac4f41f4065 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Fri, 29 Apr 2022 13:58:43 +0100 Subject: [PATCH 633/791] arm64: tegra: Add missing DFLL reset on Tegra210 Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") removed deassertion of reset lines when enabling peripheral clocks. This breaks the initialization of the DFLL driver which relied on this behaviour. In order to be able to fix this, add the corresponding reset to the DT. Tested on Google Pixel C. Cc: stable@vger.kernel.org Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 218a2b32200f..4f0e51f1a343 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1366,8 +1366,9 @@ <&tegra_car TEGRA210_CLK_DFLL_REF>, <&tegra_car TEGRA210_CLK_I2C5>; clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; - reset-names = "dvco"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, + <&tegra_car 155>; + reset-names = "dvco", "dfll"; #clock-cells = <0>; clock-output-names = "dfllCPU_out"; status = "disabled"; From 5be66d2dc8873edcf215804067b1c076b00c6887 Mon Sep 17 00:00:00 2001 From: Satya Priya Date: Tue, 22 Feb 2022 11:25:08 +0530 Subject: [PATCH 634/791] arm64: dts: qcom: pm8350c: Add pwm support Add pwm support for PM8350C pmic. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645509309-16142-4-git-send-email-quic_c_skakit@quicinc.com --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index 9bc6464477bd..e0bbb67717fe 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -29,6 +29,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pm8350c_pwm: pwm@e800 { + compatible = "qcom,pm8350c-pwm"; + reg = <0xe800>; + #pwm-cells = <2>; + status = "disabled"; + }; }; }; From 82096cc644098ab610e6df5238341907ea662164 Mon Sep 17 00:00:00 2001 From: Satya Priya Date: Tue, 22 Feb 2022 11:25:09 +0530 Subject: [PATCH 635/791] arm64: dts: qcom: Enable pm8350c pwm for sc7280-idp2 Enable pm8350c pmic pwm support for backlight on sc7280-idp2. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645509309-16142-5-git-send-email-quic_c_skakit@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 73b9911dd802..d4f7cab17078 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -34,3 +34,7 @@ &nvme_3v3_regulator { gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; }; + +&pm8350c_pwm { + status = "okay"; +}; From aadc48f7c4ecd11b4fba7ba7d5ed1788ce32bb78 Mon Sep 17 00:00:00 2001 From: Katherine Perez Date: Tue, 7 Dec 2021 15:17:36 -0800 Subject: [PATCH 636/791] arm64: dts: qcom: sm8350-duo2: enable battery charger Enable the relevant qup and I2C nodes to enable the battery charger. Signed-off-by: Katherine Perez Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211207231736.1762503-2-kaperez@linux.microsoft.com --- .../boot/dts/qcom/sm8350-microsoft-surface-duo2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 9cb1d8455fd0..9a6faa9393dc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -281,6 +281,14 @@ firmware-name = "qcom/sm8350/microsoft/cdsp.mbn"; }; +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + &ipa { status = "okay"; @@ -296,6 +304,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/microsoft/slpi.mbn"; From 1c1271e3bd28f293d336d92a78cce65b59c1d2d0 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:13 -0500 Subject: [PATCH 637/791] ARM: dts: ls1021a: remove "simple-bus" compatible from ifc node The binding of ifc device has been updated. Update dts to match accordingly. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 2e69d6eab4d1..52835d3dfa1b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -123,7 +123,7 @@ }; ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; status = "disabled"; From b4269132ace84954915a6630238a9bc7194fd4a7 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:16 -0500 Subject: [PATCH 638/791] ARM: dts: update ifc node name to be memory-controller Update the node name to be align with latest binding. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 52835d3dfa1b..dca1bfbd028e 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -122,7 +122,7 @@ interrupts = ; }; - ifc: ifc@1530000 { + ifc: memory-controller@1530000 { compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; From fefbc0021940a1da023eeff7634341841a048acf Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:14 -0500 Subject: [PATCH 639/791] arm64: dts: remove "simple-bus" compatible from ifc node The binding of ifc device has been updated. Update dts to match accordingly. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 35d1939e690b..e0dc64452569 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -390,7 +390,7 @@ }; ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = <0 43 0x4>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 4e7bd04d9798..6a51f33b382b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -281,7 +281,7 @@ }; ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 18e529118476..5578078c64d2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -397,7 +397,7 @@ }; ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; little-endian; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 1282b61da8a5..eb63117b44fb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -1037,7 +1037,7 @@ }; ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 0x4>; /* Level high type */ little-endian; From e55264f3d7581e8a352ef734109edede7e7befbb Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:17 -0500 Subject: [PATCH 640/791] arm64: dts: freescale: update ifc node name to be memory-controller Update the node name to be align with updated DT binding. But be noted that u-boot for ls1088a used the ifc node name to disable ifc-nor node when the SoC is configured to use QSPI. The u-boot has been updated to use the latest name but the change could break compatibility with older u-boot for ls1088a. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e0dc64452569..0c9c9edeb9ff 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -389,7 +389,7 @@ big-endian; }; - ifc: ifc@1530000 { + ifc: memory-controller@1530000 { compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = <0 43 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 6a51f33b382b..9d53730b956b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -280,7 +280,7 @@ big-endian; }; - ifc: ifc@1530000 { + ifc: memory-controller@1530000 { compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 5578078c64d2..80bf1e672e5c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -396,7 +396,7 @@ #interrupt-cells = <2>; }; - ifc: ifc@2240000 { + ifc: memory-controller@2240000 { compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index eb63117b44fb..202650a4a91c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -1036,7 +1036,7 @@ QORIQ_CLK_PLL_DIV(4)>; }; - ifc: ifc@2240000 { + ifc: memory-controller@2240000 { compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 0x4>; /* Level high type */ From eefe06b295087caa24340888b9465d7dc61df856 Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Mon, 25 Apr 2022 19:12:23 +0530 Subject: [PATCH 641/791] arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. General features: - NXP i.MX8M Plus - Up to 4GB LDDR4 - 8 eMMC - Gigabit Ethernet - USB 3.0, 2.0 Host/OTG - PCIe 3.0 interface - I2S - LVDS - rest of i.MX8M Plus features i.Core MX8M Plus needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Manoj Sai Signed-off-by: Matteo Lisi Reviewed-by: Jagan Teki Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-icore-mx8mp.dtsi | 186 ++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi new file mode 100644 index 000000000000..5116079cce22 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,icore-mx8mp", "fsl,imx8mp"; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x25>; + + regulators { + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1025000>; + regulator-min-microvolt = <720000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3600000>; + regulator-min-microvolt = <3000000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "LDO1"; + }; + + ldo3: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <1710000>; + regulator-name = "LDO3"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; +}; + +/* EMMC */ +&usdhc3 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; +}; From aec8ad34f7f248381288919f4fc1315e8abad90d Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Mon, 25 Apr 2022 19:12:24 +0530 Subject: [PATCH 642/791] arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Plus PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Manoj Sai Signed-off-by: Matteo Lisi Reviewed-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 175 ++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index cdf9dfcbe020..238a83e5b8c6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts new file mode 100644 index 000000000000..70a701a624a6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-icore-mx8mp.dtsi" +#include + +/ { + model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit"; + compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + reg_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1_host_vbus"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* SDCARD */ +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + pinctrl-names = "default" ; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_reg_usb1: regusb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; +}; From 8b3dd27bfe47abe30450d01077983497aa1a159f Mon Sep 17 00:00:00 2001 From: Paul Elder Date: Wed, 6 Apr 2022 17:33:54 +0200 Subject: [PATCH 643/791] dt-bindings: soc: Add i.MX8MP media block control DT bindings The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral providing access to the NoC and ensuring proper power sequencing of the peripherals within the MEDIAMIX domain. Add DT bindings for it. There is already a driver for block controls of other SoCs in the i.MX8M family, so these bindings will expand upon that. Signed-off-by: Paul Elder Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Reviewed-by: Marek Vasut Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 104 ++++++++++++++++++ include/dt-bindings/power/imx8mp-power.h | 10 ++ 2 files changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml new file mode 100644 index 000000000000..21d3ee486295 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP Media Block Control + +maintainers: + - Paul Elder + +description: + The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral + providing access to the NoC and ensuring proper power sequencing of the + peripherals within the MEDIAMIX domain. + +properties: + compatible: + items: + - const: fsl,imx8mp-media-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + maxItems: 10 + + power-domain-names: + items: + - const: bus + - const: mipi-dsi1 + - const: mipi-csi1 + - const: lcdif1 + - const: isi + - const: mipi-csi2 + - const: lcdif2 + - const: isp + - const: dwe + - const: mipi-dsi2 + + clocks: + items: + - description: The APB clock + - description: The AXI clock + - description: The pixel clock for the first CSI2 receiver (aclk) + - description: The pixel clock for the second CSI2 receiver (aclk) + - description: The pixel clock for the first LCDIF (pix_clk) + - description: The pixel clock for the second LCDIF (pix_clk) + - description: The core clock for the ISP (clk) + - description: The MIPI-PHY reference clock used by DSI + + clock-names: + items: + - const: apb + - const: axi + - const: cam1 + - const: cam2 + - const: disp1 + - const: disp2 + - const: isp + - const: phy + +required: + - compatible + - reg + - '#power-domain-cells' + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + media_blk_ctl: blk-ctl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; + reg = <0x32ec0000 0x138>; + power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>, + <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>, + <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>, + <&mipi_phy2_pd>; + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi", + "mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2"; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; + clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", + "isp", "phy"; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h index 9f90c40a2c6c..bc8458f1e725 100644 --- a/include/dt-bindings/power/imx8mp-power.h +++ b/include/dt-bindings/power/imx8mp-power.h @@ -32,4 +32,14 @@ #define IMX8MP_HSIOBLK_PD_PCIE 3 #define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1 +#define IMX8MP_MEDIABLK_PD_LCDIF_1 2 +#define IMX8MP_MEDIABLK_PD_ISI 3 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 +#define IMX8MP_MEDIABLK_PD_LCDIF_2 5 +#define IMX8MP_MEDIABLK_PD_ISP 6 +#define IMX8MP_MEDIABLK_PD_DWE 7 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 + #endif From f11cf9e35e7f740d158e298baf5764bcdd8a199e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Apr 2022 17:33:56 +0200 Subject: [PATCH 644/791] dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains This adds the defines for the power domains provided by the HDMI blk-ctrl on the i.MX8MP. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo --- include/dt-bindings/power/imx8mp-power.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h index bc8458f1e725..7789bcca3223 100644 --- a/include/dt-bindings/power/imx8mp-power.h +++ b/include/dt-bindings/power/imx8mp-power.h @@ -42,4 +42,12 @@ #define IMX8MP_MEDIABLK_PD_DWE 7 #define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 +#define IMX8MP_HDMIBLK_PD_IRQSTEER 0 +#define IMX8MP_HDMIBLK_PD_LCDIF 1 +#define IMX8MP_HDMIBLK_PD_PAI 2 +#define IMX8MP_HDMIBLK_PD_PVI 3 +#define IMX8MP_HDMIBLK_PD_TRNG 4 +#define IMX8MP_HDMIBLK_PD_HDMI_TX 5 +#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6 + #endif From e95a7329f83781916ff5c1a52c1f7641757ff1e2 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Apr 2022 17:33:57 +0200 Subject: [PATCH 645/791] dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl Add the DT binding for the HDMI blk-ctrl found on the i.MX8MP SoC. Signed-off-by: Lucas Stach Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml new file mode 100644 index 000000000000..563e1d0e327f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP HDMI blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the display pipeline + peripherals located in the HDMI domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mp-hdmi-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 8 + maxItems: 8 + + power-domain-names: + items: + - const: bus + - const: irqsteer + - const: lcdif + - const: pai + - const: pvi + - const: trng + - const: hdmi-tx + - const: hdmi-tx-phy + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: apb + - const: axi + - const: ref_266m + - const: ref_24m + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x23c>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "axi", "ref_266m", "ref_24m"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>; + power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy"; + #power-domain-cells = <1>; + }; From eca2eee48d78af51bddacbd40844fb2ce3767616 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Feb 2022 01:17:37 +0100 Subject: [PATCH 646/791] dt-bindings: arm: Add Data Modul i.MX8M Mini eDM SBC Add DT compatible string for Data Modul i.MX8M Mini eDM SBC board into YAML DT binding document. This system is an evaluation board for various custom display units. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Reviewed-by: Peng Fan Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 08bdd30e511c..55d6e866acb9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -762,6 +762,7 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board + - dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board From 5c35e2284103ea2674d95a7532d6d4e2bb759553 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 22 Feb 2022 08:09:41 +0100 Subject: [PATCH 647/791] dt-bindings: arm: fsl: add TQ Systems boards based on i.MX6UL(L) TQMa6ULx is a SOM family using NXP i.MX6UL CPU family. TQMa6ULLx is a SOM family using NXP i.MX6ULL CPU family. Both are available as a socket type as well as an LGA type. For both variants there are the mainboards MBa6ULx and MBa6ULxL, trailing 'L' is LGA version. Finally there is the possibility to use the socket module with an LGA adapter on the MBa6ULxL. The SOM needs a mainboard, therefore we provide compatibles using this naming schema: "tq,imx6ul-" for the module and "tq,imx6ul--" for when mounted on the mainboard. The i.MX6ULL version is done similar. Signed-off-by: Matthias Schiffer Acked-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 55d6e866acb9..09bb76bf24b6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -613,6 +613,28 @@ properties: - const: kontron,imx6ul-n6310-som - const: fsl,imx6ul + - description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul1-mba6ulx + - const: tq,imx6ul-tqma6ul1 # MCIMX6G1 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board + items: + - enum: + - tq,imx6ul-tqma6ul2-mba6ulx + - const: tq,imx6ul-tqma6ul2 # MCIMX6G2 + - const: fsl,imx6ul + + - description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter + - tq,imx6ul-tqma6ul2l-mba6ulxl + - const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant + - const: fsl,imx6ul + - description: i.MX6ULL based Boards items: - enum: @@ -667,6 +689,21 @@ properties: - const: kontron,imx6ull-n6411-som - const: fsl,imx6ull + - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board + items: + - enum: + - tq,imx6ull-tqma6ull2-mba6ulx + - const: tq,imx6ull-tqma6ull2 # MCIMX6Y2 + - const: fsl,imx6ull + + - description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board + items: + - enum: + - tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter + - tq,imx6ull-tqma6ull2l-mba6ulxl + - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant + - const: fsl,imx6ull + - description: i.MX6ULZ based Boards items: - enum: From 5a10857a8e35c71f526965211759dffbc54b5827 Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 22 Feb 2022 10:16:04 +0100 Subject: [PATCH 648/791] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL Add devicetree bindings for phyGATE Tauri board with phyCORE-i.MX6 ULL. Signed-off-by: Andrej Picej Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 09bb76bf24b6..03b8d8cf2c6b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -662,6 +662,15 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyGATE-Tauri + items: + - enum: + - phytec,imx6ull-phygate-tauri-emmc + - phytec,imx6ull-phygate-tauri-nand + - const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL + - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: From afd406d7328e93bf99467e9ad866c34beb9f306f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 Apr 2022 21:21:41 +0200 Subject: [PATCH 649/791] dt-bindings: arm: Add i.MX53 based Menlo board comment Add comment regarding the i.MX53 based Menlo board. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 03b8d8cf2c6b..8a7ed7782e99 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -172,7 +172,7 @@ properties: - karo,tx53 # Ka-Ro electronics TX53 module - kiebackpeter,imx53-ddc # K+P imx53 DDC - kiebackpeter,imx53-hsc # K+P imx53 HSC - - menlo,m53menlo + - menlo,m53menlo # i.MX53 Menlo board - voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668 - const: fsl,imx53 From a84091746e50111b0dd6722eca7230d5719ffd18 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 8 Apr 2022 16:57:24 +0200 Subject: [PATCH 650/791] dt-bindings: arm: fsl: add toradex,verdin-imx8mp et al. Add toradex,verdin-imx8mp for the Verdin iMX8M Plus modules, its nonwifi and wifi variants and the carrier boards (both Dahlia and the Verdin Development Board) they may be mated in. Signed-off-by: Marcel Ziswiler Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 8a7ed7782e99..b6cc34115362 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -907,6 +907,9 @@ properties: items: - enum: - fsl,imx8mp-evk # i.MX8MP EVK Board + - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules + - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT + - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules - const: fsl,imx8mp - description: PHYTEC phyCORE-i.MX8MP SoM based boards @@ -915,6 +918,24 @@ properties: - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM - const: fsl,imx8mp + - description: Toradex Boards with Verdin iMX8M Plus Modules + items: + - enum: + - toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia + - toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board + - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT + - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module + - const: fsl,imx8mp + + - description: Toradex Boards with Verdin iMX8M Plus Wi-Fi / BT Modules + items: + - enum: + - toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia + - toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B. + - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module + - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module + - const: fsl,imx8mp + - description: i.MX8MQ based Boards items: - enum: From 31963ac56eb5ff6af62787128d635975d8d103e5 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:21 +0200 Subject: [PATCH 651/791] dt-bindings: arm: fsl: imx6dl-colibri: Drop dedicated v1.1 bindings The dedicated device tree for V1.1 modules has been dropped. Remove its bindings too. Acked-by: Rob Herring Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b6cc34115362..5b434e21844f 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -411,7 +411,6 @@ properties: - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - toradex,colibri_imx6dl # Colibri iMX6 Modules - - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board @@ -492,13 +491,6 @@ properties: - const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module - const: fsl,imx6dl - - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules - items: - - enum: - - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3 - - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module - - const: fsl,imx6dl - - description: i.MX6S DHCOM DRC02 Board items: - const: dh,imx6s-dhcom-drc02 From 9eef821d3b84c866acbe58a0964e2756990523e9 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:22 +0200 Subject: [PATCH 652/791] dt-bindings: arm: fsl: Add carriers for toradex,colibri-imx6dl Add bindings for Aster, Iris and Iris V2 carrier boards our Colibri iMX6S/DL may be mated with. Acked-by: Rob Herring Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 5b434e21844f..b71fb76d95ee 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -487,7 +487,10 @@ properties: - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules items: - enum: + - toradex,colibri_imx6dl-aster # Colibri iMX6DL/S Module on Aster Board - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3 + - toradex,colibri_imx6dl-iris # Colibri iMX6DL/S Module on Iris Board + - toradex,colibri_imx6dl-iris-v2 # Colibri iMX6DL/S Module on Iris Board V2 - const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module - const: fsl,imx6dl From 84cb08ca541437b061f9d901f3c637d93ebebb2e Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 12 Apr 2022 16:32:37 +0200 Subject: [PATCH 653/791] dt-bindings: arm: fsl: add IMX8MN DDR3L eval board This eval board features an IMX8MN UltraLite and has DDR3L RAM. The product part number is 8MNANOD3L-EVK. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Acked-by: Krzysztof Kozlowski Acked-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b71fb76d95ee..065336080c46 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -876,6 +876,7 @@ properties: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO + - fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board From bed5522940e08ee9b2dc802e4ef53a09e27975e8 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 14 Apr 2022 09:15:04 -0700 Subject: [PATCH 654/791] dt-bindings: arm: Add i.MX8M Plus Gateworks GW74xx board Add DT compatible string for i.MX8M Plus based Gateworks GW74xx board. Signed-off-by: Tim Harvey Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 065336080c46..13aee9fe115e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -903,6 +903,7 @@ properties: items: - enum: - fsl,imx8mp-evk # i.MX8MP EVK Board + - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules From 1299bb1d2e9adbd4e64c7bbd572d67cff09851fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 18 Apr 2022 15:24:56 +0200 Subject: [PATCH 655/791] dt-bindings: arm: Add i.MX8M Mini Toradex Verdin based Menlo board Add DT compatible string for board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo. The board is a compatible replacement for i.MX53 M53Menlo and features USB, multiple UARTs, ethernet, LEDs, SD and eMMC. Acked-by: Peng Fan Acked-by: Rob Herring Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Francesco Dolcini Cc: Marcel Ziswiler Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 13aee9fe115e..754351643cff 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -814,6 +814,7 @@ properties: - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM + - menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules From cff15d3ee66d0412f36fc927a19b27fcc3f9dc20 Mon Sep 17 00:00:00 2001 From: Changming Huang Date: Wed, 20 Apr 2022 10:35:55 +0800 Subject: [PATCH 656/791] dt-bindings: arm: fsl: add ls1021a-iot board Add the board ls1021a-iot in the binding docuemnt. Signed-off-by: Changming Huang Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 754351643cff..b8b0efa55339 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1065,6 +1065,7 @@ properties: - description: LS1021A based Boards items: - enum: + - fsl,ls1021a-iot - fsl,ls1021a-moxa-uc-8410a - fsl,ls1021a-qds - fsl,ls1021a-tsn From 7a0a377425210eb2cdee394db73136631d5dd204 Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Mon, 25 Apr 2022 19:12:22 +0530 Subject: [PATCH 657/791] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add bindings for it. Signed-off-by: Manoj Sai Reviewed-by: Jagan Teki Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b8b0efa55339..d1d79889227e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -910,6 +910,13 @@ properties: - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules - const: fsl,imx8mp + - description: Engicam i.Core MX8M Plus SoM based boards + items: + - enum: + - engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit + - const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM + - const: fsl,imx8mp + - description: PHYTEC phyCORE-i.MX8MP SoM based boards items: - const: phytec,imx8mp-phyboard-pollux-rdk # phyBOARD-Pollux RDK From 2ae42e0c0b67d155cdac1f801f59ac3290650442 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Apr 2022 17:33:59 +0200 Subject: [PATCH 658/791] arm64: dts: imx8mp: add HSIO power-domains This adds the GPC and HSIO blk-ctrl nodes providing power control for the high-speed (USB and PCIe) IOs. Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 ++++++++++++++++++++--- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 7ad824e6b820..3a59ce27e312 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -523,6 +523,21 @@ #address-cells = <1>; #size-cells = <0>; + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb1_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb2_phy: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_gpu2d: power-domain@6 { #power-domain-cells = <0>; reg = ; @@ -549,6 +564,16 @@ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; power-domains = <&pgc_gpumix>; }; + + pgc_hsiomix: power-domains@17 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + }; }; }; }; @@ -970,6 +995,28 @@ }; }; + aips4: bus@32c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; @@ -1030,6 +1077,7 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; #phy-cells = <0>; status = "disabled"; }; @@ -1042,6 +1090,7 @@ <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -1055,9 +1104,6 @@ <&clk IMX8MP_CLK_USB_CORE_REF>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; interrupts = ; phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; @@ -1073,6 +1119,7 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; #phy-cells = <0>; status = "disabled"; }; @@ -1085,6 +1132,7 @@ <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -1098,9 +1146,6 @@ <&clk IMX8MP_CLK_USB_CORE_REF>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; interrupts = ; phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; From 9d89189d5227507a05a6029818e1a2e2b074522a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Apr 2022 17:34:00 +0200 Subject: [PATCH 659/791] arm64: dts: imx8mp: Add MEDIAMIX power domains Add the power domains related to the MEDIAMIX to the GPC. Signed-off-by: Laurent Pinchart Reviewed-by: Marek Vasut Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3a59ce27e312..a0b4957f7a16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -523,6 +523,11 @@ #address-cells = <1>; #size-cells = <0>; + pgc_mipi_phy1: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_pcie_phy: power-domain@1 { #power-domain-cells = <0>; reg = ; @@ -565,6 +570,18 @@ power-domains = <&pgc_gpumix>; }; + pgc_mediamix: power-domain@10 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + pgc_mipi_phy2: power-domain@16 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_hsiomix: power-domains@17 { #power-domain-cells = <0>; reg = ; @@ -574,6 +591,12 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; }; + + pgc_ispdwp: power-domain@18 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + }; }; }; }; From 29f440a7bda8df98c595f6ac29cd196fa1df394a Mon Sep 17 00:00:00 2001 From: Paul Elder Date: Wed, 6 Apr 2022 17:34:01 +0200 Subject: [PATCH 660/791] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for the camera and display devices. Signed-off-by: Paul Elder Signed-off-by: Laurent Pinchart Reviewed-by: Marek Vasut Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a0b4957f7a16..ed75bd30d9af 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1025,6 +1025,44 @@ #size-cells = <1>; ranges; + media_blk_ctrl: blk-ctrl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", + "syscon"; + reg = <0x32ec0000 0x10000>; + power-domains = <&pgc_mediamix>, + <&pgc_mipi_phy1>, + <&pgc_mipi_phy1>, + <&pgc_mediamix>, + <&pgc_mediamix>, + <&pgc_mipi_phy2>, + <&pgc_mediamix>, + <&pgc_ispdwp>, + <&pgc_ispdwp>, + <&pgc_mipi_phy2>; + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", + "lcdif1", "isi", "mipi-csi2", + "lcdif2", "isp", "dwe", + "mipi-dsi2"; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; + clock-names = "apb", "axi", "cam1", "cam2", + "disp1", "disp2", "isp", "phy"; + + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + + #power-domain-cells = <1>; + }; + hsio_blk_ctrl: blk-ctrl@32f10000 { compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; reg = <0x32f10000 0x24>; From 3a70c8b607c45dfc5306771879270ba00e74160a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Apr 2022 10:27:34 -0300 Subject: [PATCH 661/791] ARM: dts: mba6ulx: Remove unnecessary #address-cells/#size-cells The following W=1 dtc warning is seen: arch/arm/boot/dts/mba6ulx.dtsi:33.26-64.4: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the unnecessary #address-cells/#size-cells to fix it. Fixes: 7b8861d8e627 ("ARM: dts: imx6ul: add TQ-Systems MBa6ULx device trees") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/mba6ulx.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi index fc38e185a51e..aac42df9ecf6 100644 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -32,8 +32,6 @@ gpio_buttons: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_buttons>; From a25875276e93636a8d1878c564d635f1a18bac24 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:18:20 -0300 Subject: [PATCH 662/791] ARM: dts: imx6dl-plybas: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Oleksij Rempel Signed-off-by: Fabio Estevam Reviewed-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plybas.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts index bf72a67a9c76..c52e6caf3996 100644 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/imx6dl-plybas.dts @@ -214,7 +214,7 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; linux,rs485-enabled-at-boot-time; rs485-rts-delay = <0 20>; status = "okay"; From 89bbe4e4ba0ac2402ac6fd268acedeb44f387a80 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:18:21 -0300 Subject: [PATCH 663/791] ARM: dts: imx6ul-kontron-n6x1x-s: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Frieder Schrempf Signed-off-by: Fabio Estevam Acked-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi index 770f59b23102..a6cf0f21c66d 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -178,7 +178,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; From 83b41ad1dca61ede1c261aa788fe643b746fb546 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:19:16 -0300 Subject: [PATCH 664/791] arm64: dts: imx8mp-verdin: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Marcel Ziswiler Signed-off-by: Fabio Estevam Acked-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi index 34d9bc48c899..36289c175e6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi @@ -61,7 +61,7 @@ /* On-module Bluetooth */ &uart4 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt_uart>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index aa6442be130e..fb17e329cd37 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -760,14 +760,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; }; /* Verdin UART_2 */ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; }; /* Verdin UART_3, used as the Linux Console */ From dab98061d71891a506c3ae2766fd23c07b65f6d3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:19:17 -0300 Subject: [PATCH 665/791] arm64: dts: imx8mq-kontron-pitx-imx8m: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Heiko Thiery Signed-off-by: Fabio Estevam Acked-By: Heiko Thiery Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index 564746d5000d..a91c136797f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts @@ -311,7 +311,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; assigned-clocks = <&clk IMX8MQ_CLK_UART3>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; status = "okay"; From ce92db719adc14c7a8a5acb4bd85cb8a9d072831 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 22 Apr 2022 16:55:37 -0300 Subject: [PATCH 666/791] ARM: dts: imx6sl: Add a label for the cpu node Add a label for the cpu node, so that board devicetree files can reference to the CPU node. This is useful for describing a PMIC voltage that supplies the CPU voltage. For example: &cpu0 { cpu-supply = <&sw1_reg>; Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c7d907c5c352..06a515121dfc 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -50,7 +50,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; From b1f7836d93baff7c8c1e8550e089190d118a95f7 Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Mon, 25 Apr 2022 18:23:50 +0200 Subject: [PATCH 667/791] dt-bindings: arm: fsl: add toradex,colibri-imx6ull Add toradex,colibri-imx6ull for carrier board dts, including aster, iris and iris-v2 device tree, wifi and nonwifi variants for NAND and eMMC modules. Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Acked-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 25 +++++++++++++------ 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d1d79889227e..091db1bdf90b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -669,23 +669,32 @@ properties: - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: - - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board + - toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board + - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3 + - toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board + - toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module - - const: fsl,imx6dl + - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module items: - enum: - - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board - - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - - const: fsl,imx6dl + - toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board + - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3 + - toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board + - toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board + - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module + - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules items: - enum: - - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board - - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module - - const: fsl,imx6dl + - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3 + - toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board + - toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board + - toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board + - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module + - const: fsl,imx6ull - description: Kontron N6411 S Board items: From 13e4e43a1934d22e27a4553cb219133ef9583954 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 21:59:01 +0200 Subject: [PATCH 668/791] arm64: dts: imx8mm: Add CPLD on MX8Menlo board The CPLD on MX8Menlo board is used to operate custom hardware, the CPLD content is compatible with previous M53Menlo CPLD, add the bindings. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Marcel Ziswiler Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Reviewed-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts index c20db0c550da..92eaf4ef4563 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts @@ -71,7 +71,20 @@ &ecspi2 { pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>; cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "disabled"; + status = "okay"; + + spidev@0 { + compatible = "menlo,m53cpld"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + + spidev@1 { + compatible = "menlo,m53cpld"; + reg = <1>; + spi-max-frequency = <25000000>; + }; + }; ðphy0 { From 13305aa53692700a7d2ed2a7ad47965650d8be7b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 22:02:47 +0200 Subject: [PATCH 669/791] arm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBC The USB2 port has USB Hub permanently connected to it, disable OC to avoid getting false OC indication. Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC") Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 154116d01c94..b2d90b79f500 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -962,6 +962,7 @@ }; &usbotg2 { + disable-over-current; dr_mode = "host"; status = "okay"; }; From 42c1a6f62e5c46269ed37238f6a5331b30c32c75 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 22:03:29 +0200 Subject: [PATCH 670/791] arm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC The I2C2 has SMBus device SMSC USB2514Bi connected to it, the device is capable of up to 100 kHz operation. Reduce the bus frequency to 100 kHz to guarantee this I2C device can work correctly. Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC") Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index b2d90b79f500..8c9dd09dbc74 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -392,7 +392,7 @@ &i2c2 { /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ - clock-frequency = <320000>; + clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; From 4ce01ce36d77137cf60776b320babed89de6bd4c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 26 Apr 2022 15:51:43 -0500 Subject: [PATCH 671/791] arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3 There is a header for a DB9 serial port, but any attempts to use hardware handshaking fail. Enable RTS and CTS pin muxing and enable handshaking in the uart node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index ec3f2c177035..f338a886d811 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -278,6 +278,7 @@ pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MM_CLK_UART3>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; status = "okay"; }; @@ -386,6 +387,8 @@ fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 >; }; From 5446ff1a67160ad92d9aae9530846aa54750be36 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 26 Apr 2022 15:51:44 -0500 Subject: [PATCH 672/791] arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3 There is a header for a DB9 serial port, but any attempts to use hardware handshaking fail. Enable RTS and CTS pin muxing and enable handshaking in the uart node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 0f40b43ac091..02f37dcda7ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -175,6 +175,7 @@ pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MN_CLK_UART3>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; status = "okay"; }; @@ -258,6 +259,8 @@ fsl,pins = < MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 >; }; From 51b9d74cdb9fe5d5492214da20ab50173c1e9b08 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 27 Apr 2022 09:53:35 +0200 Subject: [PATCH 673/791] ARM: dts: ls1021a: reduce the interrupt-map-mask Reduce the interrupt-map-mask of the external interrupt controller to 7 to align with the devicetree schema. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index dca1bfbd028e..6c88be2a7e8e 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -192,7 +192,7 @@ <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0x7 0x0>; }; }; From 339c8beae89b0435610b363df378abe10a486542 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 27 Apr 2022 09:53:36 +0200 Subject: [PATCH 674/791] arm64: dts: freescale: reduce the interrup-map-mask Reduce the interrupt-map-mask of the external interrupt controller to 0xf to align with the devicetree schema. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 0c9c9edeb9ff..21200cbf7161 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -335,7 +335,7 @@ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 9d53730b956b..0085e83adf65 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -341,7 +341,7 @@ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 80bf1e672e5c..f476b7d8b056 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -265,7 +265,7 @@ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 202650a4a91c..4ba1e0499dfd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -305,7 +305,7 @@ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 82bd8c0f318b..47ea854720ce 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -698,7 +698,7 @@ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; From fcc070a44ecce5e800725136ce2e47ce00d40ca7 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 27 Apr 2022 12:42:05 +0300 Subject: [PATCH 675/791] ARM: dts: imx6qdl-phytec: Add LED labels This allows boards the option of adding properties or disabling the LEDs entirely. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1f2ba6f6254e..768bc0e3a2b3 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -47,12 +47,12 @@ pinctrl-0 = <&pinctrl_leds>; compatible = "gpio-leds"; - green { + led_green: green { label = "phyflex:green"; gpios = <&gpio1 30 0>; }; - red { + led_red: red { label = "phyflex:red"; gpios = <&gpio2 31 0>; }; From 5bb0276031b2c768667f6902c8eda8ddefab74d0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 27 Apr 2022 18:15:32 +0200 Subject: [PATCH 676/791] dt-bindings: dmaengine: fsl-imx: deprecate '#dma-channels' and '#dma-requests' The generic properties, used in most of the drivers and defined in generic dma-common DT bindings, are 'dma-channels' and 'dma-requests'. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/dma/fsl-imx-dma.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt index 7bd8847d6394..1c9929d53727 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt @@ -13,8 +13,10 @@ Required properties: - #dma-cells : Has to be 1. imx-dma does not support anything else. Optional properties: -- #dma-channels : Number of DMA channels supported. Should be 16. -- #dma-requests : Number of DMA requests supported. +- dma-channels : Number of DMA channels supported. Should be 16. +- #dma-channels : deprecated +- dma-requests : Number of DMA requests supported. +- #dma-requests : deprecated Example: @@ -23,7 +25,7 @@ Example: reg = <0x10001000 0x1000>; interrupts = <32 33>; #dma-cells = <1>; - #dma-channels = <16>; + dma-channels = <16>; }; From 552de48b9e429ca723cd5c3c2613769a428d98dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 27 Apr 2022 18:15:33 +0200 Subject: [PATCH 677/791] ARM: dts: imx27: use new 'dma-channels' property The '#dma-channels' property was deprecated in favor of one defined by generic dma-common DT bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index fd525c3b16fa..b660c7d05584 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -96,7 +96,7 @@ <&clks IMX27_CLK_DMA_AHB_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <1>; - #dma-channels = <16>; + dma-channels = <16>; }; wdog: watchdog@10002000 { From 8f2ca252ee1f848d3eec9ebbbf3c3881cb423322 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sun, 1 May 2022 18:47:13 +0100 Subject: [PATCH 678/791] ARM: dts: imx6qdl-udoo: Disable USB host to work around boot issues Attempting to boot my Udoo Dual and Quad with mainline hangs during boot after printing: [ 3.270471] imx_usb 2184000.usb: No over current polarity defined [ 3.922502] mxs_phy 20c9000.usbphy: Data pin can't make good contact. [ 3.940097] imx_usb 2184200.usb: No over current polarity defined where imx_usb 2184200.usb is usbh1 in the DT. Adding debug prints to the code seems to show that we lock up at the first read in usbmisc_imx6q_init() which in combination with the above logging about the USB controllers suggests that we lock up on the first read in usbmisc_imx6q_init(). Looking at some of the other i.MX6 boards and the warning messages that are being printed suggests that there is bitrot in the DTS for the device so disable it for now, with it disabled the board boots successfully. Clearly this is not a real fix, but it does allow some use of the board with mainline. Similar behaviour is seen all the way back as far as v4.19, I tried going back to when the board was added but had toolchain issues. Vendor provided binaries seem fine on the boards so it seems likely that the hardware is fine and the issue is with some combination of the DT and kernel. This should obviously be resolved properly but for now this at least allows the kernel to boot with reduced functionality on these systems. Signed-off-by: Mark Brown Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-udoo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index ccfa8e320be6..93a8123da27d 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -295,7 +295,7 @@ pinctrl-0 = <&pinctrl_usbh>; vbus-supply = <®_usb_h1_vbus>; clocks = <&clks IMX6QDL_CLK_CKO>; - status = "okay"; + status = "disabled"; }; &usbotg { From 680e1c8370a2ed7aff4f99ce3cebf79873d68f59 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:43 +0900 Subject: [PATCH 679/791] dt-bindings: clock: add clock binding definitions for Exynos Auto v9 Add device tree clock binding definitions for below CMU blocks. - CMU_TOP - CMU_BUSMC - CMU_CORE - CMU_FYS2 - CMU_PERIC0 / C1 - CMU_PERIS Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chanho Park Acked-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220504075154.58819-2-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../dt-bindings/clock/samsung,exynosautov9.h | 299 ++++++++++++++++++ 1 file changed, 299 insertions(+) create mode 100644 include/dt-bindings/clock/samsung,exynosautov9.h diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h new file mode 100644 index 000000000000..71ec0a955364 --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Samsung Electronics Co., Ltd. + * Author: Chanho Park + * + * Device Tree binding constants for Exynos Auto V9 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H +#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H + +/* CMU_TOP */ +#define FOUT_SHARED0_PLL 1 +#define FOUT_SHARED1_PLL 2 +#define FOUT_SHARED2_PLL 3 +#define FOUT_SHARED3_PLL 4 +#define FOUT_SHARED4_PLL 5 + +/* MUX in CMU_TOP */ +#define MOUT_SHARED0_PLL 6 +#define MOUT_SHARED1_PLL 7 +#define MOUT_SHARED2_PLL 8 +#define MOUT_SHARED3_PLL 9 +#define MOUT_SHARED4_PLL 10 +#define MOUT_CLKCMU_CMU_BOOST 11 +#define MOUT_CLKCMU_CMU_CMUREF 12 +#define MOUT_CLKCMU_ACC_BUS 13 +#define MOUT_CLKCMU_APM_BUS 14 +#define MOUT_CLKCMU_AUD_CPU 15 +#define MOUT_CLKCMU_AUD_BUS 16 +#define MOUT_CLKCMU_BUSC_BUS 17 +#define MOUT_CLKCMU_BUSMC_BUS 19 +#define MOUT_CLKCMU_CORE_BUS 20 +#define MOUT_CLKCMU_CPUCL0_SWITCH 21 +#define MOUT_CLKCMU_CPUCL0_CLUSTER 22 +#define MOUT_CLKCMU_CPUCL1_SWITCH 24 +#define MOUT_CLKCMU_CPUCL1_CLUSTER 25 +#define MOUT_CLKCMU_DPTX_BUS 26 +#define MOUT_CLKCMU_DPTX_DPGTC 27 +#define MOUT_CLKCMU_DPUM_BUS 28 +#define MOUT_CLKCMU_DPUS0_BUS 29 +#define MOUT_CLKCMU_DPUS1_BUS 30 +#define MOUT_CLKCMU_FSYS0_BUS 31 +#define MOUT_CLKCMU_FSYS0_PCIE 32 +#define MOUT_CLKCMU_FSYS1_BUS 33 +#define MOUT_CLKCMU_FSYS1_USBDRD 34 +#define MOUT_CLKCMU_FSYS1_MMC_CARD 35 +#define MOUT_CLKCMU_FSYS2_BUS 36 +#define MOUT_CLKCMU_FSYS2_UFS_EMBD 37 +#define MOUT_CLKCMU_FSYS2_ETHERNET 38 +#define MOUT_CLKCMU_G2D_G2D 39 +#define MOUT_CLKCMU_G2D_MSCL 40 +#define MOUT_CLKCMU_G3D00_SWITCH 41 +#define MOUT_CLKCMU_G3D01_SWITCH 42 +#define MOUT_CLKCMU_G3D1_SWITCH 43 +#define MOUT_CLKCMU_ISPB_BUS 44 +#define MOUT_CLKCMU_MFC_MFC 45 +#define MOUT_CLKCMU_MFC_WFD 46 +#define MOUT_CLKCMU_MIF_SWITCH 47 +#define MOUT_CLKCMU_MIF_BUSP 48 +#define MOUT_CLKCMU_NPU_BUS 49 +#define MOUT_CLKCMU_PERIC0_BUS 50 +#define MOUT_CLKCMU_PERIC0_IP 51 +#define MOUT_CLKCMU_PERIC1_BUS 52 +#define MOUT_CLKCMU_PERIC1_IP 53 +#define MOUT_CLKCMU_PERIS_BUS 54 + +/* DIV in CMU_TOP */ +#define DOUT_SHARED0_DIV3 101 +#define DOUT_SHARED0_DIV2 102 +#define DOUT_SHARED1_DIV3 103 +#define DOUT_SHARED1_DIV2 104 +#define DOUT_SHARED1_DIV4 105 +#define DOUT_SHARED2_DIV3 106 +#define DOUT_SHARED2_DIV2 107 +#define DOUT_SHARED2_DIV4 108 +#define DOUT_SHARED4_DIV2 109 +#define DOUT_SHARED4_DIV4 110 +#define DOUT_CLKCMU_CMU_BOOST 111 +#define DOUT_CLKCMU_ACC_BUS 112 +#define DOUT_CLKCMU_APM_BUS 113 +#define DOUT_CLKCMU_AUD_CPU 114 +#define DOUT_CLKCMU_AUD_BUS 115 +#define DOUT_CLKCMU_BUSC_BUS 116 +#define DOUT_CLKCMU_BUSMC_BUS 118 +#define DOUT_CLKCMU_CORE_BUS 119 +#define DOUT_CLKCMU_CPUCL0_SWITCH 120 +#define DOUT_CLKCMU_CPUCL0_CLUSTER 121 +#define DOUT_CLKCMU_CPUCL1_SWITCH 123 +#define DOUT_CLKCMU_CPUCL1_CLUSTER 124 +#define DOUT_CLKCMU_DPTX_BUS 125 +#define DOUT_CLKCMU_DPTX_DPGTC 126 +#define DOUT_CLKCMU_DPUM_BUS 127 +#define DOUT_CLKCMU_DPUS0_BUS 128 +#define DOUT_CLKCMU_DPUS1_BUS 129 +#define DOUT_CLKCMU_FSYS0_BUS 130 +#define DOUT_CLKCMU_FSYS0_PCIE 131 +#define DOUT_CLKCMU_FSYS1_BUS 132 +#define DOUT_CLKCMU_FSYS1_USBDRD 133 +#define DOUT_CLKCMU_FSYS2_BUS 134 +#define DOUT_CLKCMU_FSYS2_UFS_EMBD 135 +#define DOUT_CLKCMU_FSYS2_ETHERNET 136 +#define DOUT_CLKCMU_G2D_G2D 137 +#define DOUT_CLKCMU_G2D_MSCL 138 +#define DOUT_CLKCMU_G3D00_SWITCH 139 +#define DOUT_CLKCMU_G3D01_SWITCH 140 +#define DOUT_CLKCMU_G3D1_SWITCH 141 +#define DOUT_CLKCMU_ISPB_BUS 142 +#define DOUT_CLKCMU_MFC_MFC 143 +#define DOUT_CLKCMU_MFC_WFD 144 +#define DOUT_CLKCMU_MIF_SWITCH 145 +#define DOUT_CLKCMU_MIF_BUSP 146 +#define DOUT_CLKCMU_NPU_BUS 147 +#define DOUT_CLKCMU_PERIC0_BUS 148 +#define DOUT_CLKCMU_PERIC0_IP 149 +#define DOUT_CLKCMU_PERIC1_BUS 150 +#define DOUT_CLKCMU_PERIC1_IP 151 +#define DOUT_CLKCMU_PERIS_BUS 152 + +/* GAT in CMU_TOP */ +#define GOUT_CLKCMU_CMU_BOOST 201 +#define GOUT_CLKCMU_CPUCL0_BOOST 202 +#define GOUT_CLKCMU_CPUCL1_BOOST 203 +#define GOUT_CLKCMU_CORE_BOOST 204 +#define GOUT_CLKCMU_BUSC_BOOST 205 +#define GOUT_CLKCMU_BUSMC_BOOST 206 +#define GOUT_CLKCMU_MIF_BOOST 207 +#define GOUT_CLKCMU_ACC_BUS 208 +#define GOUT_CLKCMU_APM_BUS 209 +#define GOUT_CLKCMU_AUD_CPU 210 +#define GOUT_CLKCMU_AUD_BUS 211 +#define GOUT_CLKCMU_BUSC_BUS 212 +#define GOUT_CLKCMU_BUSMC_BUS 214 +#define GOUT_CLKCMU_CORE_BUS 215 +#define GOUT_CLKCMU_CPUCL0_SWITCH 216 +#define GOUT_CLKCMU_CPUCL0_CLUSTER 217 +#define GOUT_CLKCMU_CPUCL1_SWITCH 219 +#define GOUT_CLKCMU_CPUCL1_CLUSTER 220 +#define GOUT_CLKCMU_DPTX_BUS 221 +#define GOUT_CLKCMU_DPTX_DPGTC 222 +#define GOUT_CLKCMU_DPUM_BUS 223 +#define GOUT_CLKCMU_DPUS0_BUS 224 +#define GOUT_CLKCMU_DPUS1_BUS 225 +#define GOUT_CLKCMU_FSYS0_BUS 226 +#define GOUT_CLKCMU_FSYS0_PCIE 227 +#define GOUT_CLKCMU_FSYS1_BUS 228 +#define GOUT_CLKCMU_FSYS1_USBDRD 229 +#define GOUT_CLKCMU_FSYS1_MMC_CARD 230 +#define GOUT_CLKCMU_FSYS2_BUS 231 +#define GOUT_CLKCMU_FSYS2_UFS_EMBD 232 +#define GOUT_CLKCMU_FSYS2_ETHERNET 233 +#define GOUT_CLKCMU_G2D_G2D 234 +#define GOUT_CLKCMU_G2D_MSCL 235 +#define GOUT_CLKCMU_G3D00_SWITCH 236 +#define GOUT_CLKCMU_G3D01_SWITCH 237 +#define GOUT_CLKCMU_G3D1_SWITCH 238 +#define GOUT_CLKCMU_ISPB_BUS 239 +#define GOUT_CLKCMU_MFC_MFC 240 +#define GOUT_CLKCMU_MFC_WFD 241 +#define GOUT_CLKCMU_MIF_SWITCH 242 +#define GOUT_CLKCMU_MIF_BUSP 243 +#define GOUT_CLKCMU_NPU_BUS 244 +#define GOUT_CLKCMU_PERIC0_BUS 245 +#define GOUT_CLKCMU_PERIC0_IP 246 +#define GOUT_CLKCMU_PERIC1_BUS 247 +#define GOUT_CLKCMU_PERIC1_IP 248 +#define GOUT_CLKCMU_PERIS_BUS 249 + +#define TOP_NR_CLK 249 + +/* CMU_BUSMC */ +#define CLK_MOUT_BUSMC_BUS_USER 1 +#define CLK_DOUT_BUSMC_BUSP 2 +#define CLK_GOUT_BUSMC_PDMA0_PCLK 3 +#define CLK_GOUT_BUSMC_SPDMA_PCLK 4 + +#define BUSMC_NR_CLK 4 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_DOUT_CORE_BUSP 2 +#define CLK_GOUT_CORE_CCI_CLK 3 +#define CLK_GOUT_CORE_CCI_PCLK 4 +#define CLK_GOUT_CORE_CMU_CORE_PCLK 5 + +#define CORE_NR_CLK 5 + +/* CMU_FSYS2 */ +#define CLK_MOUT_FSYS2_BUS_USER 1 +#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 +#define CLK_MOUT_FSYS2_ETHERNET_USER 3 +#define CLK_GOUT_FSYS2_UFS_EMBD0_ACLK 4 +#define CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO 5 +#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6 +#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7 + +#define FSYS2_NR_CLK 7 + +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_IP_USER 2 +#define CLK_MOUT_PERIC0_USI00_USI 3 +#define CLK_MOUT_PERIC0_USI01_USI 4 +#define CLK_MOUT_PERIC0_USI02_USI 5 +#define CLK_MOUT_PERIC0_USI03_USI 6 +#define CLK_MOUT_PERIC0_USI04_USI 7 +#define CLK_MOUT_PERIC0_USI05_USI 8 +#define CLK_MOUT_PERIC0_USI_I2C 9 + +#define CLK_DOUT_PERIC0_USI00_USI 10 +#define CLK_DOUT_PERIC0_USI01_USI 11 +#define CLK_DOUT_PERIC0_USI02_USI 12 +#define CLK_DOUT_PERIC0_USI03_USI 13 +#define CLK_DOUT_PERIC0_USI04_USI 14 +#define CLK_DOUT_PERIC0_USI05_USI 15 +#define CLK_DOUT_PERIC0_USI_I2C 16 + +#define CLK_GOUT_PERIC0_IPCLK_0 20 +#define CLK_GOUT_PERIC0_IPCLK_1 21 +#define CLK_GOUT_PERIC0_IPCLK_2 22 +#define CLK_GOUT_PERIC0_IPCLK_3 23 +#define CLK_GOUT_PERIC0_IPCLK_4 24 +#define CLK_GOUT_PERIC0_IPCLK_5 25 +#define CLK_GOUT_PERIC0_IPCLK_6 26 +#define CLK_GOUT_PERIC0_IPCLK_7 27 +#define CLK_GOUT_PERIC0_IPCLK_8 28 +#define CLK_GOUT_PERIC0_IPCLK_9 29 +#define CLK_GOUT_PERIC0_IPCLK_10 30 +#define CLK_GOUT_PERIC0_IPCLK_11 30 +#define CLK_GOUT_PERIC0_PCLK_0 31 +#define CLK_GOUT_PERIC0_PCLK_1 32 +#define CLK_GOUT_PERIC0_PCLK_2 33 +#define CLK_GOUT_PERIC0_PCLK_3 34 +#define CLK_GOUT_PERIC0_PCLK_4 35 +#define CLK_GOUT_PERIC0_PCLK_5 36 +#define CLK_GOUT_PERIC0_PCLK_6 37 +#define CLK_GOUT_PERIC0_PCLK_7 38 +#define CLK_GOUT_PERIC0_PCLK_8 39 +#define CLK_GOUT_PERIC0_PCLK_9 40 +#define CLK_GOUT_PERIC0_PCLK_10 41 +#define CLK_GOUT_PERIC0_PCLK_11 42 + +#define PERIC0_NR_CLK 42 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_IP_USER 2 +#define CLK_MOUT_PERIC1_USI06_USI 3 +#define CLK_MOUT_PERIC1_USI07_USI 4 +#define CLK_MOUT_PERIC1_USI08_USI 5 +#define CLK_MOUT_PERIC1_USI09_USI 6 +#define CLK_MOUT_PERIC1_USI10_USI 7 +#define CLK_MOUT_PERIC1_USI11_USI 8 +#define CLK_MOUT_PERIC1_USI_I2C 9 + +#define CLK_DOUT_PERIC1_USI06_USI 10 +#define CLK_DOUT_PERIC1_USI07_USI 11 +#define CLK_DOUT_PERIC1_USI08_USI 12 +#define CLK_DOUT_PERIC1_USI09_USI 13 +#define CLK_DOUT_PERIC1_USI10_USI 14 +#define CLK_DOUT_PERIC1_USI11_USI 15 +#define CLK_DOUT_PERIC1_USI_I2C 16 + +#define CLK_GOUT_PERIC1_IPCLK_0 20 +#define CLK_GOUT_PERIC1_IPCLK_1 21 +#define CLK_GOUT_PERIC1_IPCLK_2 22 +#define CLK_GOUT_PERIC1_IPCLK_3 23 +#define CLK_GOUT_PERIC1_IPCLK_4 24 +#define CLK_GOUT_PERIC1_IPCLK_5 25 +#define CLK_GOUT_PERIC1_IPCLK_6 26 +#define CLK_GOUT_PERIC1_IPCLK_7 27 +#define CLK_GOUT_PERIC1_IPCLK_8 28 +#define CLK_GOUT_PERIC1_IPCLK_9 29 +#define CLK_GOUT_PERIC1_IPCLK_10 30 +#define CLK_GOUT_PERIC1_IPCLK_11 30 +#define CLK_GOUT_PERIC1_PCLK_0 31 +#define CLK_GOUT_PERIC1_PCLK_1 32 +#define CLK_GOUT_PERIC1_PCLK_2 33 +#define CLK_GOUT_PERIC1_PCLK_3 34 +#define CLK_GOUT_PERIC1_PCLK_4 35 +#define CLK_GOUT_PERIC1_PCLK_5 36 +#define CLK_GOUT_PERIC1_PCLK_6 37 +#define CLK_GOUT_PERIC1_PCLK_7 38 +#define CLK_GOUT_PERIC1_PCLK_8 39 +#define CLK_GOUT_PERIC1_PCLK_9 40 +#define CLK_GOUT_PERIC1_PCLK_10 41 +#define CLK_GOUT_PERIC1_PCLK_11 42 + +#define PERIC1_NR_CLK 42 + +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_BUS_USER 1 +#define CLK_GOUT_SYSREG_PERIS_PCLK 2 +#define CLK_GOUT_WDT_CLUSTER0 3 +#define CLK_GOUT_WDT_CLUSTER1 4 + +#define PERIS_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */ From e61492e47838f4d99a3ffcc591ba57d1d5d0896f Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:44 +0900 Subject: [PATCH 680/791] dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings Add dt-schema for Exynos Auto v9 SoC clock controller. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220504075154.58819-3-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../clock/samsung,exynosautov9-clock.yaml | 219 ++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml new file mode 100644 index 000000000000..eafc715d2d02 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Auto v9 SoC clock controller + +maintainers: + - Chanho Park + - Chanwoo Choi + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + Exynos Auto v9 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz). + The external OSCCLK must be defined as fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynosautov9.h' header. + +properties: + compatible: + enum: + - samsung,exynosautov9-cmu-top + - samsung,exynosautov9-cmu-busmc + - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-fsys2 + - samsung,exynosautov9-cmu-peric0 + - samsung,exynosautov9-cmu-peric1 + - samsung,exynosautov9-cmu-peris + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-busmc + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_BUSMC bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_busmc_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_core_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys2 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS2 bus clock (from CMU_TOP) + - description: UFS clock (from CMU_TOP) + - description: Ethernet clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys2_bus + - const: dout_fsys2_clkcmu_ufs_embd + - const: dout_fsys2_clkcmu_ethernet + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC0 bus clock (from CMU_TOP) + - description: PERIC0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric0_bus + - const: dout_clkcmu_peric0_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC1 bus clock (from CMU_TOP) + - description: PERIC1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric1_bus + - const: dout_clkcmu_peric1_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peris_bus + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS2 + - | + #include + + cmu_fsys2: clock-controller@17c00000 { + compatible = "samsung,exynosautov9-cmu-fsys2"; + reg = <0x17c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, + <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; + clock-names = "oscclk", + "dout_clkcmu_fsys2_bus", + "dout_fsys2_clkcmu_ufs_embd", + "dout_fsys2_clkcmu_ethernet"; + }; + +... From bf198e2e919ed551794d6eec3fe52e2d1693f0eb Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:13:47 -0700 Subject: [PATCH 681/791] arm64: dts: imx8mm-venice-gw7902: fix pcie bindings Update the pcie bindings to the correct dt bindings: pcie_phy: - use pcie0_refclk - add required clock-names pcie: - remove pcie_phy clock as it comes from phy driver Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 1b03aa154688..f0eccc5b810d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -595,7 +595,8 @@ &pcie_phy { fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; - clocks = <&clk IMX8MM_CLK_DUMMY>; + clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; @@ -604,8 +605,8 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; From 5394461a31c9d1c6a0452a0312f941e0b4d08d74 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:52 +0900 Subject: [PATCH 682/791] arm64: dts: exynos: add initial CMU clock nodes in ExynosAutov9 Add cmu_top, cmu_busmc, cmu_core, cmu_fsys and peric0/c1/s clock nodes. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220504075154.58819-11-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 84 ++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 68d087ed0459..499b9ce3bee1 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -6,6 +6,7 @@ * */ +#include #include #include @@ -189,6 +190,89 @@ reg = <0x10000000 0x24>; }; + cmu_peris: clock-controller@10020000 { + compatible = "samsung,exynosautov9-cmu-peris"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIS_BUS>; + clock-names = "oscclk", + "dout_clkcmu_peris_bus"; + }; + + cmu_peric0: clock-controller@10200000 { + compatible = "samsung,exynosautov9-cmu-peric0"; + reg = <0x10200000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; + clock-names = "oscclk", + "dout_clkcmu_peric0_bus", + "dout_clkcmu_peric0_ip"; + }; + + cmu_peric1: clock-controller@10800000 { + compatible = "samsung,exynosautov9-cmu-peric1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, + <&cmu_top DOUT_CLKCMU_PERIC1_IP>; + clock-names = "oscclk", + "dout_clkcmu_peric1_bus", + "dout_clkcmu_peric1_ip"; + }; + + cmu_fsys2: clock-controller@17c00000 { + compatible = "samsung,exynosautov9-cmu-fsys2"; + reg = <0x17c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, + <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; + clock-names = "oscclk", + "dout_clkcmu_fsys2_bus", + "dout_fsys2_clkcmu_ufs_embd", + "dout_fsys2_clkcmu_ethernet"; + }; + + cmu_core: clock-controller@1b030000 { + compatible = "samsung,exynosautov9-cmu-core"; + reg = <0x1b030000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_CORE_BUS>; + clock-names = "oscclk", + "dout_clkcmu_core_bus"; + }; + + cmu_busmc: clock-controller@1b200000 { + compatible = "samsung,exynosautov9-cmu-busmc"; + reg = <0x1b200000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; + clock-names = "oscclk", + "dout_clkcmu_busmc_bus"; + }; + + cmu_top: clock-controller@1b240000 { + compatible = "samsung,exynosautov9-cmu-top"; + reg = <0x1b240000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>; + clock-names = "oscclk"; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From 4c882968d434c9968f53fbefa3ba6e64ff33d6a0 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:53 +0900 Subject: [PATCH 683/791] arm64: dts: exynos: switch USI clocks in ExynosAutov9 Use CMU clock nodes instead of dummy fixed-rate-clock. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220504075154.58819-12-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 499b9ce3bee1..bb1c7f43b5db 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -157,17 +157,6 @@ clock-output-names = "oscclk"; }; - /* - * Keep the stub clock for serial driver, until proper clock - * driver is implemented. - */ - uart_clock: uart-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133250000>; - clock-output-names = "uart"; - }; - /* * Keep the stub clock for ufs driver, until proper clock * driver is implemented. @@ -354,7 +343,8 @@ #address-cells = <1>; #size-cells = <1>; ranges; - clocks = <&uart_clock>, <&uart_clock>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; clock-names = "pclk", "ipclk"; status = "disabled"; @@ -365,7 +355,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus_dual>; - clocks = <&uart_clock>, <&uart_clock>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; From 9882948322874b1ffdd559e6887397de4c903440 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:54 +0900 Subject: [PATCH 684/791] arm64: dts: exynos: switch UFS clock node in ExynosAutov9 Use cmu_fsys's clock node instead of dummy UFS clock node. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220504075154.58819-13-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index bb1c7f43b5db..0ce46ec5cdc3 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -156,16 +156,6 @@ #clock-cells = <0>; clock-output-names = "oscclk"; }; - - /* - * Keep the stub clock for ufs driver, until proper clock - * driver is implemented. - */ - ufs_core_clock: ufs-core-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <166562500>; - }; }; soc: soc@0 { @@ -382,8 +372,8 @@ <0x17dc0000 0x2200>; /* 3: UFS protector */ reg-names = "hci", "vs_hci", "unipro", "ufsp"; interrupts = ; - clocks = <&ufs_core_clock>, - <&ufs_core_clock>; + clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, + <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; clock-names = "core_clk", "sclk_unipro_main"; freq-table-hz = <0 0>, <0 0>; pinctrl-names = "default"; From 450cec4f7d78fb2e04e3f7f5360e62f4837a4b68 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:16:29 -0700 Subject: [PATCH 685/791] arm64: dts: imx8m*venice: add missing clock-names to pcie_phy Define the missing clock-names property for the pcie_phy required by the fsl,imx8-pcie-phy dt bindings. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 73addc0b8e57..337f2600a276 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -112,6 +112,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 1e7badb2a82e..8b0ef3fa543f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -134,6 +134,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 7a5d45e80982..2561b8b3fb11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -154,6 +154,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 70b2ae55e906..157ade01626e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -678,6 +678,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 1deb2ea8fcc9..a7dae9bd4c11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -540,6 +540,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; From dd6fa8604301248935b0cf15b8ff6352dc5f7637 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:19:44 -0700 Subject: [PATCH 686/791] arm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channel Add missing vdd_5p0 ADC channel for the GW7902 boards. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 7 +++++++ arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index f0eccc5b810d..407ab4592b4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -394,6 +394,13 @@ gw,voltage-divider-ohms = <10000 10000>; }; + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + channel@a2 { gw,mode = <2>; reg = <0xa2>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 2c1f591335ad..367a232675aa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -393,6 +393,13 @@ gw,voltage-divider-ohms = <10000 10000>; }; + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + channel@a2 { gw,mode = <2>; reg = <0xa2>; From 22463f7cd0e17c4b60a0d8ad6c10f62c76840344 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:20:30 -0700 Subject: [PATCH 687/791] arm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp override Remove the unnecessary cpu_alert0 and cpu_crit0 TMU node overrides as these are added dynamically by boot firmware based on CPU temperature grade. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw7901.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 157ade01626e..24737e89038a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -1091,15 +1091,3 @@ >; }; }; - -&cpu_alert0 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; -}; - -&cpu_crit0 { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; -}; From 15ca3f00a1e3a56811371a63bf0c067603226eae Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:48:58 +0200 Subject: [PATCH 688/791] arm64: dt: imx8mq: support pwm polarity inversion The i.MX8MQ has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells and correct board device trees. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 622f3787a186..b86f188a440d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -18,7 +18,7 @@ backlight_dsi: backlight-dsi { compatible = "pwm-backlight"; /* 200 Hz for the PAM2841 */ - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 100>; num-interpolated-steps = <100>; /* Default brightness level (index into the array defined by */ diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 94a13cb500e6..8956a46788fa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -18,7 +18,7 @@ compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 10000>; + pwms = <&pwm2 0 10000 0>; power-supply = <®_main_usb>; enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; brightness-levels = <0 32 64 128 160 200 255>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1eca2b431467..49eadb081b19 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -798,7 +798,7 @@ clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, <&clk IMX8MQ_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -809,7 +809,7 @@ clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, <&clk IMX8MQ_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -820,7 +820,7 @@ clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, <&clk IMX8MQ_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -831,7 +831,7 @@ clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, <&clk IMX8MQ_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; From 957aef026c462f27419082c61cd170f6e2d5c833 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:48:59 +0200 Subject: [PATCH 689/791] arm64: dt: imx8mm: support pwm polarity inversion The i.MX8M Mini has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells and correct board device trees. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 8c9dd09dbc74..778bdbe228d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -35,7 +35,7 @@ brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; default-brightness-level = <7>; enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; /* Disabled by default, unless display board plugged in. */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6a209395452a..c42b966f7a64 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -61,7 +61,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 255>; num-interpolated-steps = <255>; default-brightness-level = <250>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 1ee05677c2dd..1bf070473829 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -758,7 +758,7 @@ clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, <&clk IMX8MM_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -769,7 +769,7 @@ clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, <&clk IMX8MM_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -780,7 +780,7 @@ clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, <&clk IMX8MM_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -791,7 +791,7 @@ clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, <&clk IMX8MM_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; From 6bc1e58055c1ea3ff31335637f62a1b77da5633d Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:49:00 +0200 Subject: [PATCH 690/791] arm64: dt: imx8mn: support pwm polarity inversion The i.MX8M Nano has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 13c51363cc06..176abe8fe659 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -705,7 +705,7 @@ clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, <&clk IMX8MN_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -716,7 +716,7 @@ clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, <&clk IMX8MN_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -727,7 +727,7 @@ clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, <&clk IMX8MN_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -738,7 +738,7 @@ clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, <&clk IMX8MN_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; From d80b9c8422fa8e02b9a92b90fbb328e3e069c649 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:49:01 +0200 Subject: [PATCH 691/791] arm64: dt: imx8mp: support pwm polarity inversion The i.MX8M Plus has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells. Tested on MBa8MPxL mainboard. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ed75bd30d9af..d9542dfff83f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -615,7 +615,7 @@ clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, <&clk IMX8MP_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -626,7 +626,7 @@ clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, <&clk IMX8MP_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -637,7 +637,7 @@ clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, <&clk IMX8MP_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -648,7 +648,7 @@ clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, <&clk IMX8MP_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; From 5652dc5cd96765d236ada1006db1d467c523c3b4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 09:25:08 +0100 Subject: [PATCH 692/791] dt-bindings: memory: renesas,rpc-if: Document RZ/G2UL SoC Document RZ/G2UL RPC-IF bindings. RZ/G2UL RPC-IF is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,rzg2l-rpc-if" will be used as a fallback. Signed-off-by: Biju Das Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220501082508.25511-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 9a6dbf54b540..6744d17f1efd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -39,6 +39,7 @@ properties: - items: - enum: + - renesas,r9a07g043-rpc-if # RZ/G2UL - renesas,r9a07g044-rpc-if # RZ/G2{L,LC} - renesas,r9a07g054-rpc-if # RZ/V2L - const: renesas,rzg2l-rpc-if From 033a26dcbe10476c5203f590dce0537fac802d03 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 14:40:58 +0200 Subject: [PATCH 693/791] dt-bindings: soc: renesas: Move renesas,rzg2l-sysc from arm to soc The Renesas RZ/{G2L,V2L} System Controller (SYSC) DT binding is not really a power-related DT binding, hence it does not belong under Documentation/devicetree/bindings/power/. Move it to Documentation/devicetree/bindings/soc/renesas/. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/a47015888f99476a5206a556dce93503494d9a73.1651495078.git.geert+renesas@glider.be --- .../bindings/{power => soc/renesas}/renesas,rzg2l-sysc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/{power => soc/renesas}/renesas,rzg2l-sysc.yaml (96%) diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml similarity index 96% rename from Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml rename to Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml index c31eeb66319f..ce2875c89329 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" +$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Renesas RZ/{G2L,V2L} System Controller (SYSC) From 96055bf71ab1629cdedff15bcbc04609cfa1f198 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:47 +0100 Subject: [PATCH 694/791] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's Manual (Rev. 1.10, Sep. 2021). Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a09g011-cpg.h | 352 ++++++++++++++++++++++ 1 file changed, 352 insertions(+) create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h new file mode 100644 index 000000000000..41dd585d7115 --- /dev/null +++ b/include/dt-bindings/clock/r9a09g011-cpg.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ + +#include + +/* Module Clocks */ +#define R9A09G011_SYS_CLK 0 +#define R9A09G011_PFC_PCLK 1 +#define R9A09G011_PMC_CORE_CLOCK 2 +#define R9A09G011_GIC_CLK 3 +#define R9A09G011_RAMA_ACLK 4 +#define R9A09G011_ROMA_ACLK 5 +#define R9A09G011_SEC_ACLK 6 +#define R9A09G011_SEC_PCLK 7 +#define R9A09G011_SEC_TCLK 8 +#define R9A09G011_DMAA_ACLK 9 +#define R9A09G011_TSU0_PCLK 10 +#define R9A09G011_TSU1_PCLK 11 + +#define R9A09G011_CST_TRACECLK 12 +#define R9A09G011_CST_SB_CLK 13 +#define R9A09G011_CST_AHB_CLK 14 +#define R9A09G011_CST_ATB_SB_CLK 15 +#define R9A09G011_CST_TS_SB_CLK 16 + +#define R9A09G011_SDI0_ACLK 17 +#define R9A09G011_SDI0_IMCLK 18 +#define R9A09G011_SDI0_IMCLK2 19 +#define R9A09G011_SDI0_CLK_HS 20 +#define R9A09G011_SDI1_ACLK 21 +#define R9A09G011_SDI1_IMCLK 22 +#define R9A09G011_SDI1_IMCLK2 23 +#define R9A09G011_SDI1_CLK_HS 24 +#define R9A09G011_EMM_ACLK 25 +#define R9A09G011_EMM_IMCLK 26 +#define R9A09G011_EMM_IMCLK2 27 +#define R9A09G011_EMM_CLK_HS 28 +#define R9A09G011_NFI_ACLK 29 +#define R9A09G011_NFI_NF_CLK 30 + +#define R9A09G011_PCI_ACLK 31 +#define R9A09G011_PCI_CLK_PMU 32 +#define R9A09G011_PCI_APB_CLK 33 +#define R9A09G011_USB_ACLK_H 34 +#define R9A09G011_USB_ACLK_P 35 +#define R9A09G011_USB_PCLK 36 +#define R9A09G011_ETH0_CLK_AXI 37 +#define R9A09G011_ETH0_CLK_CHI 38 +#define R9A09G011_ETH0_GPTP_EXT 39 + +#define R9A09G011_SDT_CLK 40 +#define R9A09G011_SDT_CLKAPB 41 +#define R9A09G011_SDT_CLK48 42 +#define R9A09G011_GRP_CLK 43 +#define R9A09G011_CIF_P0_CLK 44 +#define R9A09G011_CIF_P1_CLK 45 +#define R9A09G011_CIF_APB_CLK 46 +#define R9A09G011_DCI_CLKAXI 47 +#define R9A09G011_DCI_CLKAPB 48 +#define R9A09G011_DCI_CLKDCI2 49 + +#define R9A09G011_HMI_PCLK 50 +#define R9A09G011_LCI_PCLK 51 +#define R9A09G011_LCI_ACLK 52 +#define R9A09G011_LCI_VCLK 53 +#define R9A09G011_LCI_LPCLK 54 + +#define R9A09G011_AUI_CLK 55 +#define R9A09G011_AUI_CLKAXI 56 +#define R9A09G011_AUI_CLKAPB 57 +#define R9A09G011_AUMCLK 58 +#define R9A09G011_GMCLK0 59 +#define R9A09G011_GMCLK1 60 +#define R9A09G011_MTR_CLK0 61 +#define R9A09G011_MTR_CLK1 62 +#define R9A09G011_MTR_CLKAPB 63 +#define R9A09G011_GFT_CLK 64 +#define R9A09G011_GFT_CLKAPB 65 +#define R9A09G011_GFT_MCLK 66 + +#define R9A09G011_ATGA_CLK 67 +#define R9A09G011_ATGA_CLKAPB 68 +#define R9A09G011_ATGB_CLK 69 +#define R9A09G011_ATGB_CLKAPB 70 +#define R9A09G011_SYC_CNT_CLK 71 + +#define R9A09G011_CPERI_GRPA_PCLK 72 +#define R9A09G011_TIM0_CLK 73 +#define R9A09G011_TIM1_CLK 74 +#define R9A09G011_TIM2_CLK 75 +#define R9A09G011_TIM3_CLK 76 +#define R9A09G011_TIM4_CLK 77 +#define R9A09G011_TIM5_CLK 78 +#define R9A09G011_TIM6_CLK 79 +#define R9A09G011_TIM7_CLK 80 +#define R9A09G011_IIC_PCLK0 81 + +#define R9A09G011_CPERI_GRPB_PCLK 82 +#define R9A09G011_TIM8_CLK 83 +#define R9A09G011_TIM9_CLK 84 +#define R9A09G011_TIM10_CLK 85 +#define R9A09G011_TIM11_CLK 86 +#define R9A09G011_TIM12_CLK 87 +#define R9A09G011_TIM13_CLK 88 +#define R9A09G011_TIM14_CLK 89 +#define R9A09G011_TIM15_CLK 90 +#define R9A09G011_IIC_PCLK1 91 + +#define R9A09G011_CPERI_GRPC_PCLK 92 +#define R9A09G011_TIM16_CLK 93 +#define R9A09G011_TIM17_CLK 94 +#define R9A09G011_TIM18_CLK 95 +#define R9A09G011_TIM19_CLK 96 +#define R9A09G011_TIM20_CLK 97 +#define R9A09G011_TIM21_CLK 98 +#define R9A09G011_TIM22_CLK 99 +#define R9A09G011_TIM23_CLK 100 +#define R9A09G011_WDT0_PCLK 101 +#define R9A09G011_WDT0_CLK 102 +#define R9A09G011_WDT1_PCLK 103 +#define R9A09G011_WDT1_CLK 104 + +#define R9A09G011_CPERI_GRPD_PCLK 105 +#define R9A09G011_TIM24_CLK 106 +#define R9A09G011_TIM25_CLK 107 +#define R9A09G011_TIM26_CLK 108 +#define R9A09G011_TIM27_CLK 109 +#define R9A09G011_TIM28_CLK 110 +#define R9A09G011_TIM29_CLK 111 +#define R9A09G011_TIM30_CLK 112 +#define R9A09G011_TIM31_CLK 113 + +#define R9A09G011_CPERI_GRPE_PCLK 114 +#define R9A09G011_PWM0_CLK 115 +#define R9A09G011_PWM1_CLK 116 +#define R9A09G011_PWM2_CLK 117 +#define R9A09G011_PWM3_CLK 118 +#define R9A09G011_PWM4_CLK 119 +#define R9A09G011_PWM5_CLK 120 +#define R9A09G011_PWM6_CLK 121 +#define R9A09G011_PWM7_CLK 122 + +#define R9A09G011_CPERI_GRPF_PCLK 123 +#define R9A09G011_PWM8_CLK 124 +#define R9A09G011_PWM9_CLK 125 +#define R9A09G011_PWM10_CLK 126 +#define R9A09G011_PWM11_CLK 127 +#define R9A09G011_PWM12_CLK 128 +#define R9A09G011_PWM13_CLK 129 +#define R9A09G011_PWM14_CLK 130 +#define R9A09G011_PWM15_CLK 131 + +#define R9A09G011_CPERI_GRPG_PCLK 132 +#define R9A09G011_CPERI_GRPH_PCLK 133 +#define R9A09G011_URT_PCLK 134 +#define R9A09G011_URT0_CLK 135 +#define R9A09G011_URT1_CLK 136 +#define R9A09G011_CSI0_CLK 137 +#define R9A09G011_CSI1_CLK 138 +#define R9A09G011_CSI2_CLK 139 +#define R9A09G011_CSI3_CLK 140 +#define R9A09G011_CSI4_CLK 141 +#define R9A09G011_CSI5_CLK 142 + +#define R9A09G011_ICB_ACLK1 143 +#define R9A09G011_ICB_GIC_CLK 144 +#define R9A09G011_ICB_MPCLK1 145 +#define R9A09G011_ICB_SPCLK1 146 +#define R9A09G011_ICB_CLK48 147 +#define R9A09G011_ICB_CLK48_2 148 +#define R9A09G011_ICB_CLK48_3 149 +#define R9A09G011_ICB_CLK48_4L 150 +#define R9A09G011_ICB_CLK48_4R 151 +#define R9A09G011_ICB_CLK48_5 152 +#define R9A09G011_ICB_CST_ATB_SB_CLK 153 +#define R9A09G011_ICB_CST_CS_CLK 154 +#define R9A09G011_ICB_CLK100_1 155 +#define R9A09G011_ICB_ETH0_CLK_AXI 156 +#define R9A09G011_ICB_DCI_CLKAXI 157 +#define R9A09G011_ICB_SYC_CNT_CLK 158 + +#define R9A09G011_ICB_DRPA_ACLK 159 +#define R9A09G011_ICB_RFX_ACLK 160 +#define R9A09G011_ICB_RFX_PCLK5 161 +#define R9A09G011_ICB_MMC_ACLK 162 + +#define R9A09G011_ICB_MPCLK3 163 +#define R9A09G011_ICB_CIMA_CLK 164 +#define R9A09G011_ICB_CIMB_CLK 165 +#define R9A09G011_ICB_BIMA_CLK 166 +#define R9A09G011_ICB_FCD_CLKAXI 167 +#define R9A09G011_ICB_VD_ACLK4 168 +#define R9A09G011_ICB_MPCLK4 169 +#define R9A09G011_ICB_VCD_PCLK4 170 + +#define R9A09G011_CA53_CLK 171 +#define R9A09G011_CA53_ACLK 172 +#define R9A09G011_CA53_APCLK_DBG 173 +#define R9A09G011_CST_APB_CA53_CLK 174 +#define R9A09G011_CA53_ATCLK 175 +#define R9A09G011_CST_CS_CLK 176 +#define R9A09G011_CA53_TSCLK 177 +#define R9A09G011_CST_TS_CLK 178 +#define R9A09G011_CA53_APCLK_REG 179 + +#define R9A09G011_DRPA_ACLK 180 +#define R9A09G011_DRPA_DCLK 181 +#define R9A09G011_DRPA_INITCLK 182 + +#define R9A09G011_RAMB0_ACLK 183 +#define R9A09G011_RAMB1_ACLK 184 +#define R9A09G011_RAMB2_ACLK 185 +#define R9A09G011_RAMB3_ACLK 186 + +#define R9A09G011_CIMA_CLKAPB 187 +#define R9A09G011_CIMA_CLK 188 +#define R9A09G011_CIMB_CLK 189 +#define R9A09G011_FAFA_CLK 190 +#define R9A09G011_STG_CLKAXI 191 +#define R9A09G011_STG_CLK0 192 + +#define R9A09G011_BIMA_CLKAPB 193 +#define R9A09G011_BIMA_CLK 194 +#define R9A09G011_FAFB_CLK 195 +#define R9A09G011_FCD_CLK 196 +#define R9A09G011_FCD_CLKAXI 197 + +#define R9A09G011_RIM_CLK 198 +#define R9A09G011_VCD_ACLK 199 +#define R9A09G011_VCD_PCLK 200 +#define R9A09G011_JPG0_CLK 201 +#define R9A09G011_JPG0_ACLK 202 + +#define R9A09G011_MMC_CORE_DDRC_CLK 203 +#define R9A09G011_MMC_ACLK 204 +#define R9A09G011_MMC_PCLK 205 +#define R9A09G011_DDI_APBCLK 206 + +/* Resets */ +#define R9A09G011_SYS_RST_N 0 +#define R9A09G011_PFC_PRESETN 1 +#define R9A09G011_RAMA_ARESETN 2 +#define R9A09G011_ROM_ARESETN 3 +#define R9A09G011_DMAA_ARESETN 4 +#define R9A09G011_SEC_ARESETN 5 +#define R9A09G011_SEC_PRESETN 6 +#define R9A09G011_SEC_RSTB 7 +#define R9A09G011_TSU0_RESETN 8 +#define R9A09G011_TSU1_RESETN 9 +#define R9A09G011_PMC_RESET_N 10 + +#define R9A09G011_CST_NTRST 11 +#define R9A09G011_CST_NPOTRST 12 +#define R9A09G011_CST_NTRST2 13 +#define R9A09G011_CST_CS_RESETN 14 +#define R9A09G011_CST_TS_RESETN 15 +#define R9A09G011_CST_TRESETN 16 +#define R9A09G011_CST_SB_RESETN 17 +#define R9A09G011_CST_AHB_RESETN 18 +#define R9A09G011_CST_TS_SB_RESETN 19 +#define R9A09G011_CST_APB_CA53_RESETN 20 +#define R9A09G011_CST_ATB_SB_RESETN 21 + +#define R9A09G011_SDI0_IXRST 22 +#define R9A09G011_SDI1_IXRST 23 +#define R9A09G011_EMM_IXRST 24 +#define R9A09G011_NFI_MARESETN 25 +#define R9A09G011_NFI_REG_RST_N 26 +#define R9A09G011_USB_PRESET_N 27 +#define R9A09G011_USB_DRD_RESET 28 +#define R9A09G011_USB_ARESETN_P 29 +#define R9A09G011_USB_ARESETN_H 30 +#define R9A09G011_ETH0_RST_HW_N 31 +#define R9A09G011_PCI_ARESETN 32 + +#define R9A09G011_SDT_RSTSYSAX 33 +#define R9A09G011_GRP_RESETN 34 +#define R9A09G011_CIF_RST_N 35 +#define R9A09G011_DCU_RSTSYSAX 36 +#define R9A09G011_HMI_RST_N 37 +#define R9A09G011_HMI_PRESETN 38 +#define R9A09G011_LCI_PRESETN 39 +#define R9A09G011_LCI_ARESETN 40 + +#define R9A09G011_AUI_RSTSYSAX 41 +#define R9A09G011_MTR_RSTSYSAX 42 +#define R9A09G011_GFT_RSTSYSAX 43 +#define R9A09G011_ATGA_RSTSYSAX 44 +#define R9A09G011_ATGB_RSTSYSAX 45 +#define R9A09G011_SYC_RST_N 46 + +#define R9A09G011_TIM_GPA_PRESETN 47 +#define R9A09G011_TIM_GPB_PRESETN 48 +#define R9A09G011_TIM_GPC_PRESETN 49 +#define R9A09G011_TIM_GPD_PRESETN 50 +#define R9A09G011_PWM_GPE_PRESETN 51 +#define R9A09G011_PWM_GPF_PRESETN 52 +#define R9A09G011_CSI_GPG_PRESETN 53 +#define R9A09G011_CSI_GPH_PRESETN 54 +#define R9A09G011_IIC_GPA_PRESETN 55 +#define R9A09G011_IIC_GPB_PRESETN 56 +#define R9A09G011_URT_PRESETN 57 +#define R9A09G011_WDT0_PRESETN 58 +#define R9A09G011_WDT1_PRESETN 59 + +#define R9A09G011_ICB_PD_AWO_RST_N 60 +#define R9A09G011_ICB_PD_MMC_RST_N 61 +#define R9A09G011_ICB_PD_VD0_RST_N 62 +#define R9A09G011_ICB_PD_VD1_RST_N 63 +#define R9A09G011_ICB_PD_RFX_RST_N 64 + +#define R9A09G011_CA53_NCPUPORESET0 65 +#define R9A09G011_CA53_NCPUPORESET1 66 +#define R9A09G011_CA53_NCORERESET0 67 +#define R9A09G011_CA53_NCORERESET1 68 +#define R9A09G011_CA53_NPRESETDBG 69 +#define R9A09G011_CA53_L2RESET 70 +#define R9A09G011_CA53_NMISCRESET_HM 71 +#define R9A09G011_CA53_NMISCRESET_SM 72 +#define R9A09G011_CA53_NARESET 73 + +#define R9A09G011_DRPA_ARESETN 74 + +#define R9A09G011_RAMB0_ARESETN 75 +#define R9A09G011_RAMB1_ARESETN 76 +#define R9A09G011_RAMB2_ARESETN 77 +#define R9A09G011_RAMB3_ARESETN 78 + +#define R9A09G011_CIMA_RSTSYSAX 79 +#define R9A09G011_CIMB_RSTSYSAX 80 +#define R9A09G011_FAFA_RSTSYSAX 81 +#define R9A09G011_STG_RSTSYSAX 82 + +#define R9A09G011_BIMA_RSTSYSAX 83 +#define R9A09G011_FAFB_RSTSYSAX 84 +#define R9A09G011_FCD_RSTSYSAX 85 +#define R9A09G011_RIM_RSTSYSAX 86 +#define R9A09G011_VCD_RESETN 87 +#define R9A09G011_JPG_XRESET 88 + +#define R9A09G011_MMC_CORE_DDRC_RSTN 89 +#define R9A09G011_MMC_ARESETN_N 90 +#define R9A09G011_MMC_PRESETN 91 +#define R9A09G011_DDI_PWROK 92 +#define R9A09G011_DDI_RESET 93 +#define R9A09G011_DDI_RESETN_APB 94 + +#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */ From 5c39d087c98db6bc453e6f7911e7a9713f219a77 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 May 2022 08:19:03 -0300 Subject: [PATCH 695/791] dt-bindings: vendor-prefixes: Add prefix for Storopack Add a vendor prefix entry for Storopack (https://www.storopack.com). Signed-off-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 01430973ecec..0206bb14c1df 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1193,6 +1193,8 @@ patternProperties: description: StorLink Semiconductors, Inc. "^storm,.*": description: Storm Semiconductor, Inc. + "^storopack,.*": + description: Storopack "^summit,.*": description: Summit microelectronics "^sunchip,.*": From 0efdbec205bfd16a537c29eecd535afce195b4d2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 May 2022 08:19:04 -0300 Subject: [PATCH 696/791] dt-bindings: arm: fsl: Add Storopack i.MX7D SMEGW01 board Add DT compatible string for Storopack i.MX7D SMEGW01 board. Signed-off-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 091db1bdf90b..0bf43346d232 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -757,6 +757,7 @@ properties: - kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board - remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet + - storopack,imx7d-smegw01 # Storopack i.MX7D SMEGW01 - technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph From 9ac0ae97e34911177e3b59328055eccbd27cefca Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 May 2022 08:19:05 -0300 Subject: [PATCH 697/791] ARM: dts: imx7d-smegw01: Add support for i.MX7D SMEGW01 board Add support for the i.MX7D SMEGW01 board. This is a gateway board that supports the following peripherals: - eMMC / SD card - RTC - USB modem - Wifi via SDIO - Dual Ethernet - CAN - Serial SRAM Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-smegw01.dts | 469 ++++++++++++++++++++++++++++ 2 files changed, 470 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-smegw01.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 32e9bbf0d13c..0ad8339e07d8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -741,6 +741,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ + imx7d-smegw01.dtb \ imx7d-zii-rmu2.dtb \ imx7d-zii-rpu2.dtb \ imx7s-colibri-aster.dtb \ diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts new file mode 100644 index 000000000000..c6b32064a009 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2020 PHYTEC Messtechnik GmbH +// Author: Jens Lang +// Copyright (C) 2021 Fabio Estevam + +/dts-v1/; +#include +#include "imx7d.dtsi" + +/ { + model = "Storopack SMEGW01 board"; + compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc3; + mmc2 = &usdhc2; + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_lte_on: regulator-lte-on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_on>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "lte_on"; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_lte_nreset: regulator-lte-nreset { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_nreset>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "LTE_nReset"; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + regulator-name = "wifi_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wlan_rfkill: regulator-wlan-rfkill { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-2 = <&pinctrl_rfkill>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wlan_rfkill"; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + sram@0 { + compatible = "microchip,48l640"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + i2c_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + reg = <0x52>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_lpsr>; + dr_mode = "otg"; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + sd-uhs-ddr50; + mmc-ddr-1_8v; + vmmc-supply = <®_wifi>; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + max-frequency = <200000000>; + bus-width = <8>; + fsl,tuning-step = <1>; + non-removable; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0 + >; + }; + + pinctrl_lte_on: lteongrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059 + >; + }; + + pinctrl_lte_nreset: ltenresetgrp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059 + >; + }; + + pinctrl_rfkill: rfkillrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74 + >; + }; + + pinctrl_usbotg1_lpsr: usbotg1 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04 + >; + }; + + pinctrl_usbotg1_pwr: usbotg1-pwr { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04 + >; + }; + + pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5d + MX7D_PAD_SD3_CLK__SD3_CLK 0x1d + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5e + MX7D_PAD_SD3_CLK__SD3_CLK 0x1e + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5f + MX7D_PAD_SD3_CLK__SD3_CLK 0x0f + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; From 92c996f4ceabd5780bb7678138267db0a1e1a00e Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 29 Apr 2022 16:56:38 +0530 Subject: [PATCH 698/791] arm64: dts: ti: k3-j721e-*: add DP & DP PHY Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add the required phy link nodes in the board dts files. A slight irregularity in the bindings is the DPTX PHY register block, which is in the MHDP IP, but is needed and mapped by the PHY. Signed-off-by: Tomi Valkeinen Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220429112639.13004-2-r-ravikumar@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 16 ++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 75 ++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 16 ++++ 3 files changed, 105 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index f5ca8e26ed99..2f119e94e783 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -793,6 +793,22 @@ }; }; +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = ; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; +}; + &pcie0_rc { reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index db0669985e42..43b6cf5791ee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ #include +#include #include #include @@ -789,6 +790,47 @@ #size-cells = <2>; }; + serdes_wiz4: wiz@5050000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 297 9>; + assigned-clock-parents = <&k3_clks 297 10>; + assigned-clock-rates = <19200000>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05050000 0x00 0x05050000 0x010000>, + <0x0a030a00 0x00 0x0a030a00 0x40>; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible = "ti,j721e-serdes-10g"; + reg = <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy", "dptx_phy"; + + resets = <&serdes_wiz4 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; + clock-names = "refclk"; + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 297 9>, + <&k3_clks 297 9>, + <&k3_clks 297 9>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -1267,6 +1309,37 @@ }; }; + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + /* + * Note: we do not map DPTX PHY area, as that is handled by + * the PHY driver. + */ + reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ + <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 151 36>; + + interrupt-parent = <&gic500>; + interrupts = ; + + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@4 { + reg = <4>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = @@ -1317,8 +1390,6 @@ "common_s2"; dss_ports: ports { - #address-cells = <1>; - #size-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index f25d85169e0d..98177a20b45f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -624,6 +624,22 @@ }; }; +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = ; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; +}; + &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; From 8f984f60f2f1fa109f9ae8c9194b6989f6675c1d Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 29 Apr 2022 16:56:39 +0530 Subject: [PATCH 699/791] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required pinmux nodes for hotplug. Signed-off-by: Tomi Valkeinen Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220429112639.13004-3-r-ravikumar@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 61 +++++++++++++++++-- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2f119e94e783..2bc26a296496 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -148,6 +148,28 @@ pinctrl-0 = <&main_mcan2_gpio_pins_default>; standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; }; + + dp_pwr_3v3: regulator-dp-pwr { + compatible = "regulator-fixed"; + regulator-name = "dp-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -190,6 +212,12 @@ >; }; + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ + >; + }; + main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ @@ -658,6 +686,33 @@ <&k3_clks 152 18>; /* PLL23_HSDIV0 */ }; +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + &mcasp0 { status = "disabled"; }; @@ -807,6 +862,8 @@ &mhdp { phys = <&torrent_phy_dp>; phy-names = "dpphy"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; }; &pcie0_rc { @@ -859,10 +916,6 @@ status = "disabled"; }; -&dss { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; From d4f3c8a169ab82b91ba1e10a495e900477a75cf5 Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Thu, 5 May 2022 14:37:08 +0530 Subject: [PATCH 700/791] arm64: dts: ti: k3-j721e-sk: Enable DisplayPort Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220505090709.9252-2-r-ravikumar@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 45 +++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 98177a20b45f..07b1e40fbc47 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -213,6 +213,18 @@ enable-active-high; }; + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -638,6 +650,8 @@ &mhdp { phys = <&torrent_phy_dp>; phy-names = "dpphy"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; }; &usbss0 { @@ -718,6 +732,33 @@ <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ }; +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + &mcasp0 { /* Unused */ status = "disabled"; @@ -852,10 +893,6 @@ status = "disabled"; }; -&dss { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; From 7d4686fc3c2ad9bfd1eaf3c54515d6469e542578 Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Thu, 5 May 2022 14:37:09 +0530 Subject: [PATCH 701/791] arm64: dts: ti: k3-j721e-sk: Enable HDMI Add node for dvi bridge and the endpoint nodes to describe connection from DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector. Also add the required pinmux for HDMI hotplug and powerdown Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220505090709.9252-3-r-ravikumar@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 80 +++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 07b1e40fbc47..80358cba6954 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -225,6 +225,59 @@ }; }; }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins_default>; + + ddc-i2c-bus = <&main_i2c1>; + + /* HDMI_HPD */ + hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-bridge { + compatible = "ti,tfp410"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pdn_pins_default>; + + powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; + ti,deskew = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi1_out>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = + <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_pmx0 { @@ -329,6 +382,18 @@ >; }; + hdmi_hpd_pins_default: hdmi-hpd-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ + >; + }; + + hdmi_pdn_pins_default: hdmi-pdn-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ + >; + }; + /* Reset for M.2 E Key slot on PCIe0 */ ekey_reset_pins_default: ekey-reset-pns-pins-default { pinctrl-single,pins = < @@ -733,11 +798,24 @@ }; &dss_ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi0_out: endpoint { remote-endpoint = <&dp0_in>; }; }; + + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; }; &dp0_ports { From 9583009097c8933a30110097d373a09624cb8c37 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 23 Apr 2022 02:36:11 +0530 Subject: [PATCH 702/791] arm64: dts: qcom: sm8150: Fix iommu sid value for SDC2 controller Fix the IOMMU sid value for SDC2 controller, to ensure that no ADMA error is observed when the microSD card is detected on the SA8155p-ADP board. Fixes: 876644c76034 ("arm64: dts: qcom: sm8150: Add support for SDC2") Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220422210611.173842-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2700a8145cb9..f70ae4c56762 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3555,7 +3555,7 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; - iommus = <&apps_smmu 0x4a0 0x0>; + iommus = <&apps_smmu 0x6a0 0x0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd 0>; From 11a3f3dc2cf8d6127aae6183a69dcf3dde026305 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 24 Apr 2022 01:20:03 +0530 Subject: [PATCH 703/791] arm64: dts: qcom: sa8155p-adp: Disable multiple Tx and Rx queues for ethernet IP Fix the issues seen with ethernet traffic getting stalled on SA8155p-ADP board with default (or larger) mtu size of 1500 bytes, by disabling multiple Tx and Rx queues for the stmmac IP block. With the single queue setup, the ethernet traffic is stable, wget / curl can work well on the board and no ethernet stall is observed even when longer netperf / iperf3 test are run. Also a performance of ~940 Mbits/sec is observed on the 1G link, so there is no observable degradation in performance as well. Fixes: c5cb42cc8411 ("arm64: dts: qcom: sa8155p-adp: Enable ethernet node") Cc: Bjorn Andersson Cc: Vinod Koul Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220423195003.353150-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 40 ++---------------------- 1 file changed, 2 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 8034d0d31bd0..ba547ca9fc6b 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -49,7 +49,7 @@ }; mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; + snps,rx-queues-to-use = <1>; snps,rx-sched-sp; queue0 { @@ -58,28 +58,10 @@ snps,route-up; snps,priority = <0x1>; }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; }; mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; + snps,tx-queues-to-use = <1>; snps,tx-sched-wrr; queue0 { @@ -87,24 +69,6 @@ snps,dcb-algorithm; snps,priority = <0x0>; }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; }; }; From 366a0a194b3b3e3e52bc7b7b1ac35b40a1187902 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 26 Apr 2022 12:41:03 -0700 Subject: [PATCH 704/791] arm64: dts: qcom: sc7280: eDP for herobrine boards Add eDP support to herobrine boards, splitting up amongst the different files as makes sense. Rationale for the current split of things: * The eDP connector itself is on qcard. However, not all devices with a qcard will use an eDP panel. Some might use MIPI and, presumably, someone could build a device with qcard that had no display at all. * The qcard provides a PWM for backlight that goes to the eDP connector. This PWM is also provided to the board and it's expected that it would be used as the backlight PWM even for herobrine devices with MIPI displays. * It's currently assumed that all herobrine boards will have some sort of display, either MIPI or eDP (but not both). * We will assume herobrine-rev1 has eDP. The schematics allow for a MIPI panel to be hooked up but, aside from some testing, nobody is doing this and most boards don't have all the parts stuffed for it. The two panels would also share a PWM for backlight, which is weird. * herobrine-villager and herobrine-hoglin (crd) also have eDP. * herobrine-hoglin (crd) has slightly different regulator setup for the backlight. It's expected that this is unique to this board. See comments in the dts file. * There are some regulators that are defined in the qcard schematic but provided by the board like "vreg_edp_bl" and "vreg_edp_3p3". While we could put references to these regulators straight in the qcard.dtsi file, this would force someone using qcard that didn't provide those regulators to provide a dummy or do an ugly /delete-node/. Instead, we'll add references in herobrine.dtsi. Signed-off-by: Douglas Anderson Reviewed-by: Abhinav Kumar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220426124053.v2.1.Iedd71976a78d53c301ce0134832de95a989c9195@changeid --- .../boot/dts/qcom/sc7280-herobrine-crd.dts | 40 ++++++++++++++ .../qcom/sc7280-herobrine-herobrine-r1.dts | 8 +++ .../dts/qcom/sc7280-herobrine-villager-r0.dts | 8 +++ .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 24 +++++++++ arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 54 +++++++++++++++++++ 5 files changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index b06f61e9b90b..a4ac33c4fd59 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -12,6 +12,27 @@ / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; compatible = "google,hoglin", "qcom,sc7280"; + + /* FIXED REGULATORS */ + + /* + * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL. + * However, on CRD there's an extra regulator in the way. Since this + * is expected to be uncommon, we'll leave the "vreg_edp_bl" label + * in the baseboard herobrine.dtsi point at "ppvar_sys" and then + * make a "_crd" specific version here. + */ + vreg_edp_bl_crd: vreg-edp-bl-crd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_edp_bl_crd"; + + gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + vin-supply = <&ppvar_sys>; + }; }; /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ @@ -81,6 +102,14 @@ ap_ts_pen_1v8: &i2c13 { }; }; +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + /* For nvme */ &pcie1 { status = "okay"; @@ -91,6 +120,10 @@ ap_ts_pen_1v8: &i2c13 { status = "okay"; }; +&pm8350c_pwm_backlight { + power-supply = <&vreg_edp_bl_crd>; +}; + /* For eMMC */ &sdhc_1 { status = "okay"; @@ -121,6 +154,13 @@ ap_ts_pen_1v8: &i2c13 { "PMIC_EDP_BL_EN", "PMIC_EDP_BL_PWM", ""; + + edp_bl_reg_en: edp-bl-reg-en { + pins = "gpio6"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + }; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index 29c4ca095294..b69ca09d9bfb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -100,6 +100,14 @@ ts_i2c: &i2c13 { }; }; +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + /* For nvme */ &pcie1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts index 6c2b9a14535a..d3d6ffad4eff 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts @@ -58,6 +58,14 @@ ap_tp_i2c: &i2c0 { status = "okay"; }; +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + /* For nvme */ &pcie1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index d58045dd7334..9cb1bc8ed6b5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -367,6 +367,11 @@ vreg_edp_3p3: &pp3300_left_in_mlb {}; /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ +&edp_panel { + /* Our board provides power to the qcard for the eDP panel. */ + power-supply = <&vreg_edp_3p3>; +}; + ap_sar_sensor_i2c: &i2c1 { clock-frequency = <400000>; status = "disabled"; @@ -420,6 +425,14 @@ ap_i2c_tpm: &i2c14 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + /* NVMe drive, enabled on a per-board basis */ &pcie1 { pinctrl-names = "default"; @@ -429,6 +442,17 @@ ap_i2c_tpm: &i2c14 { vddpe-3v3-supply = <&pp3300_ssd>; }; +&pm8350c_pwm { + status = "okay"; +}; + +&pm8350c_pwm_backlight { + status = "okay"; + + /* Our board provides power to the qcard for the backlight */ + power-supply = <&vreg_edp_bl>; +}; + &pmk8350_rtc { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 98b5cd70bca5..d59002d4492e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -29,6 +29,16 @@ serial0 = &uart5; serial1 = &uart7; }; + + pm8350c_pwm_backlight: backlight { + compatible = "pwm-backlight"; + status = "disabled"; + + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_edp_bl_en>; + pwms = <&pm8350c_pwm 3 65535>; + }; }; &apps_rsc { @@ -293,11 +303,50 @@ modem-init; }; +/* NOTE: Not all Qcards have eDP connector stuffed */ +&mdss_edp { + vdda-0p9-supply = <&vdd_a_edp_0_0p9>; + vdda-1p2-supply = <&vdd_a_edp_0_1p2>; + + aux-bus { + edp_panel: panel { + compatible = "edp-panel"; + + backlight = <&pm8350c_pwm_backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + edp_panel_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + }; + }; +}; + +&mdss_edp_out { + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_edp_phy { + vdda-pll-supply = <&vdd_a_edp_0_0p9>; + vdda-phy-supply = <&vdd_a_edp_0_1p2>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pm8350c_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_edp_bl_pwm>; +}; + &pmk8350_vadc { pmk8350-die-temp@3 { reg = ; @@ -383,6 +432,11 @@ mos_bt_uart: &uart7 { * baseboard or board device tree, not here. */ +/* No external pull for eDP HPD, so set the internal one. */ +&edp_hot_plug_det { + bias-pull-down; +}; + /* * For ts_i2c * From 51d30402be7506db007af6d29c6bc7c1cefcc82f Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 26 Apr 2022 19:03:37 -0700 Subject: [PATCH 705/791] arm64: dts: qcom: sc7180-trogdor: Simplify trackpad enabling Trogdor boards with a detachable keyboard don't have a trackpad over i2c. Instead the trackpad is on the detachable keyboard base. Let's move the enabling of the trackpad i2c bus out of the base sc7180-trogdor.dtsi file so that each trogdor board that is detachable, of which there are many, doesn't have to disable the trackpad bus. Cc: "Joseph S. Barrera III" Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220427020339.360855-2-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 - 6 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index c81805ef2250..8da61a52f150 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -111,10 +111,6 @@ ap_ts_pen_1v8: &i2c4 { }; }; -&i2c7 { - status = "disabled"; -}; - &i2c9 { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index bff2b556cc75..532c7dcc3f73 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -88,10 +88,6 @@ ap_h1_spi: &spi0 {}; }; }; -&ap_tp_i2c { - status = "disabled"; -}; - ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 69666f92176a..75df5d1633b2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -19,6 +19,10 @@ ap_h1_spi: &spi0 {}; semtech,avg-pos-strength = <64>; }; +&ap_tp_i2c { + status = "okay"; +}; + /* * Lazor is stuffed with a 47k NTC as charger thermistor which currently is * not supported by the PM6150 ADC driver. Disable the charger thermal zone diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index e90f99ef5323..410ca2a76d81 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -36,6 +36,10 @@ ap_h1_spi: &spi0 {}; realtek,dmic-clk-driving-high = "true"; }; +&ap_tp_i2c { + status = "okay"; +}; + &cpu6_alert0 { temperature = <60000>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 457c25499863..311c42a535ff 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -20,6 +20,10 @@ ap_h1_spi: &spi0 {}; compatible = "google,trogdor", "qcom,sc7180"; }; +&ap_tp_i2c { + status = "okay"; +}; + ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index b0efb354458c..7648be83f7e4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -727,7 +727,6 @@ ap_sar_sensor_i2c: &i2c5 { }; ap_tp_i2c: &i2c7 { - status = "okay"; clock-frequency = <400000>; trackpad: trackpad@15 { From d277cab7afc7b54ea91808c0895d78c2021af534 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 26 Apr 2022 19:03:38 -0700 Subject: [PATCH 706/791] arm64: dts: qcom: sc7180-trogdor: Simplify spi0/spi6 labeling We had to do this spi0/spi6 flip-flop on trogdor-r0 because the spi buses got swizzled between r0 and r1. The swizzle stopped after r1, but we kept this around to support either hardware possibility and to keep trogdor-r0 working. trogdor-r0 isn't supported upstream, so this swizzle is not doing anything besides making a pattern that others tryt to copy for the EC and H1 nodes. Let's remove it and simplify the dts files. Cc: "Joseph S. Barrera III" Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220427020339.360855-3-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 6 +----- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 3 --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 3 --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++-- 6 files changed, 3 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 8da61a52f150..ac2279142a95 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -6,14 +6,10 @@ */ #include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" -/* Deleted nodes from trogdor.dtsi */ +/* Deleted nodes from sc7180-trogdor.dtsi */ /delete-node/ &alc5682; /delete-node/ &pp3300_codec; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 532c7dcc3f73..9b3e3d13c165 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -5,9 +5,6 @@ * Copyright 2021 Google LLC. */ -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 75df5d1633b2..fe2369c29aad 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,9 +5,6 @@ * Copyright 2020 Google LLC. */ -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" &ap_sar_sensor { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 410ca2a76d81..3bca7545ffe5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -6,10 +6,6 @@ */ #include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 311c42a535ff..6c822c84112a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -8,10 +8,6 @@ /dts-v1/; #include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 7648be83f7e4..ea5bedc3d1cb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -626,7 +626,7 @@ }; }; -&ap_ec_spi { +ap_ec_spi: &spi6 { status = "okay"; cros_ec: ec@0 { compatible = "google,cros-ec-spi"; @@ -675,7 +675,7 @@ }; }; -&ap_h1_spi { +ap_h1_spi: &spi0 { status = "okay"; cr50: tpm@0 { compatible = "google,cr50"; From 19794489fa2474a55c00848e00ca3d15ea01d36c Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 26 Apr 2022 19:03:39 -0700 Subject: [PATCH 707/791] arm64: dts: qcom: Only include sc7180.dtsi in sc7180-trogdor.dtsi The SoC is always present on sc7180-trogdor.dtsi and thus we should include it in the "generic" dtsi file for trogdor. Previously we had removed it from there because we had to do the spi6/spi0 swizzle, so each trogdor variant board had to include sc7180.dtsi and then sc7180-trogdor.dtsi so that the latter dtsi file could modify the right spi bus for EC and H1 properties that are common to all trogdor boards. Now that we're done with that we can replace sc7180.dtsi includes with sc7180-trogdor.dtsi and include sc7180.dtsi in sc7180-trogdor.dtsi as was originally intended. We still need to include sc7180-trogdor.dtsi before the bridge dtsi files though because those rely on the panel label. Cc: "Joseph S. Barrera III" Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220427020339.360855-4-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts | 2 +- .../boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts | 2 +- .../boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 ++- 19 files changed, 17 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index ac2279142a95..8ac1f1e61006 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -5,7 +5,6 @@ * Copyright 2020 Google LLC. */ -#include "sc7180.dtsi" #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts index 70032983fb65..d9e905ed4e62 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts index e92e2e9e48ed..242c178fdc52 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts index 0de0c97f5728..66dd87016201 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-homestar.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts index f360ff27226e..235cda2bba5e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts index c44ed54af690..913b5fc3ba76 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts index 42b4bbcc76f4..d42dcd421146 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts index dc47842bc662..15d77dc5f956 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index b142006478ea..bfbf26fd2cd4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index 59740799fa3a..d45a59afd7fc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts index 18ef9da71998..6ff81c1f7c44 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index 8913592b2d82..e58e36e35950 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts index 7adcedbf080d..76c83f88cb41 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts index 7f5c015e1ecb..960f7b7ce094 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts index 8107f3d932eb..38027f13b9d0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts index 83f6a4eb5ae5..56dd222650d3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 3bca7545ffe5..4841d42c8c62 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -5,7 +5,6 @@ * Copyright 2020 Google LLC. */ -#include "sc7180.dtsi" #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 6c822c84112a..352827e5740a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -7,7 +7,6 @@ /dts-v1/; -#include "sc7180.dtsi" #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index ea5bedc3d1cb..e55dbaa6dc12 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -11,7 +11,8 @@ #include #include -/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "sc7180.dtsi" +/* PMICs depend on spmi_bus label and so must come after sc7180.dtsi */ #include "pm6150.dtsi" #include "pm6150l.dtsi" From 987da486d84a5643fb0e027fe4fc4dfcb54206a0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 28 Apr 2022 22:50:57 +0900 Subject: [PATCH 708/791] arm64: dts: renesas: Add Renesas R8A779G0 SoC support Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220428135058.597586-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi new file mode 100644 index 000000000000..7cbb0de060dd --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G0) SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779g0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779g0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779g0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779g0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; From e4d755cfec44197f605e1a2e9ff17434c6c9d513 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 28 Apr 2022 22:50:58 +0900 Subject: [PATCH 709/791] arm64: dts: renesas: Add Renesas White Hawk boards support Initial support for the Renesas White Hawk CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220428135058.597586-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 45 +++++++++++++++++++ .../boot/dts/renesas/r8a779g0-white-hawk.dts | 22 +++++++++ 3 files changed, 69 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index fa9811251fd7..15309309a2e1 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb + dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi new file mode 100644 index 000000000000..ea4ae4b893ab --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk CPU board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "r8a779g0.dtsi" + +/ { + model = "Renesas White Hawk CPU board"; + compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts new file mode 100644 index 000000000000..bc0ac109b17c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk CPU and BreakOut boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779g0-white-hawk-cpu.dtsi" + +/ { + model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; + compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; + + aliases { + serial0 = &hscif0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; From c62af12c700dc435b82df207e49dac3f91ece6c6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 Apr 2022 08:23:58 +0100 Subject: [PATCH 710/791] arm64: dts: renesas: rzg2l-smarc: Move ssi0 and cpu sound_dai nodes from common dtsi On RZ/G2{L,LC} SoM module, the wm8978 audio codec is connected to ssi0, whereas on RZ/G2UL it is connected to ssi1. So move ssi0 and cpu sound_dai nodes from common dtsi to board specific dtsi. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220429072400.23729-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 8 -------- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 11 +++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 11 +++++++++++ 4 files changed, 22 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index df27b63f0465..52ee1640c3c1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -54,12 +54,6 @@ status = "disabled"; }; -&ssi0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &usb2_phy0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 0e61b85efb43..3962d47b3e59 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -52,7 +52,6 @@ "Mic Bias", "Microphone Jack"; cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi0>; }; codec_dai: simple-audio-card,codec { @@ -168,13 +167,6 @@ status = "okay"; }; -&ssi0 { - pinctrl-0 = <&ssi0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index aadc41515093..e180a955b6ac 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -18,6 +18,10 @@ }; }; +&cpu_dai { + sound-dai = <&ssi0>; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; @@ -49,6 +53,13 @@ }; #endif +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &vccq_sdhi1 { gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 74a844ea7537..aa170492dd2b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -60,6 +60,10 @@ }; #endif +&cpu_dai { + sound-dai = <&ssi0>; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -91,6 +95,13 @@ }; #endif +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + #if (SW_RSPI_CAN) &spi1 { /delete-property/ pinctrl-0; From 1ed914e341392dbb7c29f0f62c105a81cce6b3e0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 Apr 2022 08:23:59 +0100 Subject: [PATCH 711/791] arm64: dts: renesas: rzg2ul-smarc: Enable Audio Enable Audio on RZ/G2UL SMARC EVK by adding ssi1 pincontrol entries to the soc-pinctrl dtsi and ssi1 and cpu sound_dai nodes to the board dtsi. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220429072400.23729-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 7 ++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 23 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 17527184ff2a..201b70150e01 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -98,4 +98,11 @@ pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; }; + + ssi1_pins: ssi1 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index d75ad79ba804..0051634d7b1c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -27,6 +27,10 @@ }; #endif +&cpu_dai { + sound-dai = <&ssi1>; +}; + &i2c1 { wm8978: codec@1a { compatible = "wlf,wm8978"; @@ -35,6 +39,25 @@ }; }; +#if (SW_ET0_EN_N) +&ssi1 { + pinctrl-0 = <&ssi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#else +&snd_rzg2l { + status = "disabled"; +}; + +&ssi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + &vccq_sdhi1 { gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; }; From 094ff3485a05cd29db083a6e2905e87b68f13538 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 Apr 2022 08:24:00 +0100 Subject: [PATCH 712/791] arm64: dts: renesas: rzg2ul-smarc: Enable USB2.0 support Enable USB2.0 Host/Device support on RZ/G2UL SMARC EVK by adding usb{0,1} pincontrol entries to the soc-pinctrl dtsi and deleting the nodes which disabled it. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220429072400.23729-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a07g043u11-smarc.dts | 46 ------------------- .../dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 11 +++++ 2 files changed, 11 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 52ee1640c3c1..2d740bd420ca 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -14,54 +14,8 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; }; -&ehci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ehci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&hsusb { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&phyrst { - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; status = "disabled"; }; - -&usb2_phy0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&usb2_phy1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 201b70150e01..bd8bc858c28c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -105,4 +105,15 @@ , /* TXD */ ; /* RXD */ }; + + usb0_pins: usb0 { + pinmux = , /* VBUS */ + , /* OVC */ + ; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = , /* OVC */ + ; /* VBUS */ + }; }; From b7423e39432c00de8ba8ebefce3849aa502208d1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 24 Apr 2022 19:12:27 +0300 Subject: [PATCH 713/791] arm64: dts: renesas: Remove empty lvds endpoints Endpoints node must have a remote-endpoint property, as endpoints only exist to model a link between ports. Drop the empty lvds endpoints from SoC dtsi files, they should be instead declared in the board dts or in overlays. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/20220424161228.8147-1-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ---- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 4 ---- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 4 ---- 12 files changed, 30 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index faf5bbbb3710..d99ed3d47427 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2776,8 +2776,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index be998bc40412..69ab6e66bb98 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2621,8 +2621,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 4f69f90d88cb..514a095ac3a3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1914,8 +1914,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -1941,8 +1939,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 989c1c00dcdc..aefed8e0037f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2895,8 +2895,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 884210544ba0..d3cd275b20cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -3395,8 +3395,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 0d96b5bb9584..da4904325c4a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2992,8 +2992,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 58e161e5dae0..9a46bdeb8993 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2802,8 +2802,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index ecca9582edf6..0d6d8cb9a409 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2804,8 +2804,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 79718234d85f..6d9e69895cae 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1191,8 +1191,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 148983130adf..46d5567799b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1569,8 +1569,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 5d41e46d06f5..12440f12c83d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -2091,8 +2091,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -2118,8 +2116,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 0eccf81db374..2c0441718d39 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1410,8 +1410,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -1437,8 +1435,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; From 747bbcd3aacd95fe200cdda415dba02e872946b5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 24 Apr 2022 19:12:28 +0300 Subject: [PATCH 714/791] arm64: dts: renesas: Remove empty rgb output endpoints Endpoints node must have a remote-endpoint property, as endpoints only exist to model a link between ports. Drop the empty rgb output endpoints from SoC dtsi files, and declare them in the board dts instead. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/20220424161228.8147-2-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/beacon-renesom-baseboard.dtsi | 10 ++++++++-- arch/arm64/boot/dts/renesas/draak.dtsi | 2 +- arch/arm64/boot/dts/renesas/ebisu.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 2 +- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 -- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 10 ++++++++-- 18 files changed, 20 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 5ad6cd1864c1..142e7ffbd2bd 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -272,8 +272,14 @@ status = "okay"; }; -&du_out_rgb { - remote-endpoint = <&rgb_panel>; +&du { + ports { + port@0 { + du_out_rgb: endpoint { + remote-endpoint = <&rgb_panel>; + }; + }; + }; }; &ehci0 { diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 2a784ee6da49..7231f820d601 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -285,7 +285,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index ae688707f8c6..72f359efa23e 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -356,7 +356,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index d99ed3d47427..bdf23c17f049 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2738,8 +2738,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 69ab6e66bb98..156ccc541358 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2583,8 +2583,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 4e72e4f2bab0..5a6ea08ffd2b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -172,7 +172,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&tda19988_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 514a095ac3a3..9da3e739a729 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1871,8 +1871,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index aefed8e0037f..e20e3e135229 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2857,8 +2857,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index d3cd275b20cd..b0063f58990f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -3351,8 +3351,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index da4904325c4a..ef1d86023155 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2954,8 +2954,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 9a46bdeb8993..aa666b17b827 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2764,8 +2764,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 0d6d8cb9a409..02b1cbb61b85 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2766,8 +2766,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 6d9e69895cae..1891b3bc8cc5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1157,8 +1157,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 46d5567799b8..b56120fffaf0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1534,8 +1534,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 12440f12c83d..44d6f6032de7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -2048,8 +2048,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 2c0441718d39..9c181e0cb6c0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1367,8 +1367,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 7ad72f377a35..31837fcd7bf0 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -386,7 +386,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index ae532cd21708..5bcb84403ef6 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -97,8 +97,14 @@ status = "okay"; }; -&du_out_rgb { - remote-endpoint = <&adv7513_in>; +&du { + ports { + port@0 { + du_out_rgb: endpoint { + remote-endpoint = <&adv7513_in>; + }; + }; + }; }; &ehci0 { From 257d24b3589ba745e5709f180667c6b27e5442aa Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 27 Apr 2022 11:56:52 +0200 Subject: [PATCH 715/791] ARM: dts: r9a06g032: Add the two DMA nodes Describe the two DMA controllers available on this SoC. Signed-off-by: Miquel Raynal Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20220427095653.91804-9-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index cd9dc815089f..74d583927b86 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -201,6 +201,34 @@ status = "disabled"; }; + dma0: dma-controller@40104000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40104000 0x1000>; + interrupts = ; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + + dma1: dma-controller@40105000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40105000 0x1000>; + interrupts = ; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA1>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; From 6002e2f179ec65e97e880b21e919e71852d95204 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 27 Apr 2022 11:56:53 +0200 Subject: [PATCH 716/791] ARM: dts: r9a06g032: Describe the DMA router There is a dmamux on this SoC which allows picking two different sources for a single DMA request. Signed-off-by: Miquel Raynal Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20220427095653.91804-10-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 74d583927b86..a84efde210d2 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -92,6 +92,16 @@ clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, <&ext_rgmii_ref>; clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + #address-cells = <1>; + #size-cells = <1>; + + dmamux: dma-router@a0 { + compatible = "renesas,rzn1-dmamux"; + reg = <0xa0 4>; + #dma-cells = <6>; + dma-requests = <32>; + dma-masters = <&dma0 &dma1>; + }; }; uart0: serial@40060000 { From f691d4b64c19176099c58811b0e1240259a1d258 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 21 Apr 2022 11:53:21 +0200 Subject: [PATCH 717/791] ARM: dts: r9a06g032: Fill the UART DMA properties UART 0 to 2 do not have DMA support, while UART 3 to 7 do. Fill the "dmas" and "dma-names" properties for each of these nodes. Please mind that these nodes go through the dmamux node which will redirect the requests to the right DMA controller. The first 4 cells of the "dmas" properties will be transferred as-is to the DMA controllers. The last 2 cells are consumed by the dmamux. Which means cell 0 and 4 are almost redundant, one giving the controller request ID and the other the dmamux channel which is a 1:1 translation of the request IDs, shifted by 16 when pointing to the second DMA controller. Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/r/20220421095323.101811-11-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index a84efde210d2..6b6944b943f8 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -145,6 +145,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -156,6 +158,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -167,6 +171,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -178,6 +184,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -189,6 +197,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; + dma-names = "rx", "tx"; status = "disabled"; }; From d5379f9c7f2230d6af6bc0f7d0587cca4689ddc7 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 29 Apr 2022 12:52:28 +0200 Subject: [PATCH 718/791] ARM: dts: r9a06g032: Fix the NAND controller node Add the missing power-domains property which is mandatory. Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/r/20220429105229.368728-3-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 6b6944b943f8..50fc2e04877e 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -216,6 +216,7 @@ interrupts = ; clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; clock-names = "hclk", "eclk"; + power-domains = <&sysctrl>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 1404ca90f49be530551e26b8bc6dfe2142aba86e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 Apr 2022 14:31:55 +0100 Subject: [PATCH 719/791] arm64: dts: renesas: r9a07g044: Fix external clk node names Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220428133156.18080-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 19287cccb1f0..3652e511160f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -13,14 +13,14 @@ #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio_clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio_clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ @@ -28,14 +28,14 @@ }; /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { + can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal { + extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ From 975253505429bc60d1b400296728fffb416aa1ff Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 Apr 2022 14:31:56 +0100 Subject: [PATCH 720/791] arm64: dts: renesas: r9a07g054: Fix external clk node names Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220428133156.18080-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index f35aa0311e9c..4d6b9d7684c9 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -13,14 +13,14 @@ #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio_clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio_clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ @@ -28,14 +28,14 @@ }; /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { + can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal { + extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ From 22ec868997108e514fe380171c45578da630a0ec Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:22 +0100 Subject: [PATCH 721/791] arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 47 ++++++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 15335e9ca06b..82fe61991204 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -158,11 +158,52 @@ status = "disabled"; }; - spi1: spi@1004b000 { - reg = <0 0x1004b000 0 0x400>; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; + resets = <&cpg R9A07G043_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + spi1: spi@1004b000 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; + resets = <&cpg R9A07G043_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; + resets = <&cpg R9A07G043_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; scif0: serial@1004b800 { From e6a9acc370c6cb9e6ff6225b034a7a4374df0134 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:23 +0100 Subject: [PATCH 722/791] arm64: dts: renesas: r9a07g043: Add OPP table Add OPP table for RZ/G2UL SoC. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 82fe61991204..e2300d5c6a15 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -53,6 +80,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From 91e548da2cb1b180a1ab1059a1c89d7532135da7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:24 +0100 Subject: [PATCH 723/791] arm64: dts: renesas: r9a07g043: Add TSU node Add TSU node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index e2300d5c6a15..cd7d30797eee 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -486,6 +486,16 @@ /* place holder */ }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g043-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; + resets = <&cpg R9A07G043_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, @@ -826,6 +836,22 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, From c2ff5c0282f94c1f1f81007e1fa7378fe95f46d3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:25 +0100 Subject: [PATCH 724/791] arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham and others for r8a77990 SoC. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index cd7d30797eee..9048edb5e2b1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -77,6 +77,7 @@ compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; + #cooling-cells = <2>; next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; @@ -841,6 +842,15 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; trips { sensor_crit: sensor-crit { @@ -848,6 +858,12 @@ hysteresis = <1000>; type = "critical"; }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; }; From 470218e29daf7f1de9f4d1af16c7ecf54344f6a1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 2 May 2022 20:01:55 +0100 Subject: [PATCH 725/791] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220502190155.84496-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 9048edb5e2b1..b31fb713ae4d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -498,12 +498,19 @@ }; sbc: spi@10060000 { + compatible = "renesas,r9a07g043-rpc-if", + "renesas,rzg2l-rpc-if"; reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, + <&cpg CPG_MOD R9A07G043_SPI_CLK>; + resets = <&cpg R9A07G043_SPI_RST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; }; cpg: clock-controller@11010000 { From 6af663af3c46300032fd7a783bdc3e585035438f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 19:33:52 +0200 Subject: [PATCH 726/791] arm64: dts: renesas: Add interrupt-names to CANFD nodes The Renesas R-Car CAN-FD Controller on R-Car Gen3 and RZ/G2 SoCs has two interrupts. Add interrupt-names properties to all CAN-FD device nodes to identify the individual interrupts, so we can make this property a required property in the DT bindings. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/10eef1e20372af4a156b06df8e5124666ec7c6b6.1651512451.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77951.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + 12 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index bdf23c17f049..e7d17776624d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1179,6 +1179,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774A1_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 156ccc541358..f62d95760e82 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1052,6 +1052,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774B1_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 9da3e739a729..b6aeb22e8836 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1009,6 +1009,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774C0_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e20e3e135229..8ec59094882b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1280,6 +1280,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774E1_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index b0063f58990f..a297af22a195 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1368,6 +1368,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A7795_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ef1d86023155..4159c23d3874 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1240,6 +1240,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A7796_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index aa666b17b827..3c744b7d0dc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1229,6 +1229,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77961_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 02b1cbb61b85..21a5e1cdd9f1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1103,6 +1103,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77965_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1891b3bc8cc5..2703ef3a38c2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -557,6 +557,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77970_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index b56120fffaf0..8594be72f221 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -609,6 +609,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77980_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 44d6f6032de7..d33021202637 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1052,6 +1052,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77990_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 9c181e0cb6c0..f040d03e0a87 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -557,6 +557,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77995_CLK_CANFD>, <&can_clk>; From d8ff11cdc0b153bfebf103716cb1e3f6a26029ed Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 29 Apr 2022 12:46:02 +0200 Subject: [PATCH 727/791] ARM: dts: r9a06g032: Describe the RTC Describe the SoC RTC which counts time and provides alarm support. Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/r/20220429104602.368055-7-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 50fc2e04877e..2d5756935d98 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -66,6 +66,19 @@ interrupt-parent = <&gic>; ranges; + rtc0: rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = , + , + ; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + wdt0: watchdog@40008000 { compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; reg = <0x40008000 0x1000>; From 627632dcc2dd2e9a09a1bafb2e5fcf53cd4c968a Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Fri, 29 Apr 2022 15:41:41 +0200 Subject: [PATCH 728/791] ARM: dts: r9a06g032: Add internal PCI bridge node Add the device node for the r9a06g032 internal PCI bridge device. Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20220429134143.628428-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 2d5756935d98..a72c58efdd78 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -117,6 +117,35 @@ }; }; + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclkh", "hclkpm", "pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; + uart0: serial@40060000 { compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; reg = <0x40060000 0x400>; From 47f02f883883d6e318a06cb7c05c8a7bed2c17ce Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Fri, 29 Apr 2022 15:41:42 +0200 Subject: [PATCH 729/791] ARM: dts: r9a06g032: Add USB PHY DT support Define the r9a06g032 generic part of the USB PHY device node. Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20220429134143.628428-7-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index a72c58efdd78..b94a4a36c41b 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -316,4 +316,10 @@ , ; }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; }; From fcb3083968df0addf6fb0b452d6e29be756ea943 Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Fri, 29 Apr 2022 15:41:43 +0200 Subject: [PATCH 730/791] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Describe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device. Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20220429134143.628428-8-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index b94a4a36c41b..d3665910958b 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -144,6 +144,18 @@ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; }; uart0: serial@40060000 { From a1721bbbdb5c6687d157f8b8714bba837f6028ac Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 15:35:17 +0200 Subject: [PATCH 731/791] arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4 instead of R-Car Gen3: - DMAC, - (H)SCIF, - I2C, - IPMMU, - WDT. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/73cea9d5e1a6639422c67e4df4285042e31c9fd5.1651497071.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 74 ++++++++++++++--------- 1 file changed, 44 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 57d49d27cdca..b9731504b7cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -86,7 +86,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a779a0-wdt", - "renesas,rcar-gen3-wdt"; + "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; interrupts = ; clocks = <&cpg CPG_MOD 907>; @@ -430,7 +430,7 @@ i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6500000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 518>; @@ -446,7 +446,7 @@ i2c1: i2c@e6508000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 519>; @@ -462,7 +462,7 @@ i2c2: i2c@e6510000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6510000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 520>; @@ -478,7 +478,7 @@ i2c3: i2c@e66d0000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66d0000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 521>; @@ -494,7 +494,7 @@ i2c4: i2c@e66d8000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66d8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 522>; @@ -510,7 +510,7 @@ i2c5: i2c@e66e0000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66e0000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 523>; @@ -526,7 +526,7 @@ i2c6: i2c@e66e8000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66e8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 524>; @@ -542,7 +542,7 @@ hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6540000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 514>, @@ -558,7 +558,7 @@ hscif1: serial@e6550000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 515>, @@ -574,7 +574,7 @@ hscif2: serial@e6560000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6560000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 516>, @@ -590,7 +590,7 @@ hscif3: serial@e66a0000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe66a0000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 517>, @@ -943,7 +943,7 @@ scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 702>, @@ -959,7 +959,7 @@ scif1: serial@e6e68000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 703>, @@ -975,7 +975,7 @@ scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c50000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 704>, @@ -991,7 +991,7 @@ scif4: serial@e6c40000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c40000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 705>, @@ -2003,7 +2003,8 @@ }; dmac1: dma-controller@e7350000 { - compatible = "renesas,dmac-r8a779a0"; + compatible = "renesas,dmac-r8a779a0", + "renesas,rcar-gen4-dmac"; reg = <0 0xe7350000 0 0x1000>, <0 0xe7300000 0 0x10000>; interrupts = , @@ -2037,7 +2038,8 @@ }; dmac2: dma-controller@e7351000 { - compatible = "renesas,dmac-r8a779a0"; + compatible = "renesas,dmac-r8a779a0", + "renesas,rcar-gen4-dmac"; reg = <0 0xe7351000 0 0x1000>, <0 0xe7310000 0 0x10000>; interrupts = , @@ -2092,7 +2094,8 @@ }; ipmmu_rt0: iommu@ee480000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee480000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 10>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2100,7 +2103,8 @@ }; ipmmu_rt1: iommu@ee4c0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee4c0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 19>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2108,7 +2112,8 @@ }; ipmmu_ds0: iommu@eed00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2116,7 +2121,8 @@ }; ipmmu_ds1: iommu@eed40000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed40000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2124,7 +2130,8 @@ }; ipmmu_ir: iommu@eed80000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed80000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 3>; power-domains = <&sysc R8A779A0_PD_A3IR>; @@ -2132,7 +2139,8 @@ }; ipmmu_vc0: iommu@eedc0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeedc0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 12>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2140,7 +2148,8 @@ }; ipmmu_vi0: iommu@eee80000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee80000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 14>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2148,7 +2157,8 @@ }; ipmmu_vi1: iommu@eeec0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeeec0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 15>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2156,7 +2166,8 @@ }; ipmmu_3dg: iommu@eee00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 6>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2164,7 +2175,8 @@ }; ipmmu_vip0: iommu@eef00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 5>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2172,7 +2184,8 @@ }; ipmmu_vip1: iommu@eef40000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef40000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 11>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2180,7 +2193,8 @@ }; ipmmu_mm: iommu@eefc0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeefc0000 0 0x20000>; interrupts = , ; From fb1929b98f2e1c012b4df596b7b2c9f6f28fbe54 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 4 May 2022 10:44:56 +0100 Subject: [PATCH 732/791] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220504094456.24386-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi new file mode 100644 index 000000000000..27810f4ad4cb --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g011"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0>; + device_type = "cpu"; + clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@82000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x82010000 0 0x1000>, + <0x0 0x82020000 0 0x20000>, + <0x0 0x82040000 0 0x20000>, + <0x0 0x82060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; + clock-names = "clk"; + }; + + cpg: clock-controller@a3500000 { + compatible = "renesas,r9a09g011-cpg"; + reg = <0 0xa3500000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + uart0: serial@a4040000 { + compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; + reg = <0 0xa4040000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, + <&cpg CPG_MOD R9A09G011_URT_PCLK>; + clock-names = "sclk", "pclk"; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; From ad1bd2bf658062c6edc5ff1ee1725565a4fc8930 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:57 +0100 Subject: [PATCH 733/791] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK Add basic support for RZ/V2M EVK (based on R9A09G011): - memory - External input clock - UART Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-13-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 44 +++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 15309309a2e1..e66d76d42e52 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -83,3 +83,5 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb + +dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts new file mode 100644 index 000000000000..c207d8ce5523 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g011.dtsi" + +/ { + model = "RZ/V2M Evaluation Kit 2.0"; + compatible = "renesas,rzv2mevk2", "renesas,r9a09g011"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@58000000 { + device_type = "memory"; + /* + * first 1.25GiB is reserved for ISP Firmware, + * next 128MiB is reserved for secure area. + */ + reg = <0x0 0x58000000 0x0 0x28000000>; + }; + + memory@180000000 { + device_type = "memory"; + reg = <0x1 0x80000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; From 1c4f01be3490263b73755ed24a229a5885d9ce8e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Tue, 11 Jan 2022 16:54:14 -0500 Subject: [PATCH 734/791] ARM: dts: imx: Add i.MXRT1050-EVK support The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MXRT, which features NXP's implementation of the Arm Cortex-M7 core. The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket, USB 2.0 OTG. This patch aims to support the preliminary booting up features as follows: GPIO LPUART SD/MMC Signed-off-by: Giulio Benetti Signed-off-by: Jesse Taube [Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl] Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imxrt1050-evk.dts | 72 +++++++++++++ arch/arm/boot/dts/imxrt1050.dtsi | 160 ++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0ad8339e07d8..b4ac94e3c9ed 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -751,6 +751,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_IMXRT) += \ + imxrt1050-evk.dtb dtb-$(CONFIG_SOC_LAN966) += \ lan966x-pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) += \ diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts new file mode 100644 index 000000000000..6a9c10decf52 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050-evk.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +/dts-v1/; +#include "imxrt1050.dtsi" +#include "imxrt1050-pinfunc.h" + +/ { + model = "NXP IMXRT1050-evk board"; + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x2000000>; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi new file mode 100644 index 000000000000..77b911b06041 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include "armv7-m.dtsi" +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + osc3M: osc3M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + }; + + soc { + lpuart1: serial@40184000 { + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x40184000 0x4000>; + interrupts = <20>; + clocks = <&clks IMXRT1050_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: pinctrl@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + anatop: anatop@400d8000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x400d8000 0x4000>; + }; + + clks: clock-controller@400fc000 { + compatible = "fsl,imxrt1050-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <95>, <96>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL2_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, + <&clks IMXRT1050_CLK_PLL1_ARM>, + <&clks IMXRT1050_CLK_PLL2_SYS>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL2_SYS>; + }; + + edma1: dma-controller@400e8000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x400e8000 0x4000>, + <0x400ec000 0x4000>; + dma-channels = <32>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMXRT1050_CLK_DMA>, + <&clks IMXRT1050_CLK_DMA_MUX>; + }; + + usdhc1: mmc@402c0000 { + compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x402c0000 0x4000>; + interrupts = <110>; + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, + <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,wp-controller; + no-1-8-v; + max-frequency = <4000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + gpio1: gpio@401b8000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <80>, <81>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <82>, <83>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <84>, <85>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@401c4000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c4000 0x4000>; + interrupts = <86>, <87>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = <88>, <89>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt: timer@401ec000 { + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc3M>; + clock-names = "per"; + }; + }; +}; From 6192cf8ac0824a87c4dac0e94ae94062a0edc811 Mon Sep 17 00:00:00 2001 From: Philip Oberfichtner Date: Fri, 6 May 2022 07:59:49 +0200 Subject: [PATCH 735/791] ARM: dts: Add bosch acc board Add device tree for the Bosch ACC board, based on i.MX6 Dual. Signed-off-by: Philip Oberfichtner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-bosch-acc.dts | 779 ++++++++++++++++++++++++++ 2 files changed, 780 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-bosch-acc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b4ac94e3c9ed..b711d4423b42 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -549,6 +549,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-b450v3.dtb \ imx6q-b650v3.dtb \ imx6q-b850v3.dtb \ + imx6q-bosch-acc.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-cubox-i-emmc-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6q-bosch-acc.dts new file mode 100644 index 000000000000..8768222e183e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-bosch-acc.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker + * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner + */ + +/dts-v1/; + +#include +#include +#include "imx6q.dtsi" + +/ { + model = "Bosch ACC"; + compatible = "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc4; + mmc1 = &usdhc2; + serial0 = &uart2; + serial1 = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 200000>; + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; + num-interpolated-steps = <10>; + default-brightness-level = <60>; + power-supply = <®_lcd>; + }; + + panel { + compatible = "dataimage,fg1001l0dsswmg01"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + refclk: refclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "12mhz_refclk"; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <0>, <12000000>, <0>; + }; + + cpus { + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led_red: led-0 { + color = ; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm2 0 500000>; + }; + + led_white: led-1 { + color = ; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm3 0 500000>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_gpio_led>; + + led-2 { + color = ; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_5p0: regulator-5p0 { + compatible = "regulator-fixed"; + regulator-name = "5p0"; + }; + + reg_vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_h2_vbus: regulator-usb-h2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5p0> ; + regulator-always-on; + }; + + reg_vsnvs: regulator-vsnvs { + compatible = "regulator-fixed"; + regulator-name = "VSNVS_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_enable>; + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_dac: regulator-dac { + compatible = "regulator-fixed"; + regulator-name = "vref_dac"; + regulator-min-microvolt = <20000>; + regulator-max-microvolt = <20000>; + vin-supply = <®_5p0> ; + regulator-boot-on; + }; + + reg_sw4: regulator-sw4 { + compatible = "regulator-fixed"; + regulator-name = "SW4_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_sys: regulator-sys { + compatible = "regulator-fixed"; + regulator-name = "SYS_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; +}; + +®_arm { + vin-supply = <&sw2_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +®_vdd1p1 { + vin-supply = <®_vsnvs>; +}; + +®_vdd2p5 { + vin-supply = <®_vsnvs>; +}; + +®_vdd3p0 { + vin-supply = <®_vsnvs>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + phy-mode = "rmii"; + phy-supply = <®_sw4>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpu_vg { + status = "disabled"; +}; + +&gpu_2d { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1c_reg: sw1c { + regulator-name = "VDD_SOC (sw1abc)"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-name = "VDD_ARM (sw2)"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + sw3b_reg: sw3b { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + sw4_reg: sw4 { + regulator-name = "AUX 3V15 (sw4)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + lm75: sensor@49 { + compatible = "national,lm75b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm75>; + reg = <0x49>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@51 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + eeprom_ext: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + usb3503: usb@8 { + compatible = "smsc,usb3503"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503>; + reg = <0x08>; + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + refclk-frequency = <12000000>; + }; + + exc3000: touchscreen@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctouch>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; + + vcnl4035: light-sensor@60 { + compatible = "vishay,vcnl4035"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_proximity>; + reg = <0x60>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + vbus-supply = <®_usb_h2_vbus>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphynop1 { + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + vcc-supply = <®_usb_h1_vbus>; +}; + +&usbphynop2 { + vcc-supply = <®_usb_h2_vbus>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + timeout-sec=<10>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_reset_gpio_led: reset-gpio-led-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd_enable: lcdenablegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: usb3503-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; From 75f9d540862a392395f41a5aa437a7fc2d059c23 Mon Sep 17 00:00:00 2001 From: Philip Oberfichtner Date: Fri, 6 May 2022 07:59:47 +0200 Subject: [PATCH 736/791] dt-bindings: arm: Add bosch acc board Add device tree binding for the Bosch ACC board, based on i.MX6 Dual. Signed-off-by: Philip Oberfichtner Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0bf43346d232..ef524378d449 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -192,6 +192,7 @@ properties: items: - enum: - auvidea,h100 # Auvidea H100 + - bosch,imx6q-acc # Bosch ACC i.MX6 Dual - boundary,imx6q-nitrogen6_max - boundary,imx6q-nitrogen6_som2 - boundary,imx6q-nitrogen6x From 3f781d5c67f7f5763913cccb972598df19f80c06 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 6 May 2022 15:24:04 +0200 Subject: [PATCH 737/791] ARM: dts: imx6ull-colibri: use pull-down for adc pins Disable the keeper and enable a 100k pull-down on the ADC pins as per the following note in section 13.2 of the i.MX 6ULL Application Processor Reference Manual, Rev. 1, 11/2017 [1]: The keeper causes an undesired jump behavior in ADC. To avoid the problem, disable keeper before starting ADC. [1] https://www.nxp.com/webapp/Download?colCode=IMX6ULLRM Signed-off-by: Philippe Schenker Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 7f35a06dff95..84bb7574d211 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -52,6 +52,8 @@ &adc1 { num-channels = <10>; vref-supply = <®_module_3v3_avdd>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; }; &can1 { @@ -214,6 +216,16 @@ }; &iomuxc { + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ + >; + }; + pinctrl_can_int: canint-grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ From 5516144425e413f0efe92b249142b4db15ff7ec5 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Fri, 6 May 2022 15:24:05 +0200 Subject: [PATCH 738/791] ARM: dts: imx6ull-colibri: change touch i2c parameters Switch on 22 kOhm pull-ups and lower the I2C frequency to around 40 kHz to get more reliable communication. Signed-off-by: Max Krummenacher Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 84bb7574d211..dc947035495b 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -114,6 +114,8 @@ }; &i2c2 { + /* Use low frequency to compensate for the high pull-up values. */ + clock-frequency = <40000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; @@ -405,15 +407,15 @@ pinctrl_i2c2: i2c2-grp { fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 >; }; pinctrl_i2c2_gpio: i2c2-gpio-grp { fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 >; }; From 5f9a2cedfaf3206b64a4d6b287357ae4037ed4a9 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 6 May 2022 15:24:06 +0200 Subject: [PATCH 739/791] ARM: dts: imx6ull-colibri: add phy-supply to fec This adds the proper phy-supply to the FEC. This supply is actually switched by a clock that is now properly stated. This has the advantage to add a delay for that particular regulator which is needed. Signed-off-by: Philippe Schenker Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index dc947035495b..7cd912df5d19 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -47,6 +47,18 @@ states = <1800000 0x1 3300000 0x0>; vin-supply = <®_module_3v3>; }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed-clock"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + startup-delay-us = <150000>; + }; }; &adc1 { @@ -81,6 +93,7 @@ pinctrl-1 = <&pinctrl_enet2_sleep>; phy-mode = "rmii"; phy-handle = <ðphy1>; + phy-supply = <®_eth_phy>; status = "okay"; mdio { From 2aa9d6201949b07dca7951710ef3be995600216c Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:07 +0200 Subject: [PATCH 740/791] ARM: dts: imx6ull-colibri: add touchscreen device nodes Move all Atmel nodes from the board-level into the main module-level device tree and prepare the device trees for use with Atmel MXT device tree overlays. Also, add required pinmux groups. The common scheme for pin groups in touch screen overlays is as follows: - pinctrl_atmel_conn - SODIMM 106/107 pins for INT/RST signals (default) - pinctrl_atmel_adap - SODIMM 28/30 pins for INT/RST signals. Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri.dtsi | 39 +++++++++++++------ 3 files changed, 31 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 95a11b8bcbdb..5e55a6c820bc 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -15,10 +15,10 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>; + &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>; }; &iomuxc_snvs { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 9f1e38282bee..6e8ddb07e11d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -26,13 +26,13 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>; + &pinctrl_gpio4 &pinctrl_gpio7>; }; &iomuxc_snvs { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>; + pinctrl-0 = <&pinctrl_snvs_gpio1>; }; &usdhc2 { diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 7cd912df5d19..c89b209be316 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -124,6 +124,19 @@ pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ + status = "disabled"; + }; }; &i2c2 { @@ -241,6 +254,20 @@ >; }; + pinctrl_atmel_adap: atmeladapgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ + >; + }; + + pinctrl_atmel_conn: atmelconngrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ + >; + }; + pinctrl_can_int: canint-grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ @@ -347,12 +374,6 @@ >; }; - pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ - >; - }; - pinctrl_gpio6: gpio6-grp { /* Wifi pins */ fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ @@ -606,12 +627,6 @@ >; }; - pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ - >; - }; - pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ From 8d386fa04d2f652d3d8e2a5d82e25f20a8467bfb Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 6 May 2022 15:24:08 +0200 Subject: [PATCH 741/791] ARM: dts: imx6ull-colibri: update usdhc1 pixmux and signaling Due to many carrier boards pulling the usdhc1 signals up to 3.3 volt we need to disable 1.8 volt signaling. Adding the no-1-8-v property basically disables UHS-I modes by default. Also pull-up the command and data lines to the +V3.3_1.8_SD rail and set them to the 200 MHz speed grade (e.g. pinmux bits 7-6: meaning 11 SPEED_3_max_200MHz). Explicitly specify a bus-width of <4> in the module-level device tree include file and drop the no-1-8-v property from the carrier boards device trees. Signed-off-by: Philippe Schenker Signed-off-by: Denys Drozdov Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 14 -------- arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++------- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index a78849fd2afa..ea086b305d22 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -159,20 +159,6 @@ }; &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - disable-wp; - wakeup-source; - keep-power-in-suspend; vmmc-supply = <®_3v3>; - vqmmc-supply = <®_sd1_vmmc>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index c89b209be316..351ea2acd5a6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -35,7 +35,7 @@ regulator-max-microvolt = <3300000>; }; - reg_sd1_vmmc: regulator-sd1-vmmc { + reg_sd1_vqmmc: regulator-sd1-vqmmc { compatible = "regulator-gpio"; gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -232,9 +232,21 @@ }; &usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; + bus-width = <4>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + keep-power-in-suspend; + no-1-8-v; + vqmmc-supply = <®_sd1_vqmmc>; + wakeup-source; }; &wdog1 { @@ -550,8 +562,8 @@ pinctrl_usdhc1: usdhc1-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ @@ -561,8 +573,8 @@ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 @@ -572,12 +584,12 @@ pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; @@ -588,7 +600,7 @@ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 >; From 233edcae449c660c3bcc49848c99f9f8e60b640c Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:09 +0200 Subject: [PATCH 742/791] ARM: dts: imx6ull-colibri: update device trees to support overlays Prepare in-tree device trees for out-of-tree device tree overlay support (eMMC SKU only). Relocate panel-dpi default to edt,et057090dhu (RGB 18bit VGA 640x480) to the module-level dtsi and remove it from the carrier board dtsi. Keep backlight, resistive touch and Atmel maxtouch nodes enabled for both eMMC and NAND modules. Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 29 ----------------- arch/arm/boot/dts/imx6ull-colibri.dtsi | 31 ++++++++++++++++--- 2 files changed, 27 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index ea086b305d22..3c07b4273e80 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -29,17 +29,6 @@ clock-frequency = <16000000>; }; - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; @@ -71,14 +60,6 @@ status = "okay"; }; -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - pwms = <&pwm4 0 5000000 1>; - status = "okay"; -}; - &ecspi1 { status = "okay"; @@ -107,16 +88,6 @@ }; }; -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - /* PWM */ &pwm4 { status = "okay"; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 351ea2acd5a6..28baffcef096 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -11,12 +11,29 @@ ethernet1 = &fec1; }; - bl: backlight { + backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - status = "disabled"; + power-supply = <®_3v3>; + pwms = <&pwm4 0 5000000 1>; + status = "okay"; + }; + + panel_dpi: panel-dpi { + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + status = "okay"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; }; reg_module_3v3: regulator-module-3v3 { @@ -149,7 +166,7 @@ scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - ad7879@2c { + ad7879_ts: touchscreen@2c { compatible = "adi,ad7879-1"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_ad7879_int>; @@ -170,6 +187,12 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; }; &pwm4 { From c8eb30d06ee8401d21b166b6e3f0f7a5b2990971 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 6 May 2022 15:24:10 +0200 Subject: [PATCH 743/791] ARM: dts: imx6ull-colibri: add gpio-line-names Add GPIO line names on module-level. Those are all GPIOs that a user might use on his custom carrier board. If more meaningful names are available on the carrier board, the user can overwrite the line names in the carrier board-level device tree. Signed-off-by: Oleksandr Suvorov Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 137 ++++++++++++++++++ arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 136 +++++++++++++++++ 2 files changed, 273 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 5e55a6c820bc..60f169227ad9 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -12,6 +12,143 @@ }; }; +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "SODIMM_89", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "SODIMM_81", + "SODIMM_94", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "SODIMM_93", + "", + "SODIMM_138", + "", + "SODIMM_105", + "SODIMM_127"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 6e8ddb07e11d..3c47cfa7afa5 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -23,6 +23,142 @@ clock-frequency = <792000000>; }; +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "", + "", + "", + "", + "", + "", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "", + "", + "", + "", + "SODIMM_105"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 From 613d063240538e6c9a880bb63eb62d6ad33a9352 Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:11 +0200 Subject: [PATCH 744/791] ARM: dts: imx6ull-colibri: add support for toradex iris carrier boards Add support for Toradex Iris, small form-factor Pico-ITX Colibri Arm Computer Module family carrier boards. Iris Device Trees: - imx6ull-colibri-iris.dtb - imx6ull-colibri-emmc-iris.dtb - imx6ull-colibri-wifi-iris.dtb Iris-V2 Device Trees: - imx6ull-colibri-iris-v2.dtb - imx6ull-colibri-emmc-iris-v2.dtb - imx6ull-colibri-wifi-iris-v2.dtb Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 6 + .../boot/dts/imx6ull-colibri-emmc-iris-v2.dts | 17 +++ .../boot/dts/imx6ull-colibri-emmc-iris.dts | 17 +++ .../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts | 6 +- .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 5 +- arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts | 65 +++++++++ .../arm/boot/dts/imx6ull-colibri-iris-v2.dtsi | 27 ++++ arch/arm/boot/dts/imx6ull-colibri-iris.dts | 20 +++ arch/arm/boot/dts/imx6ull-colibri-iris.dtsi | 132 ++++++++++++++++++ .../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 4 +- .../boot/dts/imx6ull-colibri-wifi-eval-v3.dts | 4 +- .../boot/dts/imx6ull-colibri-wifi-iris-v2.dts | 65 +++++++++ .../boot/dts/imx6ull-colibri-wifi-iris.dts | 20 +++ arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri.dtsi | 4 +- 16 files changed, 385 insertions(+), 15 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b711d4423b42..d18b5a7cc4e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -708,8 +708,14 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-emmc-eval-v3.dtb \ + imx6ull-colibri-emmc-iris.dtb \ + imx6ull-colibri-emmc-iris-v2.dtb \ imx6ull-colibri-eval-v3.dtb \ + imx6ull-colibri-iris.dtb \ + imx6ull-colibri-iris-v2.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-colibri-wifi-iris.dtb \ + imx6ull-colibri-wifi-iris-v2.dtb \ imx6ull-jozacp.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-opos6uldev.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..b9060c2f7977 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts new file mode 100644 index 000000000000..0ab71f2f5daa --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-emmc-iris", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi index a099abfdfa27..1d75bc671f75 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2021 Toradex + * Copyright 2022 Toradex */ #include "imx6ull-colibri.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts index 08669a18349e..9bf7111d7b00 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ /dts-v1/; @@ -9,6 +9,6 @@ #include "imx6ull-colibri-eval-v3.dtsi" / { - model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3"; + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index 3c07b4273e80..08197c66af12 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017 Toradex AG + * Copyright 2017-2022 Toradex */ / { @@ -121,6 +121,7 @@ }; &usbotg1 { + vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts new file mode 100644 index 000000000000..afc1e0119783 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..93649cad0cc0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +#include "imx6ull-colibri-iris.dtsi" + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + + +&usdhc1 { + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + /delete-property/ keep-power-in-suspend; + /delete-property/ no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts new file mode 100644 index 000000000000..4fb97b0fe30b --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi new file mode 100644 index 000000000000..7f3b37baba88 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&gpio1 { + /* + * uart25_tx_on turns the UART transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + * The same applies to uart1_tx_on. + */ + uart25_tx_on { + gpio-hog; + gpios = <15 0>; + output-high; + }; +}; + +&gpio2 { + uart1_tx_on { + gpio-hog; + gpios = <7 0>; + output-high; + }; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 60f169227ad9..88901db255d6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ #include "imx6ull-colibri.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts index df72ce1ae2cb..1d64d1a5d8a7 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts new file mode 100644 index 000000000000..ce02f8a9ddd3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-wifi-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts new file mode 100644 index 000000000000..5ac1aa298ce7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-wifi-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 3c47cfa7afa5..db59ee6b1c86 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ #include "imx6ull-colibri.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 28baffcef096..e74dd98fa66a 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018-2021 Toradex + * Copyright 2018-2022 Toradex */ #include "imx6ull.dtsi" From 015feccc772297b7d8e95361437aa9def4adba7e Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:12 +0200 Subject: [PATCH 745/791] ARM: dts: imx6ull-colibri: add support for toradex aster carrier boards Add support for Toradex Aster, small form-factor Colibri Arm Computer Module family carrier board. Aster Device Trees: - imx6ull-colibri-aster.dtb - imx6ull-colibri-emmc-aster.dtb - imx6ull-colibri-wifi-aster.dtb Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/imx6ull-colibri-aster.dts | 20 +++ arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 145 ++++++++++++++++++ .../boot/dts/imx6ull-colibri-emmc-aster.dts | 17 ++ .../boot/dts/imx6ull-colibri-wifi-aster.dts | 20 +++ 5 files changed, 205 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d18b5a7cc4e8..a496c4751c86 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -707,12 +707,15 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ + imx6ull-colibri-aster.dtb \ + imx6ull-colibri-emmc-aster.dtb \ imx6ull-colibri-emmc-eval-v3.dtb \ imx6ull-colibri-emmc-iris.dtb \ imx6ull-colibri-emmc-iris-v2.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-iris.dtb \ imx6ull-colibri-iris-v2.dtb \ + imx6ull-colibri-wifi-aster.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ imx6ull-colibri-wifi-iris.dtb \ imx6ull-colibri-wifi-iris-v2.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts new file mode 100644 index 000000000000..d3f2fb7c6c1e --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi new file mode 100644 index 000000000000..c9133ba2d705 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + num-cs = <2>; + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */ + &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */ + >; +}; + +/* + * Following SODIMM Pins should not be accessed as GPIO on Aster board: + * 134 - AIN5_SCL (no connection) + * 127 - Voltage Level Translator OE# signal (IC11 and IC12) + * + * To configure GPIO to LED5, please disable FEC2 and uncomment the following: + * &iomuxc { + * pinctrl-names = "default"; + * pinctrl-0 = < + * &pinctrl_gpio1 + * &pinctrl_gpio2 + * &pinctrl_gpio3 + * &pinctrl_gpio4 + * &pinctrl_gpio6 - for non-WiFi modules only + * &pinctrl_gpio7 + * &pinctrl_gpio_aster + * >; + * + * pinctrl_gpio_aster: gpio-aster { + * fsl,pins = < + * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0 + * >; + * }; + * }; + */ + +&i2c1 { + status = "okay"; + + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts new file mode 100644 index 000000000000..919c0464d6cb --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-emmc-aster", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts new file mode 100644 index 000000000000..b4f65e8c5857 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-wifi-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; From 548453688549a69849bb93c5090767330ff98cbe Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:13 +0200 Subject: [PATCH 746/791] ARM: dts: imx6ull-colibri: fix nand bch geometry Fix NAND BCH geometry relevant mainly for U-Boot. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index e74dd98fa66a..5e0cee146121 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -128,6 +128,7 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; nand-on-flash-bbt; nand-ecc-mode = "hw"; nand-ecc-strength = <8>; From 17c101d839f58cc4b977706719909871765fe7b9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:14 +0200 Subject: [PATCH 747/791] ARM: dts: imx6ull-colibri: add/update some comments Add/update some comments. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 ++- arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++++----- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi index 1d75bc671f75..ea238525d5c0 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi @@ -8,7 +8,7 @@ / { aliases { mmc0 = &usdhc2; /* eMMC */ - mmc1 = &usdhc1; /* MMC 4bit slot */ + mmc1 = &usdhc1; /* MMC 4-bit slot */ }; memory@80000000 { @@ -154,6 +154,7 @@ "SODIMM_127"; }; +/* NAND */ &gpmi { status = "disabled"; }; @@ -170,6 +171,7 @@ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; }; +/* eMMC */ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2emmc>; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 5e0cee146121..4611fa890889 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -6,6 +6,7 @@ #include "imx6ull.dtsi" / { + /* Ethernet aliases to ensure correct MAC addresses */ aliases { ethernet0 = &fec2; ethernet1 = &fec1; @@ -104,6 +105,7 @@ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; }; +/* Ethernet */ &fec2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet2>; @@ -125,6 +127,7 @@ }; }; +/* NAND */ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -136,6 +139,7 @@ status = "okay"; }; +/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; @@ -157,6 +161,10 @@ }; }; +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ &i2c2 { /* Use low frequency to compensate for the high pull-up values. */ clock-frequency = <40000>; @@ -196,21 +204,25 @@ }; }; +/* PWM */ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; }; +/* PWM */ &pwm5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; }; +/* PWM */ &pwm6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm6>; }; +/* PWM */ &pwm7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm7>; @@ -224,6 +236,7 @@ status = "disabled"; }; +/* Colibri UART_A */ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; @@ -231,6 +244,7 @@ fsl,dte-mode; }; +/* Colibri UART_B */ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -238,12 +252,14 @@ fsl,dte-mode; }; +/* Colibri UART_C */ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; fsl,dte-mode; }; +/* Colibri USBC */ &usbotg1 { dr_mode = "otg"; srp-disable; @@ -251,10 +267,12 @@ adp-disable; }; +/* Colibri USBH */ &usbotg2 { dr_mode = "host"; }; +/* Colibri MMC/SD */ &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; @@ -265,7 +283,7 @@ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; bus-width = <4>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ disable-wp; keep-power-in-suspend; no-1-8-v; @@ -431,7 +449,7 @@ /* * With an eMMC instead of a raw NAND device the following pins - * are available at SODIMM pins + * are available at SODIMM pins. */ pinctrl_gpmi_gpio: gpmi-gpio-grp { fsl,pins = < @@ -556,10 +574,10 @@ pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ fsl,pins = < - MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */ - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */ - MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */ - MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */ + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ >; }; @@ -580,7 +598,7 @@ pinctrl_usbh_reg: gpio-usbh-reg { fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ >; }; @@ -658,7 +676,7 @@ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */ + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ >; }; @@ -695,7 +713,7 @@ pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */ + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ >; }; From a5fa132bbe4f66e4b3eea1085015a281477fa905 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:15 +0200 Subject: [PATCH 748/791] ARM: dts: imx6ull-colibri: move gpio-keys node to som dtsi The gpio-keys define module level wake-up pin functionality. Move it from the carrier board dts file to the Som dtsi file. While at it, also re-order the properties in the gpio-keys node alphabetically and rename to sub-node from power to wakeup. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 15 --------------- arch/arm/boot/dts/imx6ull-colibri.dtsi | 16 +++++++++++++++- 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index 08197c66af12..e29907428c20 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -8,20 +8,6 @@ stdout-path = "serial0:115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - /* fixed crystal dedicated to mcp2515 */ clk16m: clk16m { compatible = "fixed-clock"; @@ -29,7 +15,6 @@ clock-frequency = <16000000>; }; - reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3.3V"; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 4611fa890889..4292311bdc6e 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -24,6 +24,20 @@ status = "okay"; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + panel_dpi: panel-dpi { compatible = "edt,et057090dhu"; backlight = <&backlight>; @@ -707,7 +721,7 @@ pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */ + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ >; }; From 19a434aa3ebc29fda4799454afe882a5edcb1b94 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:16 +0200 Subject: [PATCH 749/791] ARM: dts: imx6ull-colibri: improve pinctrl node names Improve on pinctrl node names. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 93 +++++++++++++------------- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 4292311bdc6e..15ebabcacfc5 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -292,7 +292,7 @@ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; @@ -312,7 +312,6 @@ }; &iomuxc { - pinctrl_adc1: adc1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ @@ -336,13 +335,13 @@ >; }; - pinctrl_can_int: canint-grp { + pinctrl_can_int: canintgrp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ >; }; - pinctrl_enet2: enet2-grp { + pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 @@ -357,7 +356,7 @@ >; }; - pinctrl_enet2_sleep: enet2sleepgrp { + pinctrl_enet2_sleep: enet2-sleepgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 @@ -372,13 +371,13 @@ >; }; - pinctrl_ecspi1_cs: ecspi1-cs-grp { + pinctrl_ecspi1_cs: ecspi1csgrp { fsl,pins = < MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ >; }; - pinctrl_ecspi1: ecspi1-grp { + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ @@ -386,27 +385,27 @@ >; }; - pinctrl_flexcan1: flexcan1-grp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 >; }; - pinctrl_flexcan2: flexcan2-grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 >; }; - pinctrl_gpio_bl_on: gpio-bl-on-grp { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ >; }; - pinctrl_gpio1: gpio1-grp { + pinctrl_gpio1: gpio1grp { fsl,pins = < MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ @@ -419,7 +418,7 @@ >; }; - pinctrl_gpio2: gpio2-grp { /* Camera */ + pinctrl_gpio2: gpio2grp { /* Camera */ fsl,pins = < MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ @@ -429,20 +428,20 @@ >; }; - pinctrl_gpio3: gpio3-grp { /* CAN2 */ + pinctrl_gpio3: gpio3grp { /* CAN2 */ fsl,pins = < MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ >; }; - pinctrl_gpio4: gpio4-grp { + pinctrl_gpio4: gpio4grp { fsl,pins = < MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ >; }; - pinctrl_gpio6: gpio6-grp { /* Wifi pins */ + pinctrl_gpio6: gpio6grp { /* Wifi pins */ fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ @@ -454,7 +453,7 @@ >; }; - pinctrl_gpio7: gpio7-grp { /* CAN1 */ + pinctrl_gpio7: gpio7grp { /* CAN1 */ fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ @@ -465,7 +464,7 @@ * With an eMMC instead of a raw NAND device the following pins * are available at SODIMM pins. */ - pinctrl_gpmi_gpio: gpmi-gpio-grp { + pinctrl_gpmi_gpio: gpmigpiogrp { fsl,pins = < MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ @@ -474,7 +473,7 @@ >; }; - pinctrl_gpmi_nand: gpmi-nand-grp { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 @@ -493,35 +492,35 @@ >; }; - pinctrl_i2c1: i2c1-grp { + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ >; }; - pinctrl_i2c1_gpio: i2c1-gpio-grp { + pinctrl_i2c1_gpio: i2c1-gpiogrp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ >; }; - pinctrl_i2c2: i2c2-grp { + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 >; }; - pinctrl_i2c2_gpio: i2c2-gpio-grp { + pinctrl_i2c2_gpio: i2c2-gpiogrp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 >; }; - pinctrl_lcdif_dat: lcdif-dat-grp { + pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ @@ -544,7 +543,7 @@ >; }; - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ @@ -553,31 +552,31 @@ >; }; - pinctrl_pwm4: pwm4-grp { + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ >; }; - pinctrl_pwm5: pwm5-grp { + pinctrl_pwm5: pwm5grp { fsl,pins = < MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ >; }; - pinctrl_pwm6: pwm6-grp { + pinctrl_pwm6: pwm6grp { fsl,pins = < MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ >; }; - pinctrl_pwm7: pwm7-grp { + pinctrl_pwm7: pwm7grp { fsl,pins = < MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ >; }; - pinctrl_uart1: uart1-grp { + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ @@ -586,7 +585,7 @@ >; }; - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ + pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ fsl,pins = < MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ @@ -595,7 +594,7 @@ >; }; - pinctrl_uart2: uart2-grp { + pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ @@ -603,20 +602,20 @@ MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ >; }; - pinctrl_uart5: uart5-grp { + pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ >; }; - pinctrl_usbh_reg: gpio-usbh-reg { + pinctrl_usbh_reg: usbhreggrp { fsl,pins = < MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ >; }; - pinctrl_usdhc1: usdhc1-grp { + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ @@ -627,7 +626,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 @@ -638,7 +637,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 @@ -649,7 +648,7 @@ >; }; - pinctrl_usdhc2: usdhc2-grp { + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 @@ -677,7 +676,7 @@ >; }; - pinctrl_wdog: wdog-grp { + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; @@ -685,7 +684,7 @@ }; &iomuxc_snvs { - pinctrl_snvs_gpio1: snvs-gpio1-grp { + pinctrl_snvs_gpio1: snvsgpio1grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ @@ -695,49 +694,49 @@ >; }; - pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ + pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ >; }; - pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ + pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ fsl,pins = < MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 >; }; - pinctrl_snvs_reg_sd: snvs-reg-sd-grp { + pinctrl_snvs_reg_sd: snvsregsdgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 >; }; - pinctrl_snvs_usbc_det: snvs-usbc-det-grp { + pinctrl_snvs_usbc_det: snvsusbcdetgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 >; }; - pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { + pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ >; }; - pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { + pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ >; }; - pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { + pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 >; }; - pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { + pinctrl_snvs_wifi_pdn: snvswifipdngrp { fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 >; From 092b3ace58d9049bcd0381c32f2cd69302e199bc Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Mon, 25 Apr 2022 13:42:32 +0700 Subject: [PATCH 750/791] ARM: dts: sunxi: nanopi: Remove input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Acked-by: Jernej Skrabec Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220425064231.243482-1-danct12@riseup.net --- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index fc45d5aaa67f..a9f749f49beb 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -75,7 +75,6 @@ r_gpio_keys { compatible = "gpio-keys"; - input-name = "k1"; k1 { label = "k1"; From 5e9b59bd37371ef1e627b24483c0388a2567cc1c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 22 Mar 2022 11:58:56 +0100 Subject: [PATCH 751/791] arm64: dts: uDPU: update partition table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Partition currently called "uboot" does not only contain U-boot, but rather it contains TF-A, U-boot and U-boot environment. So, to avoid accidentally deleting the U-boot environment which is located at 0x180000 split the partition. "uboot" is not the correct name as you can't boot these boards with U-boot only, TF-A must be present as well, so rename the "uboot" partition to "firmware". While we are here, describe the NOR node as "spi-flash@0" instead of "m25p80@0" which is the old SPI-NOR driver name. This won't break booting for existing devices as the SoC-s BootROM is not partition aware at all, it will simply try booting from 0x0 of the boot device that is set by bootstrap pins. This will however prevent accidental or automated flashing of just U-boot to the partition. Signed-off-by: Robert Marko Reviewed-by: Pali Rohár Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts index 95d46e8d081c..ac64949bb53e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + spi-flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <54000000>; @@ -108,10 +108,15 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - /* only bootloader is located on the SPI */ + partition@0 { - label = "uboot"; - reg = <0 0x400000>; + label = "firmware"; + reg = <0x0 0x180000>; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x10000>; }; }; }; From e4fde76fa54a6f13da7fd5fd6601474c16c54d8d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 22 Mar 2022 11:58:57 +0100 Subject: [PATCH 752/791] arm64: dts: uDPU: correct temperature sensors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit uDPU has a pair of NCT375 temperature sensors, which are TMP75C compatible as far as the driver is concerned. The current LM75 compatible worked as all of the LM75 compatible sensors are backwards compatible with the original part, but it meant that lower resolution and incorrect sample rate was being used. The "lm75" compatible has been deprecated anyway and is meant as fallback in order to keep older DTS-es working. Signed-off-by: Robert Marko Reviewed-by: Pali Rohár Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts index ac64949bb53e..1f534c0c65f7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -153,15 +153,15 @@ scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - lm75@48 { + nct375@48 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x48>; }; - lm75@49 { + nct375@49 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x49>; }; }; From 5202f4c3816b42e989f9cad49a73c7e88fba89f4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 28 Sep 2021 19:09:17 +0200 Subject: [PATCH 753/791] arm64: dts: marvell: espressobin-ultra: fix SPI-NOR config SPI config for the SPI-NOR is incorrect and completely breaking reading/writing to the onboard SPI-NOR. SPI-NOR is connected in the single(x1) IO mode and not in the quad (x4) mode. Also, there is no need to override the max frequency from the DTSI as the mx25u3235f that is used supports 104Mhz. Fixes: 3404fe15a60f ("arm64: dts: marvell: add DT for ESPRESSObin-Ultra") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index c5eb3604dd5b..610ff6f385c7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -71,10 +71,6 @@ &spi0 { flash@0 { - spi-max-frequency = <108000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; From e836070f94619af5325fd69d3fb48bd1a9e569b4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 28 Sep 2021 19:09:18 +0200 Subject: [PATCH 754/791] arm64: dts: marvell: espressobin-ultra: add PHY and switch reset pins Both the Topaz switch and 88E1512 PHY have their reset and interrupts connected to the SoC. So, define the Topaz and 88E1512 reset pins in the DTS. Defining the interrupt pins wont work as both the 88E1512 and the Topaz switch uses active LOW IRQ signals but the A37xx GPIO controller only supports edge triggers. 88E1512 would require special setup anyway as its INT pin is shared with the LED2 and you first need to configure it as INT. Signed-off-by: Robert Marko Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 610ff6f385c7..7c786d218f1b 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -114,12 +114,16 @@ &mdio { extphy: ethernet-phy@1 { reg = <1>; + + reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; }; }; &switch0 { reg = <3>; + reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; + ports { switch0port1: port@1 { reg = <1>; From eacec7ebc16cf5d2f6a6c7cf5d57156da2c3e98f Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 28 Sep 2021 19:09:19 +0200 Subject: [PATCH 755/791] arm64: dts: marvell: espressobin-ultra: enable front USB3 port Espressobin Ultra has a front panel USB3.0 Type-A port which works just fine so enable it. I dont see a reason why it was disabled in the first place anyway. Fixes: 3404fe15a60f ("arm64: dts: marvell: add DT for ESPRESSObin-Ultra") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 7c786d218f1b..070725b81be5 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -108,7 +108,6 @@ &usb3 { usb-phy = <&usb3_phy>; - status = "disabled"; }; &mdio { From 239466bddfc02f9643f64be74ba9a1d80c286f4b Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 30 Mar 2022 11:05:43 +1300 Subject: [PATCH 756/791] arm64: dts: marvell: Update sdhci node names to match schema Update the node names of the sdhci@ interfaces to be mmc@ to match the node name enforced by the mmc-controller.yaml schema. Signed-off-by: Chris Packham Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 4 ++-- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 8c8bb97c9d30..df152c72276b 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -444,7 +444,7 @@ #mbox-cells = <1>; }; - sdhci1: sdhci@d0000 { + sdhci1: mmc@d0000 { compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; reg = <0xd0000 0x300>, @@ -455,7 +455,7 @@ status = "disabled"; }; - sdhci0: sdhci@d8000 { + sdhci0: mmc@d8000 { compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; reg = <0xd8000 0x300>, diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 6614472100c2..a06a0a889c43 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -250,7 +250,7 @@ interrupts = ; }; - ap_sdhci0: sdhci@6e0000 { + ap_sdhci0: mmc@6e0000 { compatible = "marvell,armada-ap806-sdhci"; reg = <0x6e0000 0x300>; interrupts = ; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 3bd2182817fb..d6c0990a267d 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -493,7 +493,7 @@ status = "okay"; }; - CP11X_LABEL(sdhci0): sdhci@780000 { + CP11X_LABEL(sdhci0): mmc@780000 { compatible = "marvell,armada-cp110-sdhci"; reg = <0x780000 0x300>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; From 34f7c6e7d4396090692a09789db231e12cb4762b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 20 Apr 2021 14:38:27 +0900 Subject: [PATCH 757/791] arm64: dts: visconti: Add clock controller support for TMPV7708 Adds node of clock controller support for Toshiba Visconti TMPV7708. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220421080143.2135566-1-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 01d7ee61ad25..1683113a3c43 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -7,6 +7,7 @@ * */ +#include #include #include @@ -182,6 +183,12 @@ #clock-cells = <0>; }; + osc2_clk: osc2-clk { + compatible = "fixed-clock"; + clock-frequency = <20000000>; + #clock-cells = <0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -216,6 +223,20 @@ interrupt-parent = <&gic>; }; + pipllct: clock-controller@24220000 { + compatible = "toshiba,tmpv7708-pipllct"; + reg = <0 0x24220000 0 0x820>; + #clock-cells = <1>; + clocks = <&osc2_clk>; + }; + + pismu: syscon@24200000 { + compatible = "toshiba,tmpv7708-pismu", "syscon"; + reg = <0 0x24200000 0 0x2140>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@28200000 { compatible = "arm,pl011", "arm,primecell"; reg = <0 0x28200000 0 0x1000>; From 4374055674eaf52c185c24fcbeb6cf7d6359bfc4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: [PATCH 758/791] arm64: dts: visconti: Update the clock providers for UART Remove fixed clock and source common clock for UART. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-2-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 4 ---- .../boot/dts/toshiba/tmpv7708-visrobo-vrb.dts | 4 ---- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 14 ++++++++------ 3 files changed, 8 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 9375b0faeea2..9b0666df6593 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -32,14 +32,10 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &piether { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts index d0817463706e..56701e0e1dab 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts @@ -32,14 +32,10 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &piether { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 1683113a3c43..3b51e875630c 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -129,12 +129,6 @@ ; }; - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - clk25mhz: clk25mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -243,6 +237,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART0>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -252,6 +248,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -261,6 +259,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART2>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -270,6 +270,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART2>; + clock-names = "apb_pclk"; status = "disabled"; }; From 0e7cd4395be5f433b70bde8d902ed50484ee1bc1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: [PATCH 759/791] arm64: dts: visconti: Update the clock providers for I2C Replace I2C clock with common clock framework. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-3-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 1 - arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 9 +++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index f0a93db6dde6..03827ce06ee3 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -40,5 +40,4 @@ &i2c0 { status = "okay"; - clocks = <&clk150mhz>; }; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 3b51e875630c..048b5dc7ae18 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -284,6 +284,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C0>; status = "disabled"; }; @@ -296,6 +297,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C1>; status = "disabled"; }; @@ -308,6 +310,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C2>; status = "disabled"; }; @@ -320,6 +323,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C3>; status = "disabled"; }; @@ -332,6 +336,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C4>; status = "disabled"; }; @@ -344,6 +349,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C5>; status = "disabled"; }; @@ -356,6 +362,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C6>; status = "disabled"; }; @@ -368,6 +375,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C7>; status = "disabled"; }; @@ -380,6 +388,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C8>; status = "disabled"; }; From 27b754902dab93d1c3bde94e97983ca0fe81f253 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: [PATCH 760/791] arm64: dts: visconti: Update the clock providers for watchdog timer Remove fixed clock and source common clock for watchdog timer. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-4-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 1 - arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 1 - arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 7 +------ 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 9b0666df6593..45ddf6f03175 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -58,7 +58,6 @@ &wdt { status = "okay"; - clocks = <&wdt_clk>; }; &gpio { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index 03827ce06ee3..adfe8406c24c 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -13,7 +13,6 @@ &wdt { status = "okay"; - clocks = <&wdt_clk>; }; &gpio { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 048b5dc7ae18..6050796a1678 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -171,12 +171,6 @@ clock-output-names = "extclk100mhz"; }; - wdt_clk: wdt-clk { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - osc2_clk: osc2-clk { compatible = "fixed-clock"; clock-frequency = <20000000>; @@ -490,6 +484,7 @@ wdt: wdt@28330000 { compatible = "toshiba,visconti-wdt"; reg = <0 0x28330000 0 0x1000>; + clocks = <&pismu TMPV770X_CLK_WDTCLK>; status = "disabled"; }; From 340657b179165410ec6ca30db6e6d7fc5c366ca1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 22 Apr 2022 11:39:44 +0900 Subject: [PATCH 761/791] arm64: dts: visconti: Update the clock providers for SPI Remove fixed clock and source common clock for SPI. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-5-nobuhiro1.iwamatsu@toshiba.co.jp/ --- .../dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 21 ++++++++++++------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index adfe8406c24c..0c8321022a73 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -25,8 +25,6 @@ &spi0 { status = "okay"; - clocks = <&clk300mhz>, <&clk150mhz>; - clock-names = "sspclk", "apb_pclk"; mmc-slot@0 { compatible = "mmc-spi-slot"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 6050796a1678..196cda7b5d90 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -143,13 +143,6 @@ clock-output-names = "clk125mhz"; }; - clk150mhz: clk150mhz { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - clock-output-names = "clk150mhz"; - }; - clk300mhz: clk300mhz { compatible = "fixed-clock"; clock-frequency = <300000000>; @@ -395,6 +388,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -407,6 +402,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -419,6 +416,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI2>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -431,6 +430,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI3>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -443,6 +444,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI4>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -455,6 +458,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI5>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -467,6 +472,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI6>; + clock-names = "apb_pclk"; status = "disabled"; }; From c8a93f913109e575f3b9ddc330f210aa3d3cf2e1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 22 Apr 2022 23:12:54 +0900 Subject: [PATCH 762/791] arm64: dts: visconti: Update the clock providers for ethernet device Remove fixed clock and source common clock for ethernet device. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-6-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 2 -- .../boot/dts/toshiba/tmpv7708-visrobo-vrb.dts | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 16 ++-------------- 3 files changed, 2 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 45ddf6f03175..527bb437dd90 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -42,8 +42,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - clocks = <&clk300mhz>, <&clk125mhz>; - clock-names = "stmmaceth", "phy_ref_clk"; mdio0 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts index 56701e0e1dab..ed7aa7e457b1 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts @@ -42,8 +42,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - clocks = <&clk300mhz>, <&clk125mhz>; - clock-names = "stmmaceth", "phy_ref_clk"; mdio0 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 196cda7b5d90..7c80a9434e10 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -136,20 +136,6 @@ clock-output-names = "clk25mhz"; }; - clk125mhz: clk125mhz { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - #clock-cells = <0>; - clock-output-names = "clk125mhz"; - }; - - clk300mhz: clk300mhz { - compatible = "fixed-clock"; - clock-frequency = <300000000>; - #clock-cells = <0>; - clock-output-names = "clk300mhz"; - }; - clk600mhz: clk600mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -485,6 +471,8 @@ snps,txpbl = <4>; snps,rxpbl = <4>; snps,tso; + clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>; + clock-names = "stmmaceth", "phy_ref_clk"; status = "disabled"; }; From 5d3b6ede2c6c80304944cdb5bc653957390afcf4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: [PATCH 763/791] arm64: dts: visconti: Update the clock providers for PCIe host controller Remove fixed clock and source common clock for PCIe host controller. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-7-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 16 ++-------------- 2 files changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 527bb437dd90..d209fdc98597 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -72,6 +72,4 @@ &pcie { status = "okay"; - clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>; - clock-names = "ref", "core", "aux"; }; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 7c80a9434e10..0fc32c036f30 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -129,20 +129,6 @@ ; }; - clk25mhz: clk25mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "clk25mhz"; - }; - - clk600mhz: clk600mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - clock-output-names = "clk600mhz"; - }; - extclk100mhz: extclk100mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -520,6 +506,8 @@ 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; max-link-speed = <2>; + clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>; + clock-names = "ref", "core", "aux"; status = "disabled"; }; }; From bc405bb3eeee4b711830ab569e7f3811b92196ab Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Apr 2022 15:35:00 +0200 Subject: [PATCH 764/791] arm64: dts: rockchip: enable otg/drd operation of usb_host0_xhci in rk356x This USB 3.0 controller is capable of OTG/DRD operation. Enable it in the device tree. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220425133502.405512-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 3f0e11af738d..1042e68602de 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -266,7 +266,7 @@ <&cru ACLK_USB3OTG0>; clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "host"; + dr_mode = "otg"; phy_type = "utmi_wide"; power-domains = <&power RK3568_PD_PIPE>; resets = <&cru SRST_USB3OTG0>; From 18176b9d82eebaf4408dc0440f54d57a8cbced83 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 13 May 2022 11:11:07 +0200 Subject: [PATCH 765/791] Revert "ARM: dts: BCM5301X: Fix DTC warning for NAND node" This reverts commit 90103611d573, which caused a new DTC warning arch/arm/boot/dts/bcm953012hr.dts:57.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:62.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@200000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:66.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@600000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:70.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@1000000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi index bdf1b4a608e6..be9a00ff752d 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -10,6 +10,8 @@ nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; partitions { compatible = "brcm,bcm947xx-cfe-partitions"; From 045d0c3db9119ebb36d50e0190bed4ea6374f6cf Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 11 May 2022 11:25:59 +0200 Subject: [PATCH 766/791] dt-bindings: clock: stm32mp1: adapt example for "st,stm32mp1-rcc-secure" For "st,stm32mp1-rcc-secure" schema, clocks and clock-names entries are now required properties. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220511092559.4952-1-alexandre.torgue@foss.st.com' Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index bb0e0b92e907..45b94124366c 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -106,10 +106,17 @@ additionalProperties: false examples: - | + #include rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc-secure", "syscon"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; }; ... From c88fd98110242ed56b24284dd975fe54f2f65756 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Mon, 25 Apr 2022 13:48:51 +0700 Subject: [PATCH 767/791] arm64: dts: mediatek: pumpkin: Remove input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220425064850.246228-1-danct12@riseup.net Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index fcddec14738d..7a717f926929 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -25,7 +25,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_default>; From 7d029cc240a012f0259477c905e84f3975d7cf2f Mon Sep 17 00:00:00 2001 From: Rui Salvaterra Date: Fri, 29 Apr 2022 09:42:25 +0100 Subject: [PATCH 768/791] arm64: dts: mt7622: specify the number of DMA requests The MT7622 device tree never bothered to specify the number of virtual DMA channels for the HSDMA controller, always falling back to the default value of 3. Make this value explicit, in order to avoid the following dmesg notification: mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property Signed-off-by: Rui Salvaterra Link: https://lore.kernel.org/r/20220429084225.298213-1-rsalvaterra@gmail.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 6f8cb3ad1e84..da1f88d06dcc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -917,6 +917,7 @@ clock-names = "hsdma"; power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; #dma-cells = <1>; + dma-requests = <3>; }; eth: ethernet@1b100000 { From 80dd27b6c68c7189b865b4b966aa12c77d1adc1e Mon Sep 17 00:00:00 2001 From: Rui Salvaterra Date: Thu, 28 Apr 2022 23:57:55 +0100 Subject: [PATCH 769/791] arm64: dts: mt7622: specify the L2 cache topology On an MT7622 system, the kernel complains of not being able to detect the cache hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in order to fix this. Signed-off-by: Rui Salvaterra Link: https://lore.kernel.org/r/20220428225755.785153-1-rsalvaterra@gmail.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index da1f88d06dcc..5551f004945b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -80,6 +80,7 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -94,6 +95,12 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; }; From 41d2d562e89cb9b9558242653862a932fd877f9a Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Apr 2022 18:47:55 +0200 Subject: [PATCH 770/791] arm64: dts: mediatek: mt8183-pumpkin: fix bad thermistor node name Fix the following dtbs_check error by using the correct node name: /home/fabo/build/linux/mt8183-pumpkin/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dtb: ntc: $nodename:0: 'ntc' does not match '^thermistor(.*)?$' From schema: /home/fabo/devel/baylibre/linux-mainline/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220426164755.435372-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index ee912825cfc6..afeb5cd37826 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -55,7 +55,7 @@ }; }; - ntc { + thermistor { compatible = "murata,ncp03wf104"; pullup-uv = <1800000>; pullup-ohm = <390000>; From 8a87419481f2d51a7bd03617d363faf5f2b0e1b3 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Apr 2022 15:41:04 +0200 Subject: [PATCH 771/791] arm64: dts: mediatek: mt8195-demo: Remove input-name property This property doesn't seem to exist in the documentation nor in source code, let's remove it from the device-tree. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20220426134106.242353-7-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index def3fc26cb99..6606c7fe8db3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -34,7 +34,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins>; From 7640d4350ae89df0ef142144c93e0ae48d623b69 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Apr 2022 15:41:05 +0200 Subject: [PATCH 772/791] arm64: dts: mediatek: mt8195-demo: enable uart1 The UART1 is exposed on a header. Enable the uart1 node to be able to use it. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20220426134106.242353-8-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 6606c7fe8db3..4fbd99eb496a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -406,6 +406,12 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + &u3phy0 { status = "okay"; }; From 5ba090a03af2074841342bbe5fee45260ec62144 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sun, 24 Apr 2022 11:25:27 +0800 Subject: [PATCH 773/791] arm64: dts: mediatek: add mtk-snfi for mt7622 This patch adds a device-tree node for the MTK SPI-NAND Flash Interface for MT7622 device tree. Signed-off-by: Chuanhong Guo Link: https://lore.kernel.org/r/20220424032527.673605-6-gch981213@gmail.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 5551f004945b..9768523fe4c3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -552,6 +552,18 @@ status = "disabled"; }; + snfi: spi@1100d000 { + compatible = "mediatek,mt7622-snand"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + bch: ecc@1100e000 { compatible = "mediatek,mt7622-ecc"; reg = <0 0x1100e000 0 0x1000>; From c75104762ddace5973deb4ea54d35bf2b64bba98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Wed, 4 May 2022 17:45:16 -0400 Subject: [PATCH 774/791] arm64: dts: mt8192: Follow binding order for SCP registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dt-binding for SCP documents the reg-names order as sram, cfg, l1tcm. Update the SCP node on the mt8192 devicetree to follow that order, which gets rid of a dtbs_check warning. This doesn't change any behavior since the SCP driver accesses the memory regions through the names anyway. Fixes: c63556ec6bfe ("arm64: dts: mt8192: Add SCP node") Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220504214516.2957504-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 26dbe9ecc528..733aec2e7f77 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -699,9 +699,9 @@ scp: scp@10500000 { compatible = "mediatek,mt8192-scp"; reg = <0 0x10500000 0 0x100000>, - <0 0x10700000 0 0x8000>, - <0 0x10720000 0 0xe0000>; - reg-names = "sram", "l1tcm", "cfg"; + <0 0x10720000 0 0xe0000>, + <0 0x10700000 0 0x8000>; + reg-names = "sram", "cfg", "l1tcm"; interrupts = ; clocks = <&infracfg CLK_INFRA_SCPSYS>; clock-names = "main"; From f60e2de515095d04a05c6fc169ab6457bc70f3da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 12 May 2022 11:59:39 +0200 Subject: [PATCH 775/791] ARM: dts: turris-omnia: Add atsha204a node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Crypto module atsha204a is available at i2c address 0x64. Module is used for symmetric cryptography and provides also hardware random number generator and OTP storage for device serial number and MAC addresses. Signed-off-by: Pali Rohár Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index f240018148f6..67452442e5ec 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -348,7 +348,11 @@ #size-cells = <0>; reg = <5>; - /* ATSHA204A at address 0x64 */ + /* ATSHA204A-MAHDA-T crypto module */ + crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; }; i2c@6 { From a37bc730a572b863253c0244a798127317bd79e0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Apr 2022 12:50:13 +0200 Subject: [PATCH 776/791] ARM: dts: at91: use generic node name for dataflash The node names should be generic, so use "flash" for dataflash nodes and for cfi-flash. Suggested-by: Tudor Ambarus Signed-off-by: Krzysztof Kozlowski Reviewed-by: Tudor Ambarus Acked-by: Nicolas Ferre Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220412105013.249793-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nicolas Ferre --- Documentation/devicetree/bindings/mfd/atmel-flexcom.txt | 2 +- arch/arm/boot/dts/at91rm9200ek.dts | 4 ++-- arch/arm/boot/dts/at91sam9260ek.dts | 2 +- arch/arm/boot/dts/at91sam9261ek.dts | 2 +- arch/arm/boot/dts/at91sam9263ek.dts | 2 +- arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 2 +- arch/arm/boot/dts/at91sam9m10g45ek.dts | 2 +- arch/arm/boot/dts/at91sam9rlek.dts | 2 +- arch/arm/boot/dts/usb_a9263.dts | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt index 692300117c64..9d837535637b 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt @@ -54,7 +54,7 @@ flexcom@f8034000 { clock-names = "spi_clk"; atmel,fifo-size = <32>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at25f512b"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index e1ef4e44e663..4624a6f076f8 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -73,7 +73,7 @@ spi0: spi@fffe0000 { status = "okay"; cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <15000000>; reg = <0>; @@ -94,7 +94,7 @@ status = "okay"; }; - nor_flash@10000000 { + flash@10000000 { compatible = "cfi-flash"; reg = <0x10000000 0x800000>; linux,mtd-name = "physmap-flash.0"; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index ce96345d28a3..6381088ba24f 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -92,7 +92,7 @@ spi0: spi@fffc8000 { cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { + flash@1 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <1>; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index beed819609e8..8f11c0b7d76d 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -145,7 +145,7 @@ cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; status = "okay"; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; reg = <0>; spi-max-frequency = <15000000>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 71f60576761a..42e734020235 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -95,7 +95,7 @@ spi0: spi@fffa4000 { status = "okay"; cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 87bb39060e8b..74b90dc58cbf 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -110,7 +110,7 @@ spi0: spi@fffc8000 { cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { + flash@1 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <1>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index b6256a20fbc7..e5db198a87a8 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -167,7 +167,7 @@ spi0: spi@fffa4000{ status = "okay"; cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <13000000>; reg = <0>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 62981b39c815..d74b8d9d84aa 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -180,7 +180,7 @@ spi0: spi@fffcc000 { status = "okay"; cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <15000000>; reg = <0>; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 8a0cfbfd0c45..b6cb9cdf8197 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -60,7 +60,7 @@ spi0: spi@fffa4000 { cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; status = "okay"; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; reg = <0>; spi-max-frequency = <15000000>; From b7e86ef7afd128577ff7bb0db0ae82d27d7ed7ad Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 3 May 2022 16:31:27 +0300 Subject: [PATCH 777/791] ARM: dts: at91: sama7g5: remove interrupt-parent from gic node interrupt-parent is not to be used as a boolean property. It is already present in the DT in the proper way it's supposed to be used: interrupt-parent = <&gic>; This is also reported by dtbs_check: arch/arm/boot/dts/at91-sama7g5ek.dtb: interrupt-controller@e8c11000: interrupt-parent: True is not of type 'array' From schema: /.local/lib/python3.8/site-packages/dtschema/schemas/interrupts.yaml Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Eugen Hristev Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220503133127.64320-1-eugen.hristev@microchip.com Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama7g5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 4decd3a91a76..5cb9bd2ca5e8 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -857,7 +857,6 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - interrupt-parent; reg = <0xe8c11000 0x1000>, <0xe8c12000 0x2000>; }; From 47afe2b524b8ed69c95d745a36b13e58cdafc656 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 20 Apr 2022 21:42:30 +0200 Subject: [PATCH 778/791] ARM: dts: lan966x: rename pinctrl nodes The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220420194230.3415663-1-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts index 3281af90ac6d..3c7e3a7d6f14 100644 --- a/arch/arm/boot/dts/lan966x-pcb8291.dts +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -35,7 +35,7 @@ function = "fc3_b"; }; - can0_b_pins: can0_b_pins { + can0_b_pins: can0-b-pins { /* RX, TX */ pins = "GPIO_35", "GPIO_36"; function = "can0_b"; From 8b4092fd0c1a0aaa985413c43b027f87dd457207 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:15 +0200 Subject: [PATCH 779/791] ARM: dts: lan966x: swap dma channels for crypto node The YAML binding (crypto/atmel,at91sam9g46-aes.yaml) mandates the order of the channels. Swap them to pass devicetree validation. Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291") Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-2-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 7d2869648050..5e9cbc8cdcbc 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -114,9 +114,9 @@ compatible = "atmel,at91sam9g46-aes"; reg = <0xe004c000 0x100>; interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, - <&dma0 AT91_XDMAC_DT_PERID(12)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "aes_clk"; }; From 153dd52cb278454687ce49372ee9ff032dce8778 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:16 +0200 Subject: [PATCH 780/791] ARM: dts: lan966x: add sgpio node Add the device tree node for the SGPIO IP block reused from the SparX-5. Keep the node disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-3-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 5e9cbc8cdcbc..39dfdb8e29ed 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -223,6 +223,32 @@ #interrupt-cells = <2>; }; + sgpio: gpio@e2004190 { + compatible = "microchip,sparx5-sgpio"; + reg = <0xe2004190 0x118>; + clocks = <&sys_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgpio_in: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sgpio_out: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + }; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; From 99a5f1cbd4bd2c309b3baf1cd7351424171f8905 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:17 +0200 Subject: [PATCH 781/791] ARM: dts: lan966x: add missing uart DMA channel The usart node of the flexcom3 block is missing the DMA channels. Add it. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-4-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 39dfdb8e29ed..230de3bdd5f1 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -144,6 +144,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; From 1e17387a30554c3631faad46a95ab85bfc19d2cc Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:18 +0200 Subject: [PATCH 782/791] ARM: dts: lan966x: add all flexcom usart nodes Add all the remaining usart nodes for the flexcom block. Although the DMA channels are specified, DMA is not enabled by default because break detection doesn't work with DMA. Keep the nodes disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-5-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 230de3bdd5f1..d7eacb0144f5 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -92,6 +92,19 @@ #size-cells = <1>; ranges = <0x0 0xe0040000 0x800>; status = "disabled"; + + usart0: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -102,6 +115,19 @@ #size-cells = <1>; ranges = <0x0 0xe0044000 0x800>; status = "disabled"; + + usart1: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -129,6 +155,19 @@ #size-cells = <1>; ranges = <0x0 0xe0060000 0x800>; status = "disabled"; + + usart2: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -181,6 +220,19 @@ #size-cells = <1>; ranges = <0x0 0xe0070000 0x800>; status = "disabled"; + + usart4: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; timer0: timer@e008c000 { From 8c38c72c29eb1807d2419bf301e0c07913a16ad4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:19 +0200 Subject: [PATCH 783/791] ARM: dts: lan966x: add flexcom SPI nodes Add all the SPI nodes for the flexcom IP block. Keep them disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-6-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index d7eacb0144f5..a61d394ad04d 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -105,6 +105,21 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi0: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -128,6 +143,21 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi1: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -168,6 +198,21 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -191,6 +236,21 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; dma0: dma-controller@e0068000 { @@ -233,6 +293,21 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; timer0: timer@e008c000 { From 66fc5fedb2bedcee72b5279e5a74ceb2d1ec883a Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:20 +0200 Subject: [PATCH 784/791] ARM: dts: lan966x: add flexcom I2C nodes Add all I2C nodes of the flexcom IP blocks. The driver supports FIFO, DMA or both combined. But the latter isn't working correctly. Thus, skip the fifo-size property for now. DMA is doing single byte reads in this case. Keep the nodes disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-7-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index a61d394ad04d..95d58bdca3f0 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -120,6 +120,19 @@ #size-cells = <0>; status = "disabled"; }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -158,6 +171,19 @@ #size-cells = <0>; status = "disabled"; }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -213,6 +239,19 @@ #size-cells = <0>; status = "disabled"; }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -251,6 +290,19 @@ #size-cells = <0>; status = "disabled"; }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; dma0: dma-controller@e0068000 { @@ -308,6 +360,19 @@ #size-cells = <0>; status = "disabled"; }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; timer0: timer@e008c000 { From 79d83b3a458eaebb98033424e035cb9091291c68 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 12 May 2022 11:12:46 +0300 Subject: [PATCH 785/791] ARM: dts: lan966x: add basic Kontron KSwitch D10 support Add basic support for the Kontron KSwitch D10 MMT. It comes in two variants: "6G-2GS" which features 6 Gigabit copper ports and two SFP cages and "8G" which features 6 Gigbabit copper ports (where two are 2.5G capable). For now the following is supported and working: - Kernel console - SFP cages - SPI - SGPIO - Watchdog Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur [claudiu.beznea: fixed conflict on Makefile] Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-8-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/Makefile | 4 +- ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 78 ++++++++++++++++ .../lan966x-kontron-kswitch-d10-mmt-8g.dts | 13 +++ .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 93 +++++++++++++++++++ 4 files changed, 187 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..54beef7c1810 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -742,7 +742,9 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb dtb-$(CONFIG_SOC_LAN966) += \ - lan966x-pcb8291.dtb + lan966x-pcb8291.dtb \ + lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ + lan966x-kontron-kswitch-d10-mmt-8g.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts new file mode 100644 index 000000000000..7b12cbe11c58 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 6G-2GS"; + compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; + + aliases { + i2c0 = &i2c4; + i2c1 = &i2c1; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c4>; + los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&flx1 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c1: i2c@600 { + pinctrl-0 = <&fc1_c_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c4: i2c@600 { + pinctrl-0 = <&fc4_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&gpio { + fc1_c_pins: fc1-c-i2c-pins { + /* SCL, SDA */ + pins = "GPIO_47", "GPIO_48"; + function = "fc1_c"; + }; + + fc4_b_pins: fc4-b-i2c-pins { + /* SCL, SDA */ + pins = "GPIO_57", "GPIO_58"; + function = "fc4_b"; + }; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts new file mode 100644 index 000000000000..4b35f6c46e7f --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 8G + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 8G"; + compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi new file mode 100644 index 000000000000..4c1ebb4aa5b0 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common part of the device tree for the Kontron KSwitch D10 MMT + */ + +/dts-v1/; +#include "lan966x.dtsi" + +/ { + aliases { + serial0 = &usart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; + + usart0: serial@200 { + pinctrl-0 = <&usart0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + spi3: spi@400 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* SCK, MISO, MOSI */ + pins = "GPIO_51", "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1 */ + pins = "GPIO_32", "GPIO_33", "GPIO_34"; + function = "sgpio_a"; + }; + + sgpio_b_pins: sgpio-b-pins { + /* LD */ + pins = "GPIO_64"; + function = "sgpio_b"; + }; + + usart0_pins: usart0-pins { + /* RXD, TXD */ + pins = "GPIO_25", "GPIO_26"; + function = "fc0_b"; + }; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>; + pinctrl-names = "default"; + bus-frequency = <8000000>; + /* arbitrary range because all GPIOs are in software mode */ + microchip,sgpio-port-ranges = <0 11>; + status = "okay"; + + sgpio_in: gpio@0 { + ngpios = <128>; + }; + + sgpio_out: gpio@1 { + ngpios = <128>; + }; +}; + +&watchdog { + status = "okay"; +}; From 63f295940d1afd88ec6704a3d50a6e87a8a1c45f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:22 +0200 Subject: [PATCH 786/791] ARM: dts: lan966x: add hwmon node Add the monitoring node which covers the temperature sensor as well as the PWM controller and the FAN tacho input. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-9-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 95d58bdca3f0..140bdeb9d4fd 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -444,6 +444,14 @@ }; }; + hwmon: hwmon@e2010180 { + compatible = "microchip,lan9668-hwmon"; + reg = <0xe2010180 0xc>, + <0xe20042a8 0xc>; + reg-names = "pvt", "fan"; + clocks = <&sys_clk>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; From 6ad69e07def67c95e677a747d5320f2f734fd583 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:23 +0200 Subject: [PATCH 787/791] ARM: dts: lan966x: add MIIM nodes Add the MDIO controller nodes. The integrated PHYs are connected to the second controller. This controller also takes care of the resets of the integrated PHYs, thus it has two memory regions. The first controller is routed to the external MDIO/MDC pins. By default, they are disabled. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-10-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 140bdeb9d4fd..786655b65dc5 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -418,6 +418,37 @@ #interrupt-cells = <2>; }; + mdio0: mdio@e2004118 { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe2004118 0x24>; + clocks = <&sys_clk>; + status = "disabled"; + }; + + mdio1: mdio@e200413c { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe200413c 0x24>, + <0xe2010020 0x4>; + clocks = <&sys_clk>; + status = "disabled"; + + phy0: ethernet-phy@1 { + reg = <1>; + interrupts = ; + status = "disabled"; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + interrupts = ; + status = "disabled"; + }; + }; + sgpio: gpio@e2004190 { compatible = "microchip,sparx5-sgpio"; reg = <0xe2004190 0x118>; From ff85a7a9dedb6c876974ae20ff0c902a9247dae8 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:24 +0200 Subject: [PATCH 788/791] ARM: dts: lan966x: add reset switch reset node Add the switch reset node which will later be used by the switch driver. The switch reset also resets the GPIO controller and the SGPIO controller, thus it also has to be connectected to these nodes. This way the reset will only issued once for the first device requesting the reset. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-11-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 786655b65dc5..238b4dfccaa2 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -391,6 +391,11 @@ status = "disabled"; }; + cpu_ctrl: syscon@e00c0000 { + compatible = "microchip,lan966x-cpu-syscon", "syscon"; + reg = <0xe00c0000 0x350>; + }; + can0: can@e081c000 { compatible = "bosch,m_can"; reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; @@ -406,10 +411,20 @@ status = "disabled"; }; + reset: reset-controller@e200400c { + compatible = "microchip,lan966x-switch-reset"; + reg = <0xe200400c 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + gpio: pinctrl@e2004064 { compatible = "microchip,lan966x-pinctrl"; reg = <0xe2004064 0xb4>, <0xe2010024 0x138>; + resets = <&reset 0>; + reset-names = "switch"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 78>; @@ -453,6 +468,8 @@ compatible = "microchip,sparx5-sgpio"; reg = <0xe2004190 0x118>; clocks = <&sys_clk>; + resets = <&reset 0>; + reset-names = "switch"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 4d2a87042e9fed35b5bf5d92d1955a197697aa6f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:25 +0200 Subject: [PATCH 789/791] ARM: dts: lan966x: add serdes node Add the SerDes node. On the LAN966x SoC these SerDes are used to connect network PHYs. By default, that node is disabled. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-12-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 238b4dfccaa2..92f9e2835fad 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -500,6 +500,14 @@ clocks = <&sys_clk>; }; + serdes: serdes@e202c000 { + compatible = "microchip,lan966x-serdes"; + reg = <0xe202c000 0x9c>, + <0xe2004010 0x4>; + #phy-cells = <2>; + status = "disabled"; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; From 2952d32c061140f9c573f65d5361d0faff164d76 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:26 +0200 Subject: [PATCH 790/791] ARM: dts: lan966x: add switch node Add the switch node and its 8 children ports. All are disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-13-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 62 ++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 92f9e2835fad..3cb02fffe716 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -84,6 +84,68 @@ #size-cells = <1>; ranges; + switch: switch@e0000000 { + compatible = "microchip,lan966x-switch"; + reg = <0xe0000000 0x0100000>, + <0xe2000000 0x0800000>; + reg-names = "cpu", "gcb"; + interrupts = , + , + , + , + ; + interrupt-names = "xtr", "fdma", "ana", "ptp", + "ptp-ext"; + resets = <&reset 0>; + reset-names = "switch"; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + port4: port@4 { + reg = <4>; + status = "disabled"; + }; + + port5: port@5 { + reg = <5>; + status = "disabled"; + }; + + port6: port@6 { + reg = <6>; + status = "disabled"; + }; + + port7: port@7 { + reg = <7>; + status = "disabled"; + }; + }; + }; + flx0: flexcom@e0040000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0040000 0x100>; From 46a9556d977e290a18890fb4cf07d19b0da16f31 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:27 +0200 Subject: [PATCH 791/791] ARM: dts: kswitch-d10: enable networking Enable all the necessary network related nodes, wire the pinctrl configurations, add the PHYs and connect them to the corresponding network ports. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-14-michael@walle.cc Signed-off-by: Nicolas Ferre --- ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 16 +++ .../lan966x-kontron-kswitch-d10-mmt-8g.dts | 26 +++++ .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 97 +++++++++++++++++++ 3 files changed, 139 insertions(+) diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts index 7b12cbe11c58..0f555eb45bda 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts @@ -76,3 +76,19 @@ function = "fc4_b"; }; }; + +&port2 { + phys = <&serdes 2 SERDES6G(0)>; + sfp = <&sfp0>; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; +}; + +&port3 { + phys = <&serdes 3 SERDES6G(1)>; + sfp = <&sfp1>; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts index 4b35f6c46e7f..5feef9a59a79 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts @@ -11,3 +11,29 @@ compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921", "microchip,lan9668", "microchip,lan966"; }; + +&mdio0 { + phy2: ethernet-phy@3 { + reg = <3>; + }; + + phy3: ethernet-phy@4 { + reg = <4>; + }; +}; + +&port2 { + phys = <&serdes 2 SERDES6G(0)>; + phy-handle = <&phy2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&port3 { + phys = <&serdes 3 SERDES6G(1)>; + phy-handle = <&phy3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi index 4c1ebb4aa5b0..4cab1b3b3b29 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" / { aliases { @@ -52,6 +53,12 @@ function = "fc3_b"; }; + miim_c_pins: miim-c-pins { + /* MDC, MDIO */ + pins = "GPIO_59", "GPIO_60"; + function = "miim_c"; + }; + sgpio_a_pins: sgpio-a-pins { /* SCK, D0, D1 */ pins = "GPIO_32", "GPIO_33", "GPIO_34"; @@ -71,6 +78,92 @@ }; }; +&mdio0 { + pinctrl-0 = <&miim_c_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + clock-frequency = <2500000>; + status = "okay"; + + phy4: ethernet-phy@5 { + reg = <5>; + coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + }; + + phy5: ethernet-phy@6 { + reg = <6>; + coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + }; + + phy6: ethernet-phy@7 { + reg = <7>; + coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + }; + + phy7: ethernet-phy@8 { + reg = <8>; + coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phys = <&serdes 0 CU(0)>; + phy-handle = <&phy0>; + phy-mode = "gmii"; + status = "okay"; +}; + +&port1 { + phys = <&serdes 1 CU(1)>; + phy-handle = <&phy1>; + phy-mode = "gmii"; + status = "okay"; +}; + +&port4 { + phys = <&serdes 4 SERDES6G(2)>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port5 { + phys = <&serdes 5 SERDES6G(2)>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port6 { + phys = <&serdes 6 SERDES6G(2)>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port7 { + phys = <&serdes 7 SERDES6G(2)>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + &sgpio { pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>; pinctrl-names = "default"; @@ -88,6 +181,10 @@ }; }; +&switch { + status = "okay"; +}; + &watchdog { status = "okay"; };