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clk: qcom: Add support for setting rates on PLLs
Some PLLs may require changing their rate at runtime. Add support for these PLLs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -97,7 +97,7 @@ static unsigned long
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clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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u32 l, m, n;
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u32 l, m, n, config;
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unsigned long rate;
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u64 tmp;
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@ -116,13 +116,79 @@ clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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do_div(tmp, n);
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rate += tmp;
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}
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if (pll->post_div_width) {
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regmap_read(pll->clkr.regmap, pll->config_reg, &config);
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config >>= pll->post_div_shift;
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config &= BIT(pll->post_div_width) - 1;
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rate /= config + 1;
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}
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return rate;
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}
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static const
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struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
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{
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if (!f)
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return NULL;
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for (; f->freq; f++)
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if (rate <= f->freq)
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return f;
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return NULL;
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}
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static long
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clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *p_rate, struct clk **p)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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const struct pll_freq_tbl *f;
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f = find_freq(pll->freq_tbl, rate);
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if (!f)
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return clk_pll_recalc_rate(hw, *p_rate);
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return f->freq;
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}
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static int
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clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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const struct pll_freq_tbl *f;
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bool enabled;
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u32 mode;
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u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
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f = find_freq(pll->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
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enabled = (mode & enable_mask) == enable_mask;
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if (enabled)
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clk_pll_disable(hw);
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regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
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regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
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regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
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regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
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if (enabled)
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clk_pll_enable(hw);
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return 0;
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}
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const struct clk_ops clk_pll_ops = {
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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.recalc_rate = clk_pll_recalc_rate,
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.determine_rate = clk_pll_determine_rate,
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.set_rate = clk_pll_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_pll_ops);
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@ -17,6 +17,21 @@
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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/**
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* struct pll_freq_tbl - PLL frequency table
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* @l: L value
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* @m: M value
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* @n: N value
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* @ibits: internal values
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*/
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struct pll_freq_tbl {
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unsigned long freq;
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u16 l;
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u16 m;
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u16 n;
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u32 ibits;
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};
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/**
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* struct clk_pll - phase locked loop (PLL)
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* @l_reg: L register
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@ -26,6 +41,7 @@
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* @mode_reg: mode register
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* @status_reg: status register
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* @status_bit: ANDed with @status_reg to determine if PLL is enabled
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* @freq_tbl: PLL frequency table
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* @hw: handle between common and hardware-specific interfaces
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*/
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struct clk_pll {
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@ -36,6 +52,10 @@ struct clk_pll {
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u32 mode_reg;
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u32 status_reg;
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u8 status_bit;
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u8 post_div_width;
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u8 post_div_shift;
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const struct pll_freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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