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Display support for rk3228/rk3229 (up to hdmi output) and more love
for rk3288-veyron boards. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl0Z0DEQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgbHRB/40x1DBDesIZnjpbnFPTBGcqhMXgc/tfawK jtU7fwFiToyvXXzauY877+njhC54MCwF9JhtRfxn0c5O7WRBCnZnzRIfQpqKxdXD VmIx5cKMI057oG0p4RB9tSDTHNAfg0lw9M9DQVw4f/Yl2M0kY/yk3TnL2vReMxMQ mGd0j8KDAHnpdBgYpKQPSxQdbV8i5EFkb0RcvrEZ/VPHrikg74y91nbgSjBu3EgI +NecSglseOG+SVzPzxbnU1kZ4E7Z/zXq6UQmpoVw2710MNn+QWrd1+F7bAcnszaO KJCdHRM8Icpx9mNnekjonzYuNWOAEZf+LFS2FncR6qjrzFgBWi7c =8Tz/ -----END PGP SIGNATURE----- Merge tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Display support for rk3228/rk3229 (up to hdmi output) and more love for rk3288-veyron boards. * tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add display nodes for rk322x ARM: dts: rockchip: fix vop iommu-cells on rk322x clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie" ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
adfbb80d38
@ -143,6 +143,11 @@
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#clock-cells = <0>;
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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};
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i2s1: i2s1@100b0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100b0000 0x4000>;
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@ -529,6 +534,17 @@
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status = "disabled";
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};
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hdmi_phy: hdmi-phy@12030000 {
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compatible = "rockchip,rk3228-hdmi-phy";
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reg = <0x12030000 0x10000>;
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clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
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clock-names = "sysclk", "refoclk", "refpclk";
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#clock-cells = <0>;
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clock-output-names = "hdmiphy_phy";
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#phy-cells = <0>;
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status = "disabled";
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};
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gpu: gpu@20000000 {
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compatible = "rockchip,rk3228-mali", "arm,mali-400";
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reg = <0x20000000 0x10000>;
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@ -572,6 +588,28 @@
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status = "disabled";
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};
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vop: vop@20050000 {
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compatible = "rockchip,rk3228-vop";
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reg = <0x20050000 0x1ffc>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vop_mmu>;
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status = "disabled";
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vop_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vop_out_hdmi: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&hdmi_in_vop>;
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};
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};
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};
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vop_mmu: iommu@20053f00 {
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compatible = "rockchip,iommu";
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reg = <0x20053f00 0x100>;
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@ -579,7 +617,7 @@
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interrupt-names = "vop_mmu";
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clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk", "iface";
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iommu-cells = <0>;
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#iommu-cells = <0>;
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status = "disabled";
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};
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@ -594,6 +632,36 @@
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status = "disabled";
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};
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hdmi: hdmi@200a0000 {
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compatible = "rockchip,rk3228-dw-hdmi";
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reg = <0x200a0000 0x20000>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&cru SCLK_HDMI_PHY>;
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assigned-clock-parents = <&hdmi_phy>;
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clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
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clock-names = "isfr", "iahb", "cec";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
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resets = <&cru SRST_HDMI_P>;
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reset-names = "hdmi";
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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rockchip,grf = <&grf>;
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status = "disabled";
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ports {
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hdmi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_vop: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vop_out_hdmi>;
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};
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};
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};
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};
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sdmmc: dwmmc@30000000 {
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compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x30000000 0x4000>;
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@ -922,6 +990,21 @@
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};
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};
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hdmi {
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hdmi_hpd: hdmi-hpd {
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rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
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};
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hdmii2c_xfer: hdmii2c-xfer {
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rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
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<0 RK_PA7 2 &pcfg_pull_none>;
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};
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hdmi_cec: hdmi-cec {
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rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
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@ -237,6 +237,7 @@
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/* Wake only */
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&suspend_l_wake
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&bt_dev_wake_awake
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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@ -246,6 +247,7 @@
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/* Sleep only */
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&suspend_l_sleep
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&bt_dev_wake_sleep
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>;
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backlight {
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@ -106,8 +106,6 @@
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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power-supply = <&backlight_regulator>;
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post-pwm-on-delay-ms = <200>;
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pwm-off-delay-ms = <200>;
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};
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&i2c_tunnel {
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@ -23,6 +23,31 @@
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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bt_activity: bt-activity {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&bt_host_wake>;
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/*
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* HACK: until we have an LPM driver, we'll use an
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* ugly GPIO key to allow Bluetooth to wake from S3.
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* This is expected to only be used by BT modules that
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* use UART for comms. For BT modules that talk over
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* SDIO we should use a wakeup mechanism related to SDIO.
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*
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* Use KEY_RESERVED here since that will work as a wakeup but
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* doesn't get reported to higher levels (so doesn't confuse
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* Chrome).
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*/
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bt-wake {
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label = "BT Wakeup";
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gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_RESERVED>;
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wakeup-source;
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};
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};
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power_button: power-button {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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@ -460,12 +485,18 @@
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&ddr0_retention
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&ddrio_pwroff
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&global_pwroff
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/* Wake only */
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&bt_dev_wake_awake
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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&ddr0_retention
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&ddrio_pwroff
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&global_pwroff
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/* Sleep only */
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&bt_dev_wake_sleep
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>;
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pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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@ -549,6 +580,10 @@
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rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bt_host_wake: bt-host-wake {
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rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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/*
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* We run sdio0 at max speed; bump up drive strength.
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* We also have external pulls, so disable the internal ones.
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@ -567,6 +602,20 @@
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sdio0_clk: sdio0-clk {
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rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
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};
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/*
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* These pins are only present on very new veyron boards; on
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* older boards bt_dev_wake is simply always high. Note that
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* gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
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* to map this pin everywhere
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*/
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bt_dev_wake_sleep: bt-dev-wake-sleep {
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rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
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};
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bt_dev_wake_awake: bt-dev-wake-awake {
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rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
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};
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};
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tpm {
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@ -64,6 +64,7 @@
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#define SCLK_WIFI 141
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#define SCLK_OTGPHY0 142
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#define SCLK_OTGPHY1 143
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#define SCLK_HDMI_PHY 144
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/* dclk gates */
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#define DCLK_VOP 190
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@ -164,6 +164,7 @@
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#define PCLK_DCF 233
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#define PCLK_SARADC 234
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#define PCLK_ACODECPHY 235
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#define PCLK_WDT 236
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/* hclk gates */
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#define HCLK_PERI 308
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