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drm/nouveau/pwr: tidy

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-06-12 18:31:32 +10:00
parent 3d50d4dcb0
commit adec9bc3bd
12 changed files with 133 additions and 193 deletions
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2
drivers/gpu/drm/nouveau/core/engine/device/gm100.c
View File

@ -78,7 +78,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

8
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
View File

@ -350,7 +350,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@ -380,7 +380,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@ -409,7 +409,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
@ -438,7 +438,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;

16
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
View File

@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@ -107,7 +107,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@ -139,7 +139,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@ -170,7 +170,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@ -202,7 +202,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@ -234,7 +234,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@ -265,7 +265,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
@ -297,7 +297,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;

12
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
View File

@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@ -108,7 +108,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@ -141,7 +141,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@ -191,7 +191,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@ -224,7 +224,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
@ -257,7 +257,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;

39
drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
View File

@ -7,18 +7,6 @@
struct nouveau_pwr {
struct nouveau_subdev base;
struct {
u32 limit;
u32 *data;
u32 size;
} code;
struct {
u32 limit;
u32 *data;
u32 size;
} data;
struct {
u32 base;
u32 size;
@ -44,29 +32,10 @@ nouveau_pwr(void *obj)
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR];
}
#define nouveau_pwr_create(p, e, o, d) \
nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_pwr_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_pwr_init(p) ({ \
struct nouveau_pwr *ppwr = (p); \
_nouveau_pwr_init(nv_object(ppwr)); \
})
#define nouveau_pwr_fini(p,s) ({ \
struct nouveau_pwr *ppwr = (p); \
_nouveau_pwr_fini(nv_object(ppwr), (s)); \
})
int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
#define _nouveau_pwr_dtor _nouveau_subdev_dtor
int _nouveau_pwr_init(struct nouveau_object *);
int _nouveau_pwr_fini(struct nouveau_object *, bool);
extern struct nouveau_oclass nva3_pwr_oclass;
extern struct nouveau_oclass nvc0_pwr_oclass;
extern struct nouveau_oclass nvd0_pwr_oclass;
extern struct nouveau_oclass nv108_pwr_oclass;
extern struct nouveau_oclass *nva3_pwr_oclass;
extern struct nouveau_oclass *nvc0_pwr_oclass;
extern struct nouveau_oclass *nvd0_pwr_oclass;
extern struct nouveau_oclass *nv108_pwr_oclass;
/* interface to MEMX process running on PPWR */
struct nouveau_memx;

24
drivers/gpu/drm/nouveau/core/subdev/pwr/base.c
View File

@ -22,9 +22,10 @@
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include <subdev/timer.h>
#include "priv.h"
static int
nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
u32 process, u32 message, u32 data0, u32 data1)
@ -177,6 +178,7 @@ _nouveau_pwr_fini(struct nouveau_object *object, bool suspend)
int
_nouveau_pwr_init(struct nouveau_object *object)
{
const struct nvkm_pwr_impl *impl = (void *)object->oclass;
struct nouveau_pwr *ppwr = (void *)object;
int ret, i;
@ -195,15 +197,15 @@ _nouveau_pwr_init(struct nouveau_object *object)
/* upload data segment */
nv_wr32(ppwr, 0x10a1c0, 0x01000000);
for (i = 0; i < ppwr->data.size / 4; i++)
nv_wr32(ppwr, 0x10a1c4, ppwr->data.data[i]);
for (i = 0; i < impl->data.size / 4; i++)
nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]);
/* upload code segment */
nv_wr32(ppwr, 0x10a180, 0x01000000);
for (i = 0; i < ppwr->code.size / 4; i++) {
for (i = 0; i < impl->code.size / 4; i++) {
if ((i & 0x3f) == 0)
nv_wr32(ppwr, 0x10a188, i >> 6);
nv_wr32(ppwr, 0x10a184, ppwr->code.data[i]);
nv_wr32(ppwr, 0x10a184, impl->code.data[i]);
}
/* start it running */
@ -245,3 +247,15 @@ nouveau_pwr_create_(struct nouveau_object *parent,
init_waitqueue_head(&ppwr->recv.wait);
return 0;
}
int
_nouveau_pwr_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_pwr *ppwr;
int ret = nouveau_pwr_create(parent, engine, oclass, &ppwr);
*pobject = nv_object(ppwr);
return ret;
}

3
drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
View File

@ -1,8 +1,7 @@
#ifndef __NVKM_PWR_MEMX_H__
#define __NVKM_PWR_MEMX_H__
#include <subdev/pwr.h>
#include <subdev/pwr/fuc/os.h>
#include "priv.h"
struct nouveau_memx {
struct nouveau_pwr *ppwr;

43
drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c
View File

@ -22,41 +22,20 @@
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "priv.h"
#include "fuc/nv108.fuc.h"
struct nv108_pwr_priv {
struct nouveau_pwr base;
};
static int
nv108_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv108_pwr_priv *priv;
int ret;
ret = nouveau_pwr_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.code.data = nv108_pwr_code;
priv->base.code.size = sizeof(nv108_pwr_code);
priv->base.data.data = nv108_pwr_data;
priv->base.data.size = sizeof(nv108_pwr_data);
return 0;
}
struct nouveau_oclass
nv108_pwr_oclass = {
.handle = NV_SUBDEV(PWR, 0x00),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv108_pwr_ctor,
struct nouveau_oclass *
nv108_pwr_oclass = &(struct nvkm_pwr_impl) {
.base.handle = NV_SUBDEV(PWR, 0x00),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_pwr_ctor,
.dtor = _nouveau_pwr_dtor,
.init = _nouveau_pwr_init,
.fini = _nouveau_pwr_fini,
},
};
.code.data = nv108_pwr_code,
.code.size = sizeof(nv108_pwr_code),
.data.data = nv108_pwr_data,
.data.size = sizeof(nv108_pwr_data),
}.base;

51
drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c
View File

@ -22,50 +22,29 @@
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "priv.h"
#include "fuc/nva3.fuc.h"
struct nva3_pwr_priv {
struct nouveau_pwr base;
};
static int
nva3_pwr_init(struct nouveau_object *object)
{
struct nva3_pwr_priv *priv = (void *)object;
nv_mask(priv, 0x022210, 0x00000001, 0x00000000);
nv_mask(priv, 0x022210, 0x00000001, 0x00000001);
return nouveau_pwr_init(&priv->base);
struct nouveau_pwr *ppwr = (void *)object;
nv_mask(ppwr, 0x022210, 0x00000001, 0x00000000);
nv_mask(ppwr, 0x022210, 0x00000001, 0x00000001);
return nouveau_pwr_init(ppwr);
}
static int
nva3_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nva3_pwr_priv *priv;
int ret;
ret = nouveau_pwr_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.code.data = nva3_pwr_code;
priv->base.code.size = sizeof(nva3_pwr_code);
priv->base.data.data = nva3_pwr_data;
priv->base.data.size = sizeof(nva3_pwr_data);
return 0;
}
struct nouveau_oclass
nva3_pwr_oclass = {
.handle = NV_SUBDEV(PWR, 0xa3),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva3_pwr_ctor,
struct nouveau_oclass *
nva3_pwr_oclass = &(struct nvkm_pwr_impl) {
.base.handle = NV_SUBDEV(PWR, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_pwr_ctor,
.dtor = _nouveau_pwr_dtor,
.init = nva3_pwr_init,
.fini = _nouveau_pwr_fini,
},
};
.code.data = nva3_pwr_code,
.code.size = sizeof(nva3_pwr_code),
.data.data = nva3_pwr_data,
.data.size = sizeof(nva3_pwr_data),
}.base;

43
drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c
View File

@ -22,41 +22,20 @@
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "priv.h"
#include "fuc/nvc0.fuc.h"
struct nvc0_pwr_priv {
struct nouveau_pwr base;
};
static int
nvc0_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_pwr_priv *priv;
int ret;
ret = nouveau_pwr_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.code.data = nvc0_pwr_code;
priv->base.code.size = sizeof(nvc0_pwr_code);
priv->base.data.data = nvc0_pwr_data;
priv->base.data.size = sizeof(nvc0_pwr_data);
return 0;
}
struct nouveau_oclass
nvc0_pwr_oclass = {
.handle = NV_SUBDEV(PWR, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_pwr_ctor,
struct nouveau_oclass *
nvc0_pwr_oclass = &(struct nvkm_pwr_impl) {
.base.handle = NV_SUBDEV(PWR, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_pwr_ctor,
.dtor = _nouveau_pwr_dtor,
.init = _nouveau_pwr_init,
.fini = _nouveau_pwr_fini,
},
};
.code.data = nvc0_pwr_code,
.code.size = sizeof(nvc0_pwr_code),
.data.data = nvc0_pwr_data,
.data.size = sizeof(nvc0_pwr_data),
}.base;

43
drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c
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@ -22,41 +22,20 @@
* Authors: Ben Skeggs
*/
#include <subdev/pwr.h>
#include "priv.h"
#include "fuc/nvd0.fuc.h"
struct nvd0_pwr_priv {
struct nouveau_pwr base;
};
static int
nvd0_pwr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvd0_pwr_priv *priv;
int ret;
ret = nouveau_pwr_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.code.data = nvd0_pwr_code;
priv->base.code.size = sizeof(nvd0_pwr_code);
priv->base.data.data = nvd0_pwr_data;
priv->base.data.size = sizeof(nvd0_pwr_data);
return 0;
}
struct nouveau_oclass
nvd0_pwr_oclass = {
.handle = NV_SUBDEV(PWR, 0xd0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvd0_pwr_ctor,
struct nouveau_oclass *
nvd0_pwr_oclass = &(struct nvkm_pwr_impl) {
.base.handle = NV_SUBDEV(PWR, 0xd0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_pwr_ctor,
.dtor = _nouveau_pwr_dtor,
.init = _nouveau_pwr_init,
.fini = _nouveau_pwr_fini,
},
};
.code.data = nvd0_pwr_code,
.code.size = sizeof(nvd0_pwr_code),
.data.data = nvd0_pwr_data,
.data.size = sizeof(nvd0_pwr_data),
}.base;

42
drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h Normal file
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@ -0,0 +1,42 @@
#ifndef __NVKM_PWR_PRIV_H__
#define __NVKM_PWR_PRIV_H__
#include <subdev/pwr.h>
#include <subdev/pwr/fuc/os.h>
#define nouveau_pwr_create(p, e, o, d) \
nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_pwr_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_pwr_init(p) ({ \
struct nouveau_pwr *_ppwr = (p); \
_nouveau_pwr_init(nv_object(_ppwr)); \
})
#define nouveau_pwr_fini(p,s) ({ \
struct nouveau_pwr *_ppwr = (p); \
_nouveau_pwr_fini(nv_object(_ppwr), (s)); \
})
int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
#define _nouveau_pwr_dtor _nouveau_subdev_dtor
int _nouveau_pwr_init(struct nouveau_object *);
int _nouveau_pwr_fini(struct nouveau_object *, bool);
struct nvkm_pwr_impl {
struct nouveau_oclass base;
struct {
u32 *data;
u32 size;
} code;
struct {
u32 *data;
u32 size;
} data;
};
#endif