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MIPS: Alchemy: Convert dbdma.c to syscore_ops
Convert the PM sysdev to syscore_ops and clean up the ddma addresses a bit. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2351/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
4b5c82b5e5
commit
adcb86279f
@ -36,7 +36,7 @@
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/sysdev.h>
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#include <linux/syscore_ops.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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@ -58,7 +58,8 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
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/* I couldn't find a macro that did this... */
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#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
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static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
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static dbdma_global_t *dbdma_gptr =
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(dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
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static int dbdma_initialized;
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static dbdev_tab_t dbdev_tab[] = {
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@ -299,7 +300,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
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if (ctp != NULL) {
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memset(ctp, 0, sizeof(chan_tab_t));
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ctp->chan_index = chan = i;
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dcp = DDMA_CHANNEL_BASE;
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dcp = KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
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dcp += (0x0100 * chan);
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ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
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cp = (au1x_dma_chan_t *)dcp;
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@ -958,105 +959,75 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
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}
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struct alchemy_dbdma_sysdev {
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struct sys_device sysdev;
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u32 pm_regs[NUM_DBDMA_CHANS + 1][6];
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};
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static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6];
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static int alchemy_dbdma_suspend(struct sys_device *dev,
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pm_message_t state)
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static int alchemy_dbdma_suspend(void)
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{
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struct alchemy_dbdma_sysdev *sdev =
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container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
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int i;
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u32 addr;
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void __iomem *addr;
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addr = DDMA_GLOBAL_BASE;
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sdev->pm_regs[0][0] = au_readl(addr + 0x00);
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sdev->pm_regs[0][1] = au_readl(addr + 0x04);
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sdev->pm_regs[0][2] = au_readl(addr + 0x08);
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sdev->pm_regs[0][3] = au_readl(addr + 0x0c);
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addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
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alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);
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alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);
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alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);
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alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);
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/* save channel configurations */
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for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
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sdev->pm_regs[i][0] = au_readl(addr + 0x00);
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sdev->pm_regs[i][1] = au_readl(addr + 0x04);
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sdev->pm_regs[i][2] = au_readl(addr + 0x08);
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sdev->pm_regs[i][3] = au_readl(addr + 0x0c);
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sdev->pm_regs[i][4] = au_readl(addr + 0x10);
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sdev->pm_regs[i][5] = au_readl(addr + 0x14);
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addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
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for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
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alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);
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alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);
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alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);
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alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);
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alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);
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alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);
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/* halt channel */
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au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00);
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au_sync();
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while (!(au_readl(addr + 0x14) & 1))
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au_sync();
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__raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);
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wmb();
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while (!(__raw_readl(addr + 0x14) & 1))
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wmb();
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addr += 0x100; /* next channel base */
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}
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/* disable channel interrupts */
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au_writel(0, DDMA_GLOBAL_BASE + 0x0c);
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au_sync();
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addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
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__raw_writel(0, addr + 0x0c);
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wmb();
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return 0;
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}
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static int alchemy_dbdma_resume(struct sys_device *dev)
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static void alchemy_dbdma_resume(void)
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{
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struct alchemy_dbdma_sysdev *sdev =
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container_of(dev, struct alchemy_dbdma_sysdev, sysdev);
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int i;
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u32 addr;
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void __iomem *addr;
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addr = DDMA_GLOBAL_BASE;
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au_writel(sdev->pm_regs[0][0], addr + 0x00);
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au_writel(sdev->pm_regs[0][1], addr + 0x04);
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au_writel(sdev->pm_regs[0][2], addr + 0x08);
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au_writel(sdev->pm_regs[0][3], addr + 0x0c);
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addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
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__raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);
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__raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);
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__raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);
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__raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);
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/* restore channel configurations */
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for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) {
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au_writel(sdev->pm_regs[i][0], addr + 0x00);
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au_writel(sdev->pm_regs[i][1], addr + 0x04);
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au_writel(sdev->pm_regs[i][2], addr + 0x08);
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au_writel(sdev->pm_regs[i][3], addr + 0x0c);
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au_writel(sdev->pm_regs[i][4], addr + 0x10);
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au_writel(sdev->pm_regs[i][5], addr + 0x14);
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au_sync();
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addr = (void __iomem *)KSEG1ADDR(AU1550_DBDMA_PHYS_ADDR);
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for (i = 1; i <= NUM_DBDMA_CHANS; i++) {
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__raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);
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__raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);
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__raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);
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__raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);
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__raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);
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__raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);
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wmb();
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addr += 0x100; /* next channel base */
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}
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return 0;
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}
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static struct sysdev_class alchemy_dbdma_sysdev_class = {
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.name = "dbdma",
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static struct syscore_ops alchemy_dbdma_syscore_ops = {
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.suspend = alchemy_dbdma_suspend,
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.resume = alchemy_dbdma_resume,
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};
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static int __init alchemy_dbdma_sysdev_init(void)
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{
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struct alchemy_dbdma_sysdev *sdev;
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int ret;
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ret = sysdev_class_register(&alchemy_dbdma_sysdev_class);
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if (ret)
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return ret;
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sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL);
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if (!sdev)
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return -ENOMEM;
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sdev->sysdev.id = -1;
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sdev->sysdev.cls = &alchemy_dbdma_sysdev_class;
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ret = sysdev_register(&sdev->sysdev);
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if (ret)
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kfree(sdev);
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return ret;
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}
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static int __init au1xxx_dbdma_init(void)
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{
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int irq_nr, ret;
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@ -1084,11 +1055,7 @@ static int __init au1xxx_dbdma_init(void)
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else {
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dbdma_initialized = 1;
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printk(KERN_INFO "Alchemy DBDMA initialized\n");
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ret = alchemy_dbdma_sysdev_init();
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if (ret) {
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printk(KERN_ERR "DBDMA PM init failed\n");
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ret = 0;
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}
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register_syscore_ops(&alchemy_dbdma_syscore_ops);
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}
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return ret;
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@ -635,6 +635,8 @@ enum soc_au1200_ints {
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#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
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#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
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#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
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#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
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#ifdef CONFIG_SOC_AU1000
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@ -761,7 +763,6 @@ enum soc_au1200_ints {
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#define UART3_PHYS_ADDR 0x11400000
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define DDMA_PHYS_ADDR 0x14002000
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#define PE_PHYS_ADDR 0x14008000
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#define PSC0_PHYS_ADDR 0x11A00000
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#define PSC1_PHYS_ADDR 0x11B00000
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@ -789,7 +790,6 @@ enum soc_au1200_ints {
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#define UART1_PHYS_ADDR 0x11200000
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define DDMA_PHYS_ADDR 0x14002000
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#define PSC0_PHYS_ADDR 0x11A00000
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#define PSC1_PHYS_ADDR 0x11B00000
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#define SD0_PHYS_ADDR 0x10600000
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@ -37,14 +37,6 @@
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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* The DMA base addresses.
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* The channels are every 256 bytes (0x0100) from the channel 0 base.
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* Interrupt status/enable is bits 15:0 for channels 15 to zero.
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*/
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#define DDMA_GLOBAL_BASE 0xb4003000
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#define DDMA_CHANNEL_BASE 0xb4002000
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typedef volatile struct dbdma_global {
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u32 ddma_config;
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u32 ddma_intstat;
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