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iio: adc: ad9467: add support AD9467 ADC
The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC). It is optimized for high performanceover wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range. The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. Since the chip can operate at such high sample-rates (much higher than classical interfaces), it requires that a DMA controller be used to interface directly to the chip and push data into memory. Typically, the AXI ADC IP core is used to interface with it. Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Michael Hennerich
Jonathan Cameron
parent
96553a44e9
commit
ad67971202
@ -246,6 +246,21 @@ config AD799X
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To compile this driver as a module, choose M here: the module will be
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called ad799x.
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config AD9467
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tristate "Analog Devices AD9467 High Speed ADC driver"
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depends on SPI
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select ADI_AXI_ADC
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help
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Say yes here to build support for Analog Devices:
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* AD9467 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter
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The driver requires the assistance of the AXI ADC IP core to operate,
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since SPI is used for configuration only, while data has to be
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streamed into memory via DMA.
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To compile this driver as a module, choose M here: the module will be
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called ad9467.
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config ADI_AXI_ADC
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tristate "Analog Devices Generic AXI ADC IP core driver"
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select IIO_BUFFER
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@ -26,6 +26,7 @@ obj-$(CONFIG_AD7793) += ad7793.o
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obj-$(CONFIG_AD7887) += ad7887.o
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obj-$(CONFIG_AD7949) += ad7949.o
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obj-$(CONFIG_AD799X) += ad799x.o
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obj-$(CONFIG_AD9467) += ad9467.o
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obj-$(CONFIG_ADI_AXI_ADC) += adi-axi-adc.o
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obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
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obj-$(CONFIG_AT91_ADC) += at91_adc.o
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422
drivers/iio/adc/ad9467.c
Normal file
422
drivers/iio/adc/ad9467.c
Normal file
@ -0,0 +1,422 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Analog Devices AD9467 SPI ADC driver
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*
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* Copyright 2012-2020 Analog Devices Inc.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/of_device.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/clk.h>
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#include <linux/iio/adc/adi-axi-adc.h>
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/*
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* ADI High-Speed ADC common spi interface registers
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* See Application-Note AN-877:
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* https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
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*/
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#define AN877_ADC_REG_CHIP_PORT_CONF 0x00
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#define AN877_ADC_REG_CHIP_ID 0x01
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#define AN877_ADC_REG_CHIP_GRADE 0x02
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#define AN877_ADC_REG_CHAN_INDEX 0x05
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#define AN877_ADC_REG_TRANSFER 0xFF
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#define AN877_ADC_REG_MODES 0x08
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#define AN877_ADC_REG_TEST_IO 0x0D
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#define AN877_ADC_REG_ADC_INPUT 0x0F
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#define AN877_ADC_REG_OFFSET 0x10
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#define AN877_ADC_REG_OUTPUT_MODE 0x14
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#define AN877_ADC_REG_OUTPUT_ADJUST 0x15
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#define AN877_ADC_REG_OUTPUT_PHASE 0x16
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#define AN877_ADC_REG_OUTPUT_DELAY 0x17
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#define AN877_ADC_REG_VREF 0x18
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#define AN877_ADC_REG_ANALOG_INPUT 0x2C
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/* AN877_ADC_REG_TEST_IO */
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#define AN877_ADC_TESTMODE_OFF 0x0
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#define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1
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#define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2
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#define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3
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#define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4
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#define AN877_ADC_TESTMODE_PN23_SEQ 0x5
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#define AN877_ADC_TESTMODE_PN9_SEQ 0x6
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#define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7
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#define AN877_ADC_TESTMODE_USER 0x8
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#define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9
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#define AN877_ADC_TESTMODE_SYNC 0xA
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#define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB
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#define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC
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#define AN877_ADC_TESTMODE_RAMP 0xF
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/* AN877_ADC_REG_TRANSFER */
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#define AN877_ADC_TRANSFER_SYNC 0x1
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/* AN877_ADC_REG_OUTPUT_MODE */
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#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
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#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1
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#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2
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/* AN877_ADC_REG_OUTPUT_PHASE */
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#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20
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#define AN877_ADC_INVERT_DCO_CLK 0x80
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/* AN877_ADC_REG_OUTPUT_DELAY */
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#define AN877_ADC_DCO_DELAY_ENABLE 0x80
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/*
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* Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
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*/
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#define CHIPID_AD9467 0x50
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#define AD9467_DEF_OUTPUT_MODE 0x08
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#define AD9467_REG_VREF_MASK 0x0F
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enum {
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ID_AD9467,
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};
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struct ad9467_state {
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struct spi_device *spi;
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struct clk *clk;
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unsigned int output_mode;
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struct gpio_desc *pwrdown_gpio;
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struct gpio_desc *reset_gpio;
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};
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static int ad9467_spi_read(struct spi_device *spi, unsigned int reg)
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{
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unsigned char tbuf[2], rbuf[1];
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int ret;
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tbuf[0] = 0x80 | (reg >> 8);
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tbuf[1] = reg & 0xFF;
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ret = spi_write_then_read(spi,
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tbuf, ARRAY_SIZE(tbuf),
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rbuf, ARRAY_SIZE(rbuf));
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if (ret < 0)
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return ret;
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return rbuf[0];
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}
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static int ad9467_spi_write(struct spi_device *spi, unsigned int reg,
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unsigned int val)
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{
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unsigned char buf[3];
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buf[0] = reg >> 8;
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buf[1] = reg & 0xFF;
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buf[2] = val;
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return spi_write(spi, buf, ARRAY_SIZE(buf));
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}
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static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg,
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unsigned int writeval, unsigned int *readval)
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{
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struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
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struct spi_device *spi = st->spi;
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int ret;
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if (readval == NULL) {
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ret = ad9467_spi_write(spi, reg, writeval);
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ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
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AN877_ADC_TRANSFER_SYNC);
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return ret;
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}
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ret = ad9467_spi_read(spi, reg);
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if (ret < 0)
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return ret;
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*readval = ret;
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return 0;
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}
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static const unsigned int ad9467_scale_table[][2] = {
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{2000, 0}, {2100, 6}, {2200, 7},
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{2300, 8}, {2400, 9}, {2500, 10},
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};
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static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index,
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unsigned int *val, unsigned int *val2)
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{
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const struct adi_axi_adc_chip_info *info = conv->chip_info;
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const struct iio_chan_spec *chan = &info->channels[0];
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unsigned int tmp;
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tmp = (info->scale_table[index][0] * 1000000ULL) >>
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chan->scan_type.realbits;
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*val = tmp / 1000000;
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*val2 = tmp % 1000000;
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}
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#define AD9467_CHAN(_chan, _si, _bits, _sign) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = _chan, \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.scan_index = _si, \
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.scan_type = { \
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.sign = _sign, \
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.realbits = _bits, \
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.storagebits = 16, \
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}, \
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}
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static const struct iio_chan_spec ad9467_channels[] = {
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AD9467_CHAN(0, 0, 16, 'S'),
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};
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static const struct adi_axi_adc_chip_info ad9467_chip_tbl[] = {
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[ID_AD9467] = {
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.id = CHIPID_AD9467,
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.max_rate = 250000000UL,
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.scale_table = ad9467_scale_table,
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.num_scales = ARRAY_SIZE(ad9467_scale_table),
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.channels = ad9467_channels,
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.num_channels = ARRAY_SIZE(ad9467_channels),
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},
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};
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static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)
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{
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const struct adi_axi_adc_chip_info *info = conv->chip_info;
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struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
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unsigned int i, vref_val, vref_mask;
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vref_val = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF);
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switch (info->id) {
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case CHIPID_AD9467:
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vref_mask = AD9467_REG_VREF_MASK;
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break;
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default:
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vref_mask = 0xFFFF;
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break;
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}
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vref_val &= vref_mask;
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for (i = 0; i < info->num_scales; i++) {
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if (vref_val == info->scale_table[i][1])
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break;
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}
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if (i == info->num_scales)
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return -ERANGE;
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__ad9467_get_scale(conv, i, val, val2);
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return IIO_VAL_INT_PLUS_MICRO;
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}
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static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)
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{
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const struct adi_axi_adc_chip_info *info = conv->chip_info;
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struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
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unsigned int scale_val[2];
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unsigned int i;
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if (val != 0)
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return -EINVAL;
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for (i = 0; i < info->num_scales; i++) {
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__ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]);
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if (scale_val[0] != val || scale_val[1] != val2)
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continue;
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ad9467_spi_write(st->spi, AN877_ADC_REG_VREF,
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info->scale_table[i][1]);
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ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER,
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AN877_ADC_TRANSFER_SYNC);
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return 0;
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}
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return -EINVAL;
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}
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static int ad9467_read_raw(struct adi_axi_adc_conv *conv,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long m)
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{
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struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
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switch (m) {
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case IIO_CHAN_INFO_SCALE:
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return ad9467_get_scale(conv, val, val2);
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = clk_get_rate(st->clk);
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int ad9467_write_raw(struct adi_axi_adc_conv *conv,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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const struct adi_axi_adc_chip_info *info = conv->chip_info;
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struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
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long r_clk;
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switch (mask) {
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case IIO_CHAN_INFO_SCALE:
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return ad9467_set_scale(conv, val, val2);
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case IIO_CHAN_INFO_SAMP_FREQ:
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r_clk = clk_round_rate(st->clk, val);
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if (r_clk < 0 || r_clk > info->max_rate) {
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dev_warn(&st->spi->dev,
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"Error setting ADC sample rate %ld", r_clk);
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return -EINVAL;
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}
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return clk_set_rate(st->clk, r_clk);
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default:
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return -EINVAL;
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}
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}
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static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)
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{
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int ret;
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ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode);
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if (ret < 0)
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return ret;
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return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
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AN877_ADC_TRANSFER_SYNC);
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}
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static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)
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{
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struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
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return ad9467_outputmode_set(st->spi, st->output_mode);
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}
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static int ad9467_setup(struct ad9467_state *st, unsigned int chip_id)
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{
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switch (chip_id) {
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case CHIPID_AD9467:
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st->output_mode = AD9467_DEF_OUTPUT_MODE |
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AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
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return 0;
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default:
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return -EINVAL;
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}
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}
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static void ad9467_clk_disable(void *data)
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{
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struct ad9467_state *st = data;
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clk_disable_unprepare(st->clk);
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}
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static int ad9467_probe(struct spi_device *spi)
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{
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const struct adi_axi_adc_chip_info *info;
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struct adi_axi_adc_conv *conv;
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struct ad9467_state *st;
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unsigned int id;
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int ret;
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info = of_device_get_match_data(&spi->dev);
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if (!info)
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return -ENODEV;
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conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st));
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if (IS_ERR(conv))
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return PTR_ERR(conv);
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st = adi_axi_adc_conv_priv(conv);
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st->spi = spi;
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st->clk = devm_clk_get(&spi->dev, "adc-clk");
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if (IS_ERR(st->clk))
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return PTR_ERR(st->clk);
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ret = clk_prepare_enable(st->clk);
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if (ret < 0)
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return ret;
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ret = devm_add_action_or_reset(&spi->dev, ad9467_clk_disable, st);
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if (ret)
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return ret;
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st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
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GPIOD_OUT_LOW);
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if (IS_ERR(st->pwrdown_gpio))
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return PTR_ERR(st->pwrdown_gpio);
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st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
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GPIOD_OUT_LOW);
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if (IS_ERR(st->reset_gpio))
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return PTR_ERR(st->reset_gpio);
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if (st->reset_gpio) {
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udelay(1);
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ret = gpiod_direction_output(st->reset_gpio, 1);
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if (ret)
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return ret;
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mdelay(10);
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}
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spi_set_drvdata(spi, st);
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conv->chip_info = info;
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id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID);
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if (id != conv->chip_info->id) {
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dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", id);
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return -ENODEV;
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}
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conv->reg_access = ad9467_reg_access;
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conv->write_raw = ad9467_write_raw;
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conv->read_raw = ad9467_read_raw;
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conv->preenable_setup = ad9467_preenable_setup;
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return ad9467_setup(st, id);
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}
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static const struct of_device_id ad9467_of_match[] = {
|
||||
{ .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ad9467_of_match);
|
||||
|
||||
static struct spi_driver ad9467_driver = {
|
||||
.driver = {
|
||||
.name = "ad9467",
|
||||
.of_match_table = ad9467_of_match,
|
||||
},
|
||||
.probe = ad9467_probe,
|
||||
};
|
||||
module_spi_driver(ad9467_driver);
|
||||
|
||||
MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
|
||||
MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user