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ptp: idt82p33: Add PTP_CLK_REQ_EXTTS support
82P33 family of chips can trigger TOD read/write by external signal from one of the IN12/13/14 pins, which are set user space programs by calling PTP_PIN_SETFUNC through ptp_ioctl Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Min Li
David S. Miller
parent
eea7b31372
commit
ad3cc7760d
@ -27,6 +27,8 @@ MODULE_VERSION("1.0");
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MODULE_LICENSE("GPL");
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MODULE_FIRMWARE(FW_FILENAME);
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#define EXTTS_PERIOD_MS (95)
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/* Module Parameters */
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static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
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module_param(phase_snap_threshold, uint, 0);
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@ -36,6 +38,8 @@ MODULE_PARM_DESC(phase_snap_threshold,
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static char *firmware;
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module_param(firmware, charp, 0);
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static struct ptp_pin_desc pin_config[MAX_PHC_PLL][MAX_TRIG_CLK];
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static inline int idt82p33_read(struct idt82p33 *idt82p33, u16 regaddr,
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u8 *buf, u16 count)
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{
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@ -121,24 +125,270 @@ static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
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return 0;
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}
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static int idt82p33_set_tod_trigger(struct idt82p33_channel *channel,
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u8 trigger, bool write)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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int err;
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u8 cfg;
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if (trigger > WR_TRIG_SEL_MAX)
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return -EINVAL;
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err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
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&cfg, sizeof(cfg));
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if (err)
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return err;
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if (write == true)
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trigger = (trigger << WRITE_TRIGGER_SHIFT) |
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(cfg & READ_TRIGGER_MASK);
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else
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trigger = (trigger << READ_TRIGGER_SHIFT) |
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(cfg & WRITE_TRIGGER_MASK);
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return idt82p33_write(idt82p33, channel->dpll_tod_trigger,
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&trigger, sizeof(trigger));
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}
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static int idt82p33_get_extts(struct idt82p33_channel *channel,
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struct timespec64 *ts)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 buf[TOD_BYTE_COUNT];
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int err;
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err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
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if (err)
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return err;
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/* Since trigger is not self clearing itself, we have to poll tod_sts */
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if (memcmp(buf, channel->extts_tod_sts, TOD_BYTE_COUNT) == 0)
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return -EAGAIN;
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memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT);
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idt82p33_byte_array_to_timespec(ts, buf);
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if (channel->discard_next_extts) {
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channel->discard_next_extts = false;
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return -EAGAIN;
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}
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return 0;
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}
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static int map_ref_to_tod_trig_sel(int ref, u8 *trigger)
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{
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int err = 0;
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switch (ref) {
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case 0:
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*trigger = HW_TOD_TRIG_SEL_IN12;
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break;
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case 1:
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*trigger = HW_TOD_TRIG_SEL_IN13;
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break;
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case 2:
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*trigger = HW_TOD_TRIG_SEL_IN14;
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break;
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default:
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err = -EINVAL;
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}
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return err;
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}
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static bool is_one_shot(u8 mask)
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{
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/* Treat single bit PLL masks as continuous trigger */
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if ((mask == 1) || (mask == 2))
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return false;
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else
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return true;
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}
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static int arm_tod_read_with_trigger(struct idt82p33_channel *channel, u8 trigger)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 buf[TOD_BYTE_COUNT];
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int err;
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/* Remember the current tod_sts before setting the trigger */
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err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
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if (err)
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return err;
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memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT);
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err = idt82p33_set_tod_trigger(channel, trigger, false);
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if (err)
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dev_err(idt82p33->dev, "%s: err = %d", __func__, err);
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return err;
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}
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static int idt82p33_extts_enable(struct idt82p33_channel *channel,
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struct ptp_clock_request *rq, int on)
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{
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u8 index = rq->extts.index;
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struct idt82p33 *idt82p33;
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u8 mask = 1 << index;
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int err = 0;
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u8 old_mask;
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u8 trigger;
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int ref;
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idt82p33 = channel->idt82p33;
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old_mask = idt82p33->extts_mask;
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/* Reject requests with unsupported flags */
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if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
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PTP_RISING_EDGE |
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PTP_FALLING_EDGE |
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PTP_STRICT_FLAGS))
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return -EOPNOTSUPP;
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/* Reject requests to enable time stamping on falling edge */
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if ((rq->extts.flags & PTP_ENABLE_FEATURE) &&
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(rq->extts.flags & PTP_FALLING_EDGE))
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return -EOPNOTSUPP;
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if (index >= MAX_PHC_PLL)
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return -EINVAL;
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if (on) {
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/* Return if it was already enabled */
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if (idt82p33->extts_mask & mask)
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return 0;
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/* Use the pin configured for the channel */
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ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->plln);
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if (ref < 0) {
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dev_err(idt82p33->dev, "%s: No valid pin found for Pll%d!\n",
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__func__, channel->plln);
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return -EBUSY;
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}
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err = map_ref_to_tod_trig_sel(ref, &trigger);
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if (err) {
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dev_err(idt82p33->dev,
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"%s: Unsupported ref %d!\n", __func__, ref);
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return err;
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}
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err = arm_tod_read_with_trigger(&idt82p33->channel[index], trigger);
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if (err == 0) {
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idt82p33->extts_mask |= mask;
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idt82p33->channel[index].tod_trigger = trigger;
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idt82p33->event_channel[index] = channel;
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idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask);
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if (old_mask)
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return 0;
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schedule_delayed_work(&idt82p33->extts_work,
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msecs_to_jiffies(EXTTS_PERIOD_MS));
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}
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} else {
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idt82p33->extts_mask &= ~mask;
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idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask);
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if (idt82p33->extts_mask == 0)
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cancel_delayed_work(&idt82p33->extts_work);
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}
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return err;
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}
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static int idt82p33_extts_check_channel(struct idt82p33 *idt82p33, u8 todn)
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{
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struct idt82p33_channel *event_channel;
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struct ptp_clock_event event;
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struct timespec64 ts;
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int err;
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err = idt82p33_get_extts(&idt82p33->channel[todn], &ts);
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if (err == 0) {
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event_channel = idt82p33->event_channel[todn];
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event.type = PTP_CLOCK_EXTTS;
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event.index = todn;
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event.timestamp = timespec64_to_ns(&ts);
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ptp_clock_event(event_channel->ptp_clock,
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&event);
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}
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return err;
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}
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static u8 idt82p33_extts_enable_mask(struct idt82p33_channel *channel,
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u8 extts_mask, bool enable)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 trigger = channel->tod_trigger;
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u8 mask;
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int err;
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int i;
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if (extts_mask == 0)
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return 0;
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if (enable == false)
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cancel_delayed_work_sync(&idt82p33->extts_work);
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for (i = 0; i < MAX_PHC_PLL; i++) {
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mask = 1 << i;
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if ((extts_mask & mask) == 0)
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continue;
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if (enable) {
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err = arm_tod_read_with_trigger(&idt82p33->channel[i], trigger);
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if (err)
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dev_err(idt82p33->dev,
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"%s: Arm ToD read trigger failed, err = %d",
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__func__, err);
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} else {
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err = idt82p33_extts_check_channel(idt82p33, i);
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if (err == 0 && idt82p33->extts_single_shot)
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/* trigger happened so we won't re-enable it */
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extts_mask &= ~mask;
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}
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}
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if (enable)
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schedule_delayed_work(&idt82p33->extts_work,
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msecs_to_jiffies(EXTTS_PERIOD_MS));
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return extts_mask;
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}
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static int _idt82p33_gettime(struct idt82p33_channel *channel,
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struct timespec64 *ts)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 old_mask = idt82p33->extts_mask;
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u8 buf[TOD_BYTE_COUNT];
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u8 trigger;
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u8 new_mask = 0;
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int err;
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trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
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err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
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&trigger, sizeof(trigger));
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/* Disable extts */
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if (old_mask)
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new_mask = idt82p33_extts_enable_mask(channel, old_mask, false);
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err = idt82p33_set_tod_trigger(channel, HW_TOD_RD_TRIG_SEL_LSB_TOD_STS,
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false);
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if (err)
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return err;
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channel->discard_next_extts = true;
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if (idt82p33->calculate_overhead_flag)
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idt82p33->start_time = ktime_get_raw();
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@ -147,6 +397,10 @@ static int _idt82p33_gettime(struct idt82p33_channel *channel,
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if (err)
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return err;
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/* Re-enable extts */
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if (new_mask)
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idt82p33_extts_enable_mask(channel, new_mask, true);
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idt82p33_byte_array_to_timespec(ts, buf);
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return 0;
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@ -165,19 +419,16 @@ static int _idt82p33_settime(struct idt82p33_channel *channel,
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struct timespec64 local_ts = *ts;
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char buf[TOD_BYTE_COUNT];
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s64 dynamic_overhead_ns;
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unsigned char trigger;
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int err;
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u8 i;
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trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
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err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
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&trigger, sizeof(trigger));
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err = idt82p33_set_tod_trigger(channel, HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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true);
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if (err)
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return err;
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channel->discard_next_extts = true;
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if (idt82p33->calculate_overhead_flag) {
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dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
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- ktime_to_ns(idt82p33->start_time);
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@ -202,7 +453,8 @@ static int _idt82p33_settime(struct idt82p33_channel *channel,
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return err;
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}
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static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
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static int _idt82p33_adjtime_immediate(struct idt82p33_channel *channel,
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s64 delta_ns)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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struct timespec64 ts;
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@ -226,6 +478,60 @@ static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
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return err;
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}
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static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel *channel,
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s64 delta_ns)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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char buf[TOD_BYTE_COUNT];
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struct timespec64 ts;
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const u8 delay_ns = 32;
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s32 remainder;
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s64 ns;
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int err;
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err = _idt82p33_gettime(channel, &ts);
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if (err)
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return err;
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if (ts.tv_nsec > (NSEC_PER_SEC - 5 * NSEC_PER_MSEC)) {
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/* Too close to miss next trigger, so skip it */
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mdelay(6);
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ns = (ts.tv_sec + 2) * NSEC_PER_SEC + delta_ns + delay_ns;
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} else
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ns = (ts.tv_sec + 1) * NSEC_PER_SEC + delta_ns + delay_ns;
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ts = ns_to_timespec64(ns);
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idt82p33_timespec_to_byte_array(&ts, buf);
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/*
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* Store the new time value.
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*/
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err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg, buf, sizeof(buf));
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if (err)
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return err;
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/* Schedule to implement the workaround in one second */
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(void)div_s64_rem(delta_ns, NSEC_PER_SEC, &remainder);
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if (remainder != 0)
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schedule_delayed_work(&channel->adjtime_work, HZ);
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return idt82p33_set_tod_trigger(channel, HW_TOD_TRIG_SEL_TOD_PPS, true);
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}
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static void idt82p33_adjtime_workaround(struct work_struct *work)
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{
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struct idt82p33_channel *channel = container_of(work,
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struct idt82p33_channel,
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adjtime_work.work);
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struct idt82p33 *idt82p33 = channel->idt82p33;
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mutex_lock(idt82p33->lock);
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/* Workaround for TOD-to-output alignment issue */
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_idt82p33_adjtime_internal_triggered(channel, 0);
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mutex_unlock(idt82p33->lock);
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}
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static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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@ -233,25 +539,22 @@ static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
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int err, i;
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s64 fcw;
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if (scaled_ppm == channel->current_freq_ppb)
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return 0;
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/*
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* Frequency Control Word unit is: 1.68 * 10^-10 ppm
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* Frequency Control Word unit is: 1.6861512 * 10^-10 ppm
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*
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* adjfreq:
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* ppb * 10^9
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* FCW = ----------
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* 168
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* ppb * 10^14
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* FCW = -----------
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* 16861512
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*
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* adjfine:
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* scaled_ppm * 5^12
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* FCW = -------------
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* 168 * 2^4
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* scaled_ppm * 5^12 * 10^5
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* FCW = ------------------------
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* 16861512 * 2^4
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*/
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fcw = scaled_ppm * 244140625ULL;
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fcw = div_s64(fcw, 2688);
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fcw = scaled_ppm * 762939453125ULL;
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fcw = div_s64(fcw, 8430756LL);
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for (i = 0; i < 5; i++) {
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buf[i] = fcw & 0xff;
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@ -266,26 +569,84 @@ static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
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err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
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buf, sizeof(buf));
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if (err == 0)
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channel->current_freq_ppb = scaled_ppm;
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return err;
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}
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/* ppb = scaled_ppm * 125 / 2^13 */
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static s32 idt82p33_ddco_scaled_ppm(long current_ppm, s32 ddco_ppb)
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{
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s64 scaled_ppm = div_s64(((s64)ddco_ppb << 13), 125);
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s64 max_scaled_ppm = div_s64(((s64)DCO_MAX_PPB << 13), 125);
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current_ppm += scaled_ppm;
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|
||||
if (current_ppm > max_scaled_ppm)
|
||||
current_ppm = max_scaled_ppm;
|
||||
else if (current_ppm < -max_scaled_ppm)
|
||||
current_ppm = -max_scaled_ppm;
|
||||
|
||||
return (s32)current_ppm;
|
||||
}
|
||||
|
||||
static int idt82p33_stop_ddco(struct idt82p33_channel *channel)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = _idt82p33_adjfine(channel, channel->current_freq);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
channel->ddco = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idt82p33_start_ddco(struct idt82p33_channel *channel, s32 delta_ns)
|
||||
{
|
||||
s32 current_ppm = channel->current_freq;
|
||||
u32 duration_ms = MSEC_PER_SEC;
|
||||
s32 ppb;
|
||||
int err;
|
||||
|
||||
/* If the ToD correction is less than 5 nanoseconds, then skip it.
|
||||
* The error introduced by the ToD adjustment procedure would be bigger
|
||||
* than the required ToD correction
|
||||
*/
|
||||
if (abs(delta_ns) < DDCO_THRESHOLD_NS)
|
||||
return 0;
|
||||
|
||||
/* For most cases, keep ddco duration 1 second */
|
||||
ppb = delta_ns;
|
||||
while (abs(ppb) > DCO_MAX_PPB) {
|
||||
duration_ms *= 2;
|
||||
ppb /= 2;
|
||||
}
|
||||
|
||||
err = _idt82p33_adjfine(channel,
|
||||
idt82p33_ddco_scaled_ppm(current_ppm, ppb));
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* schedule the worker to cancel ddco */
|
||||
ptp_schedule_worker(channel->ptp_clock,
|
||||
msecs_to_jiffies(duration_ms) - 1);
|
||||
channel->ddco = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idt82p33_measure_one_byte_write_overhead(
|
||||
struct idt82p33_channel *channel, s64 *overhead_ns)
|
||||
{
|
||||
struct idt82p33 *idt82p33 = channel->idt82p33;
|
||||
ktime_t start, stop;
|
||||
u8 trigger = 0;
|
||||
s64 total_ns;
|
||||
u8 trigger;
|
||||
int err;
|
||||
u8 i;
|
||||
|
||||
total_ns = 0;
|
||||
*overhead_ns = 0;
|
||||
trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
|
||||
HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
|
||||
|
||||
for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
|
||||
|
||||
@ -307,8 +668,41 @@ static int idt82p33_measure_one_byte_write_overhead(
|
||||
return err;
|
||||
}
|
||||
|
||||
static int idt82p33_measure_one_byte_read_overhead(
|
||||
struct idt82p33_channel *channel, s64 *overhead_ns)
|
||||
{
|
||||
struct idt82p33 *idt82p33 = channel->idt82p33;
|
||||
ktime_t start, stop;
|
||||
u8 trigger = 0;
|
||||
s64 total_ns;
|
||||
int err;
|
||||
u8 i;
|
||||
|
||||
total_ns = 0;
|
||||
*overhead_ns = 0;
|
||||
|
||||
for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
|
||||
|
||||
start = ktime_get_raw();
|
||||
|
||||
err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
|
||||
&trigger, sizeof(trigger));
|
||||
|
||||
stop = ktime_get_raw();
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
|
||||
}
|
||||
|
||||
*overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int idt82p33_measure_tod_write_9_byte_overhead(
|
||||
struct idt82p33_channel *channel)
|
||||
struct idt82p33_channel *channel)
|
||||
{
|
||||
struct idt82p33 *idt82p33 = channel->idt82p33;
|
||||
u8 buf[TOD_BYTE_COUNT];
|
||||
@ -368,7 +762,7 @@ static int idt82p33_measure_settime_gettime_gap_overhead(
|
||||
|
||||
static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
|
||||
{
|
||||
s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
|
||||
s64 trailing_overhead_ns, one_byte_write_ns, gap_ns, one_byte_read_ns;
|
||||
struct idt82p33 *idt82p33 = channel->idt82p33;
|
||||
int err;
|
||||
|
||||
@ -388,12 +782,19 @@ static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = idt82p33_measure_one_byte_read_overhead(channel,
|
||||
&one_byte_read_ns);
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = idt82p33_measure_tod_write_9_byte_overhead(channel);
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
|
||||
trailing_overhead_ns = gap_ns - 2 * one_byte_write_ns
|
||||
- one_byte_read_ns;
|
||||
|
||||
idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
|
||||
|
||||
@ -462,6 +863,20 @@ static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
|
||||
&sync_cnfg, sizeof(sync_cnfg));
|
||||
}
|
||||
|
||||
static long idt82p33_work_handler(struct ptp_clock_info *ptp)
|
||||
{
|
||||
struct idt82p33_channel *channel =
|
||||
container_of(ptp, struct idt82p33_channel, caps);
|
||||
struct idt82p33 *idt82p33 = channel->idt82p33;
|
||||
|
||||
mutex_lock(idt82p33->lock);
|
||||
(void)idt82p33_stop_ddco(channel);
|
||||
mutex_unlock(idt82p33->lock);
|
||||
|
||||
/* Return a negative value here to not reschedule */
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int idt82p33_output_enable(struct idt82p33_channel *channel,
|
||||
bool enable, unsigned int outn)
|
||||
{
|
||||
@ -524,6 +939,10 @@ static int idt82p33_enable_tod(struct idt82p33_channel *channel)
|
||||
struct timespec64 ts = {0, 0};
|
||||
int err;
|
||||
|
||||
/* STEELAI-366 - Temporary workaround for ts2phc compatibility */
|
||||
if (0)
|
||||
err = idt82p33_output_mask_enable(channel, false);
|
||||
|
||||
err = idt82p33_measure_tod_write_overhead(channel);
|
||||
|
||||
if (err) {
|
||||
@ -546,14 +965,15 @@ static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
|
||||
u8 i;
|
||||
|
||||
for (i = 0; i < MAX_PHC_PLL; i++) {
|
||||
|
||||
channel = &idt82p33->channel[i];
|
||||
|
||||
cancel_delayed_work_sync(&channel->adjtime_work);
|
||||
if (channel->ptp_clock)
|
||||
ptp_clock_unregister(channel->ptp_clock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int idt82p33_enable(struct ptp_clock_info *ptp,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
@ -564,7 +984,8 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,
|
||||
|
||||
mutex_lock(idt82p33->lock);
|
||||
|
||||
if (rq->type == PTP_CLK_REQ_PEROUT) {
|
||||
switch (rq->type) {
|
||||
case PTP_CLK_REQ_PEROUT:
|
||||
if (!on)
|
||||
err = idt82p33_perout_enable(channel, false,
|
||||
&rq->perout);
|
||||
@ -575,6 +996,12 @@ static int idt82p33_enable(struct ptp_clock_info *ptp,
|
||||
else
|
||||
err = idt82p33_perout_enable(channel, true,
|
||||
&rq->perout);
|
||||
break;
|
||||
case PTP_CLK_REQ_EXTTS:
|
||||
err = idt82p33_extts_enable(channel, rq, on);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
mutex_unlock(idt82p33->lock);
|
||||
@ -634,13 +1061,22 @@ static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
|
||||
struct idt82p33 *idt82p33 = channel->idt82p33;
|
||||
int err;
|
||||
|
||||
if (channel->ddco == true)
|
||||
return 0;
|
||||
|
||||
if (scaled_ppm == channel->current_freq)
|
||||
return 0;
|
||||
|
||||
mutex_lock(idt82p33->lock);
|
||||
err = _idt82p33_adjfine(channel, scaled_ppm);
|
||||
|
||||
if (err == 0)
|
||||
channel->current_freq = scaled_ppm;
|
||||
mutex_unlock(idt82p33->lock);
|
||||
|
||||
if (err)
|
||||
dev_err(idt82p33->dev,
|
||||
"Failed in %s with err %d!\n", __func__, err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -651,14 +1087,21 @@ static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
|
||||
struct idt82p33 *idt82p33 = channel->idt82p33;
|
||||
int err;
|
||||
|
||||
if (channel->ddco == true)
|
||||
return -EBUSY;
|
||||
|
||||
mutex_lock(idt82p33->lock);
|
||||
|
||||
if (abs(delta_ns) < phase_snap_threshold) {
|
||||
err = idt82p33_start_ddco(channel, delta_ns);
|
||||
mutex_unlock(idt82p33->lock);
|
||||
return 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
err = _idt82p33_adjtime(channel, delta_ns);
|
||||
/* Use more accurate internal 1pps triggered write first */
|
||||
err = _idt82p33_adjtime_internal_triggered(channel, delta_ns);
|
||||
if (err && delta_ns > IMMEDIATE_SNAP_THRESHOLD_NS)
|
||||
err = _idt82p33_adjtime_immediate(channel, delta_ns);
|
||||
|
||||
mutex_unlock(idt82p33->lock);
|
||||
|
||||
@ -703,8 +1146,10 @@ static int idt82p33_settime(struct ptp_clock_info *ptp,
|
||||
return err;
|
||||
}
|
||||
|
||||
static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
|
||||
static int idt82p33_channel_init(struct idt82p33 *idt82p33, u32 index)
|
||||
{
|
||||
struct idt82p33_channel *channel = &idt82p33->channel[index];
|
||||
|
||||
switch (index) {
|
||||
case 0:
|
||||
channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
|
||||
@ -730,22 +1175,60 @@ static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
channel->current_freq_ppb = 0;
|
||||
channel->plln = index;
|
||||
channel->current_freq = 0;
|
||||
channel->idt82p33 = idt82p33;
|
||||
INIT_DELAYED_WORK(&channel->adjtime_work, idt82p33_adjtime_workaround);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void idt82p33_caps_init(struct ptp_clock_info *caps)
|
||||
static int idt82p33_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
|
||||
enum ptp_pin_function func, unsigned int chan)
|
||||
{
|
||||
switch (func) {
|
||||
case PTP_PF_NONE:
|
||||
case PTP_PF_EXTTS:
|
||||
break;
|
||||
case PTP_PF_PEROUT:
|
||||
case PTP_PF_PHYSYNC:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void idt82p33_caps_init(u32 index, struct ptp_clock_info *caps,
|
||||
struct ptp_pin_desc *pin_cfg, u8 max_pins)
|
||||
{
|
||||
struct ptp_pin_desc *ppd;
|
||||
int i;
|
||||
|
||||
caps->owner = THIS_MODULE;
|
||||
caps->max_adj = DCO_MAX_PPB;
|
||||
caps->n_per_out = 11;
|
||||
caps->adjphase = idt82p33_adjwritephase;
|
||||
caps->n_per_out = MAX_PER_OUT;
|
||||
caps->n_ext_ts = MAX_PHC_PLL,
|
||||
caps->n_pins = max_pins,
|
||||
caps->adjphase = idt82p33_adjwritephase,
|
||||
caps->adjfine = idt82p33_adjfine;
|
||||
caps->adjtime = idt82p33_adjtime;
|
||||
caps->gettime64 = idt82p33_gettime;
|
||||
caps->settime64 = idt82p33_settime;
|
||||
caps->enable = idt82p33_enable;
|
||||
caps->verify = idt82p33_verify_pin;
|
||||
caps->do_aux_work = idt82p33_work_handler;
|
||||
|
||||
snprintf(caps->name, sizeof(caps->name), "IDT 82P33 PLL%u", index);
|
||||
|
||||
caps->pin_config = pin_cfg;
|
||||
|
||||
for (i = 0; i < max_pins; ++i) {
|
||||
ppd = &pin_cfg[i];
|
||||
|
||||
ppd->index = i;
|
||||
ppd->func = PTP_PF_NONE;
|
||||
ppd->chan = index;
|
||||
snprintf(ppd->name, sizeof(ppd->name), "in%d", 12 + i);
|
||||
}
|
||||
}
|
||||
|
||||
static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
|
||||
@ -758,7 +1241,7 @@ static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
|
||||
|
||||
channel = &idt82p33->channel[index];
|
||||
|
||||
err = idt82p33_channel_init(channel, index);
|
||||
err = idt82p33_channel_init(idt82p33, index);
|
||||
if (err) {
|
||||
dev_err(idt82p33->dev,
|
||||
"Channel_init failed in %s with err %d!\n",
|
||||
@ -766,11 +1249,8 @@ static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
|
||||
return err;
|
||||
}
|
||||
|
||||
channel->idt82p33 = idt82p33;
|
||||
|
||||
idt82p33_caps_init(&channel->caps);
|
||||
snprintf(channel->caps.name, sizeof(channel->caps.name),
|
||||
"IDT 82P33 PLL%u", index);
|
||||
idt82p33_caps_init(index, &channel->caps,
|
||||
pin_config[index], MAX_TRIG_CLK);
|
||||
|
||||
channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
|
||||
|
||||
@ -805,17 +1285,46 @@ static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int idt82p33_reset(struct idt82p33 *idt82p33, bool cold)
|
||||
{
|
||||
int err;
|
||||
u8 cfg = SOFT_RESET_EN;
|
||||
|
||||
if (cold == true)
|
||||
goto cold_reset;
|
||||
|
||||
err = idt82p33_read(idt82p33, REG_SOFT_RESET, &cfg, sizeof(cfg));
|
||||
if (err) {
|
||||
dev_err(idt82p33->dev,
|
||||
"Soft reset failed with err %d!\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
cfg |= SOFT_RESET_EN;
|
||||
|
||||
cold_reset:
|
||||
err = idt82p33_write(idt82p33, REG_SOFT_RESET, &cfg, sizeof(cfg));
|
||||
if (err)
|
||||
dev_err(idt82p33->dev,
|
||||
"Cold reset failed with err %d!\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
|
||||
{
|
||||
char fname[128] = FW_FILENAME;
|
||||
const struct firmware *fw;
|
||||
struct idt82p33_fwrc *rec;
|
||||
u8 loaddr, page, val;
|
||||
int err;
|
||||
s32 len;
|
||||
|
||||
dev_dbg(idt82p33->dev, "requesting firmware '%s'\n", FW_FILENAME);
|
||||
if (firmware) /* module parameter */
|
||||
snprintf(fname, sizeof(fname), "%s", firmware);
|
||||
|
||||
err = request_firmware(&fw, FW_FILENAME, idt82p33->dev);
|
||||
dev_info(idt82p33->dev, "requesting firmware '%s'\n", fname);
|
||||
|
||||
err = request_firmware(&fw, fname, idt82p33->dev);
|
||||
|
||||
if (err) {
|
||||
dev_err(idt82p33->dev,
|
||||
@ -863,6 +1372,46 @@ out:
|
||||
return err;
|
||||
}
|
||||
|
||||
static void idt82p33_extts_check(struct work_struct *work)
|
||||
{
|
||||
struct idt82p33 *idt82p33 = container_of(work, struct idt82p33,
|
||||
extts_work.work);
|
||||
struct idt82p33_channel *channel;
|
||||
int err;
|
||||
u8 mask;
|
||||
int i;
|
||||
|
||||
if (idt82p33->extts_mask == 0)
|
||||
return;
|
||||
|
||||
mutex_lock(idt82p33->lock);
|
||||
|
||||
for (i = 0; i < MAX_PHC_PLL; i++) {
|
||||
mask = 1 << i;
|
||||
|
||||
if ((idt82p33->extts_mask & mask) == 0)
|
||||
continue;
|
||||
|
||||
err = idt82p33_extts_check_channel(idt82p33, i);
|
||||
|
||||
if (err == 0) {
|
||||
/* trigger clears itself, so clear the mask */
|
||||
if (idt82p33->extts_single_shot) {
|
||||
idt82p33->extts_mask &= ~mask;
|
||||
} else {
|
||||
/* Re-arm */
|
||||
channel = &idt82p33->channel[i];
|
||||
arm_tod_read_with_trigger(channel, channel->tod_trigger);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (idt82p33->extts_mask)
|
||||
schedule_delayed_work(&idt82p33->extts_work,
|
||||
msecs_to_jiffies(EXTTS_PERIOD_MS));
|
||||
|
||||
mutex_unlock(idt82p33->lock);
|
||||
}
|
||||
|
||||
static int idt82p33_probe(struct platform_device *pdev)
|
||||
{
|
||||
@ -885,25 +1434,33 @@ static int idt82p33_probe(struct platform_device *pdev)
|
||||
idt82p33->pll_mask = DEFAULT_PLL_MASK;
|
||||
idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
|
||||
idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
|
||||
idt82p33->extts_mask = 0;
|
||||
INIT_DELAYED_WORK(&idt82p33->extts_work, idt82p33_extts_check);
|
||||
|
||||
mutex_lock(idt82p33->lock);
|
||||
|
||||
err = idt82p33_load_firmware(idt82p33);
|
||||
/* cold reset before loading firmware */
|
||||
idt82p33_reset(idt82p33, true);
|
||||
|
||||
err = idt82p33_load_firmware(idt82p33);
|
||||
if (err)
|
||||
dev_warn(idt82p33->dev,
|
||||
"loading firmware failed with %d\n", err);
|
||||
|
||||
/* soft reset after loading firmware */
|
||||
idt82p33_reset(idt82p33, false);
|
||||
|
||||
if (idt82p33->pll_mask) {
|
||||
for (i = 0; i < MAX_PHC_PLL; i++) {
|
||||
if (idt82p33->pll_mask & (1 << i)) {
|
||||
if (idt82p33->pll_mask & (1 << i))
|
||||
err = idt82p33_enable_channel(idt82p33, i);
|
||||
if (err) {
|
||||
dev_err(idt82p33->dev,
|
||||
"Failed in %s with err %d!\n",
|
||||
__func__, err);
|
||||
break;
|
||||
}
|
||||
else
|
||||
err = idt82p33_channel_init(idt82p33, i);
|
||||
if (err) {
|
||||
dev_err(idt82p33->dev,
|
||||
"Failed in %s with err %d!\n",
|
||||
__func__, err);
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
@ -928,6 +1485,8 @@ static int idt82p33_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct idt82p33 *idt82p33 = platform_get_drvdata(pdev);
|
||||
|
||||
cancel_delayed_work_sync(&idt82p33->extts_work);
|
||||
|
||||
idt82p33_ptp_clock_unregister_all(idt82p33);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -13,6 +13,8 @@
|
||||
|
||||
#define FW_FILENAME "idt82p33xxx.bin"
|
||||
#define MAX_PHC_PLL (2)
|
||||
#define MAX_TRIG_CLK (3)
|
||||
#define MAX_PER_OUT (11)
|
||||
#define TOD_BYTE_COUNT (10)
|
||||
#define DCO_MAX_PPB (92000)
|
||||
#define MAX_MEASURMENT_COUNT (5)
|
||||
@ -60,8 +62,18 @@ struct idt82p33_channel {
|
||||
struct ptp_clock *ptp_clock;
|
||||
struct idt82p33 *idt82p33;
|
||||
enum pll_mode pll_mode;
|
||||
s32 current_freq_ppb;
|
||||
/* Workaround for TOD-to-output alignment issue */
|
||||
struct delayed_work adjtime_work;
|
||||
s32 current_freq;
|
||||
/* double dco mode */
|
||||
bool ddco;
|
||||
u8 output_mask;
|
||||
/* last input trigger for extts */
|
||||
u8 tod_trigger;
|
||||
bool discard_next_extts;
|
||||
u8 plln;
|
||||
/* remember last tod_sts for extts */
|
||||
u8 extts_tod_sts[TOD_BYTE_COUNT];
|
||||
u16 dpll_tod_cnfg;
|
||||
u16 dpll_tod_trigger;
|
||||
u16 dpll_tod_sts;
|
||||
@ -76,6 +88,12 @@ struct idt82p33 {
|
||||
struct idt82p33_channel channel[MAX_PHC_PLL];
|
||||
struct device *dev;
|
||||
u8 pll_mask;
|
||||
/* Polls for external time stamps */
|
||||
u8 extts_mask;
|
||||
bool extts_single_shot;
|
||||
struct delayed_work extts_work;
|
||||
/* Remember the ptp channel to report extts */
|
||||
struct idt82p33_channel *event_channel[MAX_PHC_PLL];
|
||||
/* Mutex to protect operations from being interrupted */
|
||||
struct mutex *lock;
|
||||
struct regmap *regmap;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user