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powerpc/32: remove a NOP from memset()
memset() is patched after initialisation to activate the optimised part which uses cache instructions. Today we have a 'b 2f' to skip the optimised patch, which then gets replaced by a NOP, implying a useless cycle consumption. As we have a 'bne 2f' just before, we could use that instruction for the live patching, hence removing the need to have a dedicated 'b 2f' to be replaced by a NOP. This patch changes the 'bne 2f' by a 'b 2f'. During init, that 'b 2f' is then replaced by 'bne 2f' Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -98,6 +98,9 @@ extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
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notrace void __init machine_init(u64 dt_ptr)
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{
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unsigned int *addr = &memset_nocache_branch;
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unsigned long insn;
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/* Configure static keys first, now that we're relocated. */
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setup_feature_keys();
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@ -105,7 +108,9 @@ notrace void __init machine_init(u64 dt_ptr)
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udbg_early_init();
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patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
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patch_instruction(&memset_nocache_branch, PPC_INST_NOP);
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insn = create_cond_branch(addr, branch_target(addr), 0x820000);
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patch_instruction(addr, insn); /* replace b by bne cr0 */
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/* Do some early initialization based on the flat device tree */
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early_init_devtree(__va(dt_ptr));
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@ -103,9 +103,12 @@ _GLOBAL(memset)
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add r5,r0,r5
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subf r6,r0,r3
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cmplwi 0,r4,0
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bne 2f /* Use normal procedure if r4 is not zero */
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/*
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* Skip optimised bloc until cache is enabled. Will be replaced
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* by 'bne' during boot to use normal procedure if r4 is not zero
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*/
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_GLOBAL(memset_nocache_branch)
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b 2f /* Skip optimised bloc until cache is enabled */
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b 2f
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clrlwi r7,r6,32-LG_CACHELINE_BYTES
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add r8,r7,r5
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