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sh-pfc: Compute pin ranges automatically
Remove the manually specified ranges from PFC SoC data and compute the ranges automatically. This prevents ranges from being out-of-sync with pins definitions. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
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@ -82,17 +82,14 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
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unsigned int offset;
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unsigned int i;
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if (pfc->info->ranges == NULL)
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return pin;
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for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
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const struct pinmux_range *range = &pfc->info->ranges[i];
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for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
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const struct sh_pfc_pin_range *range = &pfc->ranges[i];
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if (pin <= range->end)
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return pin >= range->begin
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? offset + pin - range->begin : -1;
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return pin >= range->start
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? offset + pin - range->start : -1;
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offset += range->end - range->begin + 1;
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offset += range->end - range->start + 1;
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}
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return -EINVAL;
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@ -341,6 +338,59 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
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return 0;
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}
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static int sh_pfc_init_ranges(struct sh_pfc *pfc)
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{
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struct sh_pfc_pin_range *range;
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unsigned int nr_ranges;
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unsigned int i;
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if (pfc->info->pins[0].pin == (u16)-1) {
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/* Pin number -1 denotes that the SoC doesn't report pin numbers
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* in its pin arrays yet. Consider the pin numbers range as
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* continuous and allocate a single range.
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*/
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pfc->nr_ranges = 1;
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pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
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GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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pfc->ranges->start = 0;
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pfc->ranges->end = pfc->info->nr_pins - 1;
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pfc->nr_gpio_pins = pfc->info->nr_pins;
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return 0;
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}
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/* Count, allocate and fill the ranges. */
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for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
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nr_ranges++;
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}
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pfc->nr_ranges = nr_ranges;
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pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
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GFP_KERNEL);
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if (pfc->ranges == NULL)
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return -ENOMEM;
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range = pfc->ranges;
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range->start = pfc->info->pins[0].pin;
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for (i = 1; i < pfc->info->nr_pins; ++i) {
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if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) {
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range->end = pfc->info->pins[i-1].pin;
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range++;
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range->start = pfc->info->pins[i].pin;
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}
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}
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range->end = pfc->info->pins[i-1].pin;
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pfc->nr_gpio_pins = range->end + 1;
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id sh_pfc_of_table[] = {
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#ifdef CONFIG_PINCTRL_PFC_R8A73A4
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@ -431,6 +481,10 @@ static int sh_pfc_probe(struct platform_device *pdev)
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pinctrl_provide_dummies();
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ret = sh_pfc_init_ranges(pfc);
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if (ret < 0)
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return ret;
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/*
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* Initialize pinctrl bindings first
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*/
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@ -25,6 +25,11 @@ struct sh_pfc_window {
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struct sh_pfc_chip;
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struct sh_pfc_pinctrl;
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struct sh_pfc_pin_range {
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u16 start;
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u16 end;
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};
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struct sh_pfc {
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struct device *dev;
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const struct sh_pfc_soc_info *info;
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@ -34,6 +39,9 @@ struct sh_pfc {
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unsigned int num_windows;
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struct sh_pfc_window *window;
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struct sh_pfc_pin_range *ranges;
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unsigned int nr_ranges;
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unsigned int nr_gpio_pins;
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struct sh_pfc_chip *gpio;
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@ -334,10 +334,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
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int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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{
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const struct pinmux_range *ranges;
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struct pinmux_range def_range;
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struct sh_pfc_chip *chip;
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unsigned int nr_ranges;
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unsigned int i;
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int ret;
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@ -368,23 +365,13 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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pfc->gpio = chip;
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/* Register the GPIO to pin mappings. */
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if (pfc->info->ranges == NULL) {
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def_range.begin = 0;
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def_range.end = pfc->info->nr_pins - 1;
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ranges = &def_range;
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nr_ranges = 1;
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} else {
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ranges = pfc->info->ranges;
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nr_ranges = pfc->info->nr_ranges;
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}
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for (i = 0; i < nr_ranges; ++i) {
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const struct pinmux_range *range = &ranges[i];
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for (i = 0; i < pfc->nr_ranges; ++i) {
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const struct sh_pfc_pin_range *range = &pfc->ranges[i];
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ret = gpiochip_add_pin_range(&chip->gpio_chip,
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dev_name(pfc->dev),
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range->begin, range->begin,
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range->end - range->begin + 1);
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range->start, range->start,
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range->end - range->start + 1);
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if (ret < 0)
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return ret;
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}
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@ -1398,20 +1398,6 @@ static struct sh_pfc_pin pinmux_pins[] = {
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R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
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};
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static const struct pinmux_range pinmux_ranges[] = {
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{.begin = 0, .end = 30,},
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{.begin = 32, .end = 40,},
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{.begin = 64, .end = 85,},
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{.begin = 96, .end = 126,},
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{.begin = 128, .end = 134,},
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{.begin = 160, .end = 178,},
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{.begin = 192, .end = 222,},
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{.begin = 224, .end = 250,},
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{.begin = 256, .end = 283,},
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{.begin = 288, .end = 308,},
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{.begin = 320, .end = 329,},
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};
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/* - IRQC ------------------------------------------------------------------- */
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#define IRQC_PINS_MUX(pin, irq_mark) \
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static const unsigned int irqc_irq##irq_mark##_pins[] = { \
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@ -2756,9 +2742,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
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.pins = pinmux_pins,
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.nr_pins = ARRAY_SIZE(pinmux_pins),
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.ranges = pinmux_ranges,
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.nr_ranges = ARRAY_SIZE(pinmux_ranges),
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.groups = pinmux_groups,
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.nr_groups = ARRAY_SIZE(pinmux_groups),
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.functions = pinmux_functions,
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@ -1446,13 +1446,6 @@ static struct sh_pfc_pin pinmux_pins[] = {
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SH73A0_PIN_O(309),
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};
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static const struct pinmux_range pinmux_ranges[] = {
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{.begin = 0, .end = 118,},
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{.begin = 128, .end = 164,},
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{.begin = 192, .end = 282,},
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{.begin = 288, .end = 309,},
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};
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/* Pin numbers for pins without a corresponding GPIO port number are computed
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* from the row and column numbers with a 1000 offset to avoid collisions with
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* GPIO port numbers.
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@ -3894,8 +3887,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
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.pins = pinmux_pins,
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.nr_pins = ARRAY_SIZE(pinmux_pins),
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.ranges = pinmux_ranges,
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.nr_ranges = ARRAY_SIZE(pinmux_ranges),
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.groups = pinmux_groups,
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.nr_groups = ARRAY_SIZE(pinmux_groups),
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.functions = pinmux_functions,
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@ -587,22 +587,9 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = {
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/* PFC ranges -> pinctrl pin descs */
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static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
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{
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const struct pinmux_range *ranges;
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struct pinmux_range def_range;
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unsigned int nr_ranges;
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unsigned int nr_pins;
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unsigned int i;
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if (pfc->info->ranges == NULL) {
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def_range.begin = 0;
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def_range.end = pfc->info->nr_pins - 1;
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ranges = &def_range;
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nr_ranges = 1;
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} else {
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ranges = pfc->info->ranges;
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nr_ranges = pfc->info->nr_ranges;
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}
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/* Allocate and initialize the pins and configs arrays. */
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pmx->pins = devm_kzalloc(pfc->dev,
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sizeof(*pmx->pins) * pfc->info->nr_pins,
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GFP_KERNEL);
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@ -615,32 +602,24 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
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if (unlikely(!pmx->configs))
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return -ENOMEM;
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for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
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const struct pinmux_range *range = &ranges[i];
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unsigned int number;
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for (i = 0; i < pfc->info->nr_pins; ++i) {
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const struct sh_pfc_pin *info = &pfc->info->pins[i];
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struct sh_pfc_pin_config *cfg = &pmx->configs[i];
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struct pinctrl_pin_desc *pin = &pmx->pins[i];
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for (number = range->begin; number <= range->end;
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number++, nr_pins++) {
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struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
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struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
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const struct sh_pfc_pin *info =
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&pfc->info->pins[nr_pins];
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pin->number = number;
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pin->name = info->name;
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cfg->type = PINMUX_TYPE_NONE;
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}
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/* If the pin number is equal to -1 all pins are considered */
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pin->number = info->pin != (u16)-1 ? info->pin : i;
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pin->name = info->name;
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cfg->type = PINMUX_TYPE_NONE;
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}
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pfc->nr_gpio_pins = ranges[nr_ranges-1].end + 1;
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return nr_ranges;
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return 0;
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}
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int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
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{
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struct sh_pfc_pinctrl *pmx;
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int nr_ranges;
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int ret;
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pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
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if (unlikely(!pmx))
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@ -649,9 +628,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
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pmx->pfc = pfc;
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pfc->pinctrl = pmx;
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nr_ranges = sh_pfc_map_pins(pfc, pmx);
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if (unlikely(nr_ranges < 0))
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return nr_ranges;
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ret = sh_pfc_map_pins(pfc, pmx);
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if (ret < 0)
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return ret;
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pmx->pctl_desc.name = DRV_NAME;
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pmx->pctl_desc.owner = THIS_MODULE;
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@ -125,8 +125,6 @@ struct sh_pfc_soc_info {
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const struct sh_pfc_pin *pins;
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unsigned int nr_pins;
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const struct pinmux_range *ranges;
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unsigned int nr_ranges;
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const struct sh_pfc_pin_group *groups;
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unsigned int nr_groups;
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const struct sh_pfc_function *functions;
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