From 33aa46f252c703e42c81a76696cd0c240f2281e4 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Wed, 25 Mar 2020 15:03:35 +0100 Subject: [PATCH 01/11] cpufreq: intel_pstate: Use passive mode by default without HWP After recent changes allowing scale-invariant utilization to be used on x86, the schedutil governor on top of intel_pstate in the passive mode should be on par with (or better than) the active mode "powersave" algorithm of intel_pstate on systems in which hardware-managed P-states (HWP) are not used, so it should not be necessary to use the internal scaling algorithm in those cases. Accordingly, modify intel_pstate to start in the passive mode by default if the processor at hand does not support HWP of if the driver is requested to avoid using HWP through the kernel command line. Among other things, that will allow utilization clamps and the support for RT/DL tasks in the schedutil governor to be utilized on systems in which intel_pstate is used. Signed-off-by: Rafael J. Wysocki --- Documentation/admin-guide/pm/intel_pstate.rst | 32 +++++++++++-------- drivers/cpufreq/intel_pstate.c | 3 +- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/Documentation/admin-guide/pm/intel_pstate.rst b/Documentation/admin-guide/pm/intel_pstate.rst index ad392f3aee06..39d80bc29ccd 100644 --- a/Documentation/admin-guide/pm/intel_pstate.rst +++ b/Documentation/admin-guide/pm/intel_pstate.rst @@ -62,9 +62,10 @@ on the capabilities of the processor. Active Mode ----------- -This is the default operation mode of ``intel_pstate``. If it works in this -mode, the ``scaling_driver`` policy attribute in ``sysfs`` for all ``CPUFreq`` -policies contains the string "intel_pstate". +This is the default operation mode of ``intel_pstate`` for processors with +hardware-managed P-states (HWP) support. If it works in this mode, the +``scaling_driver`` policy attribute in ``sysfs`` for all ``CPUFreq`` policies +contains the string "intel_pstate". In this mode the driver bypasses the scaling governors layer of ``CPUFreq`` and provides its own scaling algorithms for P-state selection. Those algorithms @@ -138,12 +139,13 @@ internal P-state selection logic to be less performance-focused. Active Mode Without HWP ~~~~~~~~~~~~~~~~~~~~~~~ -This is the default operation mode for processors that do not support the HWP -feature. It also is used by default with the ``intel_pstate=no_hwp`` argument -in the kernel command line. However, in this mode ``intel_pstate`` may refuse -to work with the given processor if it does not recognize it. [Note that -``intel_pstate`` will never refuse to work with any processor with the HWP -feature enabled.] +This operation mode is optional for processors that do not support the HWP +feature or when the ``intel_pstate=no_hwp`` argument is passed to the kernel in +the command line. The active mode is used in those cases if the +``intel_pstate=active`` argument is passed to the kernel in the command line. +In this mode ``intel_pstate`` may refuse to work with processors that are not +recognized by it. [Note that ``intel_pstate`` will never refuse to work with +any processor with the HWP feature enabled.] In this mode ``intel_pstate`` registers utilization update callbacks with the CPU scheduler in order to run a P-state selection algorithm, either @@ -188,10 +190,14 @@ is not set. Passive Mode ------------ -This mode is used if the ``intel_pstate=passive`` argument is passed to the -kernel in the command line (it implies the ``intel_pstate=no_hwp`` setting too). -Like in the active mode without HWP support, in this mode ``intel_pstate`` may -refuse to work with the given processor if it does not recognize it. +This is the default operation mode of ``intel_pstate`` for processors without +hardware-managed P-states (HWP) support. It is always used if the +``intel_pstate=passive`` argument is passed to the kernel in the command line +regardless of whether or not the given processor supports HWP. [Note that the +``intel_pstate=no_hwp`` setting implies ``intel_pstate=passive`` if it is used +without ``intel_pstate=active``.] Like in the active mode without HWP support, +in this mode ``intel_pstate`` may refuse to work with processors that are not +recognized by it. If the driver works in this mode, the ``scaling_driver`` policy attribute in ``sysfs`` for all ``CPUFreq`` policies contains the string "intel_cpufreq". diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 4d1e25d1ced1..66ab6523c3eb 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -2771,6 +2771,8 @@ static int __init intel_pstate_init(void) pr_info("Invalid MSRs\n"); return -ENODEV; } + /* Without HWP start in the passive mode. */ + default_driver = &intel_cpufreq; hwp_cpu_matched: /* @@ -2816,7 +2818,6 @@ static int __init intel_pstate_setup(char *str) if (!strcmp(str, "disable")) { no_load = 1; } else if (!strcmp(str, "passive")) { - pr_info("Passive mode enabled\n"); default_driver = &intel_cpufreq; no_hwp = 1; } From 59b55c1f204608cdc2a767c8c969d9ccfd820ec7 Mon Sep 17 00:00:00 2001 From: Anders Roxell Date: Wed, 15 Apr 2020 10:15:59 +0200 Subject: [PATCH 02/11] cpufreq: omap: Build driver by default for ARCH_OMAP2PLUS When building the mult_v7_defconfig, ARM_TI_CPUFREQ doesn't get enabled evenwhen ARCH_OMAP(3|4) is selected. Build ARM_TI_CPUFREQ by default for ARCH_OMAP2PLUS. Signed-off-by: Anders Roxell Signed-off-by: Viresh Kumar --- drivers/cpufreq/Kconfig.arm | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 15c1a1231516..9481292981f0 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -317,6 +317,7 @@ config ARM_TEGRA186_CPUFREQ config ARM_TI_CPUFREQ bool "Texas Instruments CPUFreq support" depends on ARCH_OMAP2PLUS + default ARCH_OMAP2PLUS help This driver enables valid OPPs on the running platform based on values contained within the SoC in use. Enable this in order to From a08e1b6c2d0b9ab7889ac1f7b5c535affbe5032e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Apr 2020 15:55:13 +0800 Subject: [PATCH 03/11] cpufreq: Add i.MX7ULP to cpufreq-dt-platdev blacklist Add i.MX7ULP to cpufreq-dt-platdev blacklist. Signed-off-by: Peng Fan Signed-off-by: Viresh Kumar --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index cb9db16bea61..5c8baf603e05 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -105,6 +105,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "calxeda,highbank", }, { .compatible = "calxeda,ecx-2000", }, + { .compatible = "fsl,imx7ulp", }, { .compatible = "fsl,imx7d", }, { .compatible = "fsl,imx8mq", }, { .compatible = "fsl,imx8mm", }, From a6d1bfa05545b0d34f5b5093248b10a745c050e3 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 27 Apr 2020 13:53:30 +0100 Subject: [PATCH 04/11] cpufreq: dt: Add support for r8a7742 Add the compatible strings for supporting the generic cpufreq driver on the Renesas RZ/G1H (R8A7742) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Geert Uytterhoeven Signed-off-by: Viresh Kumar --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 5c8baf603e05..e8e20fef400b 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -53,6 +53,7 @@ static const struct of_device_id whitelist[] __initconst = { { .compatible = "renesas,r7s72100", }, { .compatible = "renesas,r8a73a4", }, { .compatible = "renesas,r8a7740", }, + { .compatible = "renesas,r8a7742", }, { .compatible = "renesas,r8a7743", }, { .compatible = "renesas,r8a7744", }, { .compatible = "renesas,r8a7745", }, From 7c2553f0db6133ba079597422391661914ce91c7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Apr 2020 15:21:00 +0800 Subject: [PATCH 05/11] cpufreq: imx-cpufreq-dt: support i.MX7ULP i.MX7ULP's ARM core clock design is totally different compared with i.MX7D/8M SoCs which supported by imx-cpufreq-dt. It needs get_intermediate and target_intermedate to configure clk MUX ready, before let OPP configure ARM core clk. |---FIRC |------RUN---...---SCS(MUX2) --------| ARM --(MUX1) |---SPLL_PFD0(CLK_SET_RATE_GATE) |------HSRUN--...--HSRUN_SCS(MUX3)---| |---SRIC FIRC is step clk, SPLL_PFD0 is the normal clk driving ARM core. MUX2 and MUX3 share same inputs. So if MUX2/MUX3 both sources from SPLL_PFD0, both MUXes will lose input when configure SPLL_PFD0. So the target_intermediate will configure MUX2/MUX3 to FIRC, to avoid ARM core lose clk when configure SPLL_PFD0. Signed-off-by: Peng Fan Signed-off-by: Viresh Kumar --- drivers/cpufreq/imx-cpufreq-dt.c | 84 +++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c index de206d2745fe..3fe9125156b4 100644 --- a/drivers/cpufreq/imx-cpufreq-dt.c +++ b/drivers/cpufreq/imx-cpufreq-dt.c @@ -3,7 +3,9 @@ * Copyright 2019 NXP */ +#include #include +#include #include #include #include @@ -12,8 +14,11 @@ #include #include #include +#include #include +#include "cpufreq-dt.h" + #define OCOTP_CFG3_SPEED_GRADE_SHIFT 8 #define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8) #define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8) @@ -22,20 +27,92 @@ #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5 #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5) +#define IMX7ULP_MAX_RUN_FREQ 528000 + /* cpufreq-dt device registered by imx-cpufreq-dt */ static struct platform_device *cpufreq_dt_pdev; static struct opp_table *cpufreq_opp_table; +static struct device *cpu_dev; + +enum IMX7ULP_CPUFREQ_CLKS { + ARM, + CORE, + SCS_SEL, + HSRUN_CORE, + HSRUN_SCS_SEL, + FIRC, +}; + +static struct clk_bulk_data imx7ulp_clks[] = { + { .id = "arm" }, + { .id = "core" }, + { .id = "scs_sel" }, + { .id = "hsrun_core" }, + { .id = "hsrun_scs_sel" }, + { .id = "firc" }, +}; + +static unsigned int imx7ulp_get_intermediate(struct cpufreq_policy *policy, + unsigned int index) +{ + return clk_get_rate(imx7ulp_clks[FIRC].clk); +} + +static int imx7ulp_target_intermediate(struct cpufreq_policy *policy, + unsigned int index) +{ + unsigned int newfreq = policy->freq_table[index].frequency; + + clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk); + clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk); + + if (newfreq > IMX7ULP_MAX_RUN_FREQ) + clk_set_parent(imx7ulp_clks[ARM].clk, + imx7ulp_clks[HSRUN_CORE].clk); + else + clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); + + return 0; +} + +static struct cpufreq_dt_platform_data imx7ulp_data = { + .target_intermediate = imx7ulp_target_intermediate, + .get_intermediate = imx7ulp_get_intermediate, +}; static int imx_cpufreq_dt_probe(struct platform_device *pdev) { - struct device *cpu_dev = get_cpu_device(0); + struct platform_device *dt_pdev; u32 cell_value, supported_hw[2]; int speed_grade, mkt_segment; int ret; + cpu_dev = get_cpu_device(0); + if (!of_find_property(cpu_dev->of_node, "cpu-supply", NULL)) return -ENODEV; + if (of_machine_is_compatible("fsl,imx7ulp")) { + ret = clk_bulk_get(cpu_dev, ARRAY_SIZE(imx7ulp_clks), + imx7ulp_clks); + if (ret) + return ret; + + dt_pdev = platform_device_register_data(NULL, "cpufreq-dt", + -1, &imx7ulp_data, + sizeof(imx7ulp_data)); + if (IS_ERR(dt_pdev)) { + clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks); + ret = PTR_ERR(dt_pdev); + dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret); + return ret; + } + + cpufreq_dt_pdev = dt_pdev; + + return 0; + } + ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value); if (ret) return ret; @@ -98,7 +175,10 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev) static int imx_cpufreq_dt_remove(struct platform_device *pdev) { platform_device_unregister(cpufreq_dt_pdev); - dev_pm_opp_put_supported_hw(cpufreq_opp_table); + if (!of_machine_is_compatible("fsl,imx7ulp")) + dev_pm_opp_put_supported_hw(cpufreq_opp_table); + else + clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks); return 0; } From 2dea651680cea1f3a29925de51002f33d1f55711 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Fri, 1 May 2020 00:22:25 +0200 Subject: [PATCH 06/11] cpufreq: qcom: fix wrong compatible binding Binding in Documentation is still "operating-points-v2-kryo-cpu". Restore the old binding to fix the compatibility problem. Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs") Signed-off-by: Ansuel Smith Signed-off-by: Viresh Kumar --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index a1b8238872a2..d06b37822c3d 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -277,7 +277,7 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) if (!np) return -ENOENT; - ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu"); + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); if (!ret) { of_node_put(np); return -ENOENT; From 157f527639da13c45b87adfc59ca6f6d354b8530 Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Tue, 21 Apr 2020 10:29:59 +0200 Subject: [PATCH 07/11] cpufreq: qoriq: convert to a platform driver The driver has to be manually loaded if it is built as a module. It is neither exporting MODULE_DEVICE_TABLE nor MODULE_ALIAS. Moreover, no platform-device is created (and thus no uevent is sent) for the clockgen nodes it depends on. Convert the module to a platform driver with its own alias. Moreover, drop whitelisted SOCs. Platform device will be created only for the compatible platforms. Reviewed-by: Yuantian Tang Acked-by: Viresh Kumar Signed-off-by: Mian Yousaf Kaukab Signed-off-by: Viresh Kumar --- drivers/cpufreq/qoriq-cpufreq.c | 78 +++++++++++++-------------------- 1 file changed, 30 insertions(+), 48 deletions(-) diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c index 8e436dc75c8b..6b6b20da2bcf 100644 --- a/drivers/cpufreq/qoriq-cpufreq.c +++ b/drivers/cpufreq/qoriq-cpufreq.c @@ -18,6 +18,7 @@ #include #include #include +#include /** * struct cpu_data @@ -29,12 +30,6 @@ struct cpu_data { struct cpufreq_frequency_table *table; }; -/* - * Don't use cpufreq on this SoC -- used when the SoC would have otherwise - * matched a more generic compatible. - */ -#define SOC_BLACKLIST 1 - /** * struct soc_data - SoC specific data * @flags: SOC_xxx @@ -264,64 +259,51 @@ static struct cpufreq_driver qoriq_cpufreq_driver = { .attr = cpufreq_generic_attr, }; -static const struct soc_data blacklist = { - .flags = SOC_BLACKLIST, -}; - -static const struct of_device_id node_matches[] __initconst = { +static const struct of_device_id qoriq_cpufreq_blacklist[] = { /* e6500 cannot use cpufreq due to erratum A-008083 */ - { .compatible = "fsl,b4420-clockgen", &blacklist }, - { .compatible = "fsl,b4860-clockgen", &blacklist }, - { .compatible = "fsl,t2080-clockgen", &blacklist }, - { .compatible = "fsl,t4240-clockgen", &blacklist }, - - { .compatible = "fsl,ls1012a-clockgen", }, - { .compatible = "fsl,ls1021a-clockgen", }, - { .compatible = "fsl,ls1028a-clockgen", }, - { .compatible = "fsl,ls1043a-clockgen", }, - { .compatible = "fsl,ls1046a-clockgen", }, - { .compatible = "fsl,ls1088a-clockgen", }, - { .compatible = "fsl,ls2080a-clockgen", }, - { .compatible = "fsl,lx2160a-clockgen", }, - { .compatible = "fsl,p4080-clockgen", }, - { .compatible = "fsl,qoriq-clockgen-1.0", }, - { .compatible = "fsl,qoriq-clockgen-2.0", }, + { .compatible = "fsl,b4420-clockgen", }, + { .compatible = "fsl,b4860-clockgen", }, + { .compatible = "fsl,t2080-clockgen", }, + { .compatible = "fsl,t4240-clockgen", }, {} }; -static int __init qoriq_cpufreq_init(void) +static int qoriq_cpufreq_probe(struct platform_device *pdev) { int ret; - struct device_node *np; - const struct of_device_id *match; - const struct soc_data *data; + struct device_node *np; - np = of_find_matching_node(NULL, node_matches); - if (!np) - return -ENODEV; - - match = of_match_node(node_matches, np); - data = match->data; - - of_node_put(np); - - if (data && data->flags & SOC_BLACKLIST) + np = of_find_matching_node(NULL, qoriq_cpufreq_blacklist); + if (np) { + dev_info(&pdev->dev, "Disabling due to erratum A-008083"); return -ENODEV; + } ret = cpufreq_register_driver(&qoriq_cpufreq_driver); - if (!ret) - pr_info("Freescale QorIQ CPU frequency scaling driver\n"); + if (ret) + return ret; - return ret; + dev_info(&pdev->dev, "Freescale QorIQ CPU frequency scaling driver\n"); + return 0; } -module_init(qoriq_cpufreq_init); -static void __exit qoriq_cpufreq_exit(void) +static int qoriq_cpufreq_remove(struct platform_device *pdev) { cpufreq_unregister_driver(&qoriq_cpufreq_driver); -} -module_exit(qoriq_cpufreq_exit); + return 0; +} + +static struct platform_driver qoriq_cpufreq_platform_driver = { + .driver = { + .name = "qoriq-cpufreq", + }, + .probe = qoriq_cpufreq_probe, + .remove = qoriq_cpufreq_remove, +}; +module_platform_driver(qoriq_cpufreq_platform_driver); + +MODULE_ALIAS("platform:qoriq-cpufreq"); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Tang Yuantian "); MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs"); From cf1e0449ac478e419daf3c3f03721878fe7fa2be Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Tue, 21 Apr 2020 10:30:00 +0200 Subject: [PATCH 08/11] clk: qoriq: add cpufreq platform device Add a platform device for qoirq-cpufreq driver for the compatible clockgen blocks. Reviewed-by: Yuantian Tang Acked-by: Viresh Kumar Signed-off-by: Mian Yousaf Kaukab Acked-by: Stephen Boyd Signed-off-by: Viresh Kumar --- drivers/clk/clk-qoriq.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index d5946f7486d6..374afcab89af 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -95,6 +95,7 @@ struct clockgen { }; static struct clockgen clockgen; +static bool add_cpufreq_dev __initdata; static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) { @@ -1019,7 +1020,7 @@ static void __init create_muxes(struct clockgen *cg) } } -static void __init clockgen_init(struct device_node *np); +static void __init _clockgen_init(struct device_node *np, bool legacy); /* * Legacy nodes may get probed before the parent clockgen node. @@ -1030,7 +1031,7 @@ static void __init clockgen_init(struct device_node *np); static void __init legacy_init_clockgen(struct device_node *np) { if (!clockgen.node) - clockgen_init(of_get_parent(np)); + _clockgen_init(of_get_parent(np), true); } /* Legacy node */ @@ -1447,7 +1448,7 @@ static bool __init has_erratum_a4510(void) } #endif -static void __init clockgen_init(struct device_node *np) +static void __init _clockgen_init(struct device_node *np, bool legacy) { int i, ret; bool is_old_ls1021a = false; @@ -1516,12 +1517,35 @@ static void __init clockgen_init(struct device_node *np) __func__, np, ret); } + /* Don't create cpufreq device for legacy clockgen blocks */ + add_cpufreq_dev = !legacy; + return; err: iounmap(clockgen.regs); clockgen.regs = NULL; } +static void __init clockgen_init(struct device_node *np) +{ + _clockgen_init(np, false); +} + +static int __init clockgen_cpufreq_init(void) +{ + struct platform_device *pdev; + + if (add_cpufreq_dev) { + pdev = platform_device_register_simple("qoriq-cpufreq", -1, + NULL, 0); + if (IS_ERR(pdev)) + pr_err("Couldn't register qoriq-cpufreq err=%ld\n", + PTR_ERR(pdev)); + } + return 0; +} +device_initcall(clockgen_cpufreq_init); + CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init); From 1f1755af4f062cb1cbd55ca4a250fe272b82fe2f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 May 2020 13:29:53 +0200 Subject: [PATCH 09/11] cpufreq: qoriq: Add platform dependencies The Freescale QorIQ clock controller is only present on Freescale E500MC and Layerscape SoCs. Add platform dependencies to the QORIQ_CPUFREQ config symbol, to avoid asking the user about it when configuring a kernel without E500MC or Layerscape support. Signed-off-by: Geert Uytterhoeven Acked-by: Arnd Bergmann Acked-by: Li Yang Signed-off-by: Viresh Kumar --- drivers/cpufreq/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index c3e6bd59e920..e91750132552 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -323,7 +323,8 @@ endif config QORIQ_CPUFREQ tristate "CPU frequency scaling driver for Freescale QorIQ SoCs" - depends on OF && COMMON_CLK && (PPC_E500MC || ARM || ARM64) + depends on OF && COMMON_CLK + depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST select CLK_QORIQ help This adds the CPUFreq driver support for Freescale QorIQ SoCs From 2909438d4d62681f392c57df4cd6b7183d19dde0 Mon Sep 17 00:00:00 2001 From: Wang Wenhu Date: Wed, 13 May 2020 07:18:54 -0700 Subject: [PATCH 10/11] cpufreq: fix minor typo in struct cpufreq_driver doc comment Delete the duplicate "to", possibly double-typed. Signed-off-by: Wang Wenhu Signed-off-by: Rafael J. Wysocki --- include/linux/cpufreq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index f7240251a949..67d5950bd878 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -330,7 +330,7 @@ struct cpufreq_driver { * * get_intermediate should return a stable intermediate frequency * platform wants to switch to and target_intermediate() should set CPU - * to to that frequency, before jumping to the frequency corresponding + * to that frequency, before jumping to the frequency corresponding * to 'index'. Core will take care of sending notifications and driver * doesn't have to handle them in target_intermediate() or * target_index(). From 552abb884e97d26589964e5a8c7e736f852f95f0 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 18 May 2020 12:49:45 +0200 Subject: [PATCH 11/11] cpufreq: Fix up cpufreq_boost_set_sw() After commit 18c49926c4bf ("cpufreq: Add QoS requests for userspace constraints") the return value of freq_qos_update_request(), that can be 1, passed by cpufreq_boost_set_sw() to its caller sometimes confuses the latter, which only expects to see 0 or negative error codes, so notice that cpufreq_boost_set_sw() can return an error code (which should not be -EINVAL for that matter) as soon as the first policy without a frequency table is found (because either all policies have a frequency table or none of them have it) and rework it to meet its caller's expectations. Fixes: 18c49926c4bf ("cpufreq: Add QoS requests for userspace constraints") Reported-by: Serge Semin Reported-by: Xiongfeng Wang Acked-by: Viresh Kumar Cc: 5.3+ # 5.3+ Signed-off-by: Rafael J. Wysocki --- drivers/cpufreq/cpufreq.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 045f9fe157ce..d03f250f68e4 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2535,26 +2535,27 @@ EXPORT_SYMBOL_GPL(cpufreq_update_limits); static int cpufreq_boost_set_sw(int state) { struct cpufreq_policy *policy; - int ret = -EINVAL; for_each_active_policy(policy) { + int ret; + if (!policy->freq_table) - continue; + return -ENXIO; ret = cpufreq_frequency_table_cpuinfo(policy, policy->freq_table); if (ret) { pr_err("%s: Policy frequency update failed\n", __func__); - break; + return ret; } ret = freq_qos_update_request(policy->max_freq_req, policy->max); if (ret < 0) - break; + return ret; } - return ret; + return 0; } int cpufreq_boost_trigger_state(int state)