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peci: aspeed: Clear clock_divider value before setting it

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PECI clock divider is programmed on 10:8 bits of PECI Control register.
Before setting a new value, clear bits read from hardware.

Reviewed-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20240417134849.5793-1-iwona.winiarska@intel.com
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
This commit is contained in:
Iwona Winiarska 2024-04-17 15:48:49 +02:00
parent a43b9ec091
commit aba59ce109
1 changed files with 1 additions and 0 deletions
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drivers/peci/controller/peci-aspeed.c
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@ -351,6 +351,7 @@ static int clk_aspeed_peci_set_rate(struct clk_hw *hw, unsigned long rate,
clk_aspeed_peci_find_div_values(this_rate, &msg_timing, &clk_div_exp);
val = readl(aspeed_peci->base + ASPEED_PECI_CTRL);
val &= ~ASPEED_PECI_CTRL_CLK_DIV_MASK;
val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, clk_div_exp);
writel(val, aspeed_peci->base + ASPEED_PECI_CTRL);