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Automated merge of kernel.org:/home/rmk/linux-2.6-rmk.git
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Linus Torvalds
commit
ab2fd30b66
@ -18,6 +18,11 @@
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#include <asm/arch/pxa-regs.h>
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#ifdef CONFIG_PXA27x // workaround for Errata 50
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#define MDREFR_KDIV 0x200a4000 // all banks
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#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
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#endif
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.text
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/*
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@ -28,7 +33,9 @@
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ENTRY(pxa_cpu_suspend)
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#ifndef CONFIG_IWMMXT
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mra r2, r3, acc0
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#endif
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stmfd sp!, {r2 - r12, lr} @ save registers on stack
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@ get coprocessor registers
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@ -61,14 +68,23 @@ ENTRY(pxa_cpu_suspend)
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@ prepare value for sleep mode
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mov r1, #3 @ sleep mode
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@ prepare to put SDRAM into self-refresh manually
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ldr r4, =MDREFR
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ldr r5, [r4]
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orr r5, r5, #MDREFR_SLFRSH
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@ prepare pointer to physical address 0 (virtual mapping in generic.c)
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mov r2, #UNCACHED_PHYS_0
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@ prepare SDRAM refresh settings
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ldr r4, =MDREFR
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ldr r5, [r4]
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@ enable SDRAM self-refresh mode
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orr r5, r5, #MDREFR_SLFRSH
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#ifdef CONFIG_PXA27x
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@ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
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ldr r6, =MDREFR_KDIV
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orr r5, r5, r6
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#endif
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#ifdef CONFIG_PXA25x
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@ Intel PXA255 Specification Update notes problems
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@ about suspending with PXBus operating above 133MHz
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@ (see Errata 31, GPIO output signals, ... unpredictable in sleep
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@ -100,6 +116,18 @@ ENTRY(pxa_cpu_suspend)
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mov r0, #0
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mcr p14, 0, r0, c6, c0, 0
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orr r0, r0, #2 @ initiate change bit
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#endif
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#ifdef CONFIG_PXA27x
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@ Intel PXA270 Specification Update notes problems sleeping
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@ with core operating above 91 MHz
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@ (see Errata 50, ...processor does not exit from sleep...)
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ldr r6, =CCCR
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ldr r8, [r6] @ keep original value for resume
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ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
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mov r0, #0x2 @ prepare value for CLKCFG
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#endif
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@ align execution to a cache line
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b 1f
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@ -111,6 +139,7 @@ ENTRY(pxa_cpu_suspend)
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@ All needed values are now in registers.
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@ These last instructions should be in cache
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#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
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@ initiate the frequency change...
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str r7, [r6]
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mcr p14, 0, r0, c6, c0, 0
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@ -118,14 +147,27 @@ ENTRY(pxa_cpu_suspend)
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@ restore the original cpu speed value for resume
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str r8, [r6]
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@ put SDRAM into self-refresh
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str r5, [r4]
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@ need 6 13-MHz cycles before changing PWRMODE
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@ just set frequency to 91-MHz... 6*91/13 = 42
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mov r0, #42
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10: subs r0, r0, #1
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bne 10b
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#endif
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@ Do not reorder...
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@ Intel PXA270 Specification Update notes problems performing
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@ external accesses after SDRAM is put in self-refresh mode
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@ (see Errata 39 ...hangs when entering self-refresh mode)
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@ force address lines low by reading at physical address 0
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ldr r3, [r2]
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@ put SDRAM into self-refresh
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str r5, [r4]
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@ enter sleep mode
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mcr p14, 0, r1, c7, c0, 0
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mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
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20: b 20b @ loop waiting for sleep
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@ -188,7 +230,9 @@ resume_after_mmu:
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bl cpu_xscale_proc_init
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#endif
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ldmfd sp!, {r2, r3}
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#ifndef CONFIG_IWMMXT
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mar acc0, r2, r3
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#endif
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ldmfd sp!, {r4 - r12, pc} @ return to caller
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@ -14,6 +14,7 @@
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* 26-06-2003 BJD Finished off definitions for register addresses
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* 12-03-2004 BJD Updated include protection
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* 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL
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* 05-04-2005 LCVR Added IISFCON definitions for the S3C2400
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*/
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#ifndef __ASM_ARCH_REGS_IIS_H
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@ -68,5 +69,14 @@
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#define S3C2410_IISFCON_RXMASK (0x3f)
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#define S3C2410_IISFCON_RXSHIFT (0)
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#define S3C2400_IISFCON_TXDMA (1<<11)
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#define S3C2400_IISFCON_RXDMA (1<<10)
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#define S3C2400_IISFCON_TXENABLE (1<<9)
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#define S3C2400_IISFCON_RXENABLE (1<<8)
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#define S3C2400_IISFCON_TXMASK (0x07 << 4)
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#define S3C2400_IISFCON_TXSHIFT (4)
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#define S3C2400_IISFCON_RXMASK (0x07)
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#define S3C2400_IISFCON_RXSHIFT (0)
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#define S3C2410_IISFIFO (0x10)
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#endif /* __ASM_ARCH_REGS_IIS_H */
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@ -12,6 +12,7 @@
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* Changelog:
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* 29-Sep-2004 BJD Initial include for Linux
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* 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
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* 04-Apr-2005 LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions
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*
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*/
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@ -183,6 +184,12 @@
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#define S3C2410_REFRESH_TRP_3clk (1<<20)
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#define S3C2410_REFRESH_TRP_4clk (2<<20)
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#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20)
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#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
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#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
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#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
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#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
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#define S3C2410_REFRESH_TSRC_MASK (3<<18)
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#define S3C2410_REFRESH_TSRC_4clk (0<<18)
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#define S3C2410_REFRESH_TSRC_5clk (1<<18)
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@ -205,6 +212,7 @@
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#define S3C2410_BANKSIZE_4M (0x5 << 0)
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#define S3C2410_BANKSIZE_2M (0x4 << 0)
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#define S3C2410_BANKSIZE_MASK (0x7 << 0)
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#define S3C2400_BANKSIZE_MASK (0x4 << 0)
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#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
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#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
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#define S3C2410_BANKSIZE_BURST (1<<7)
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@ -12,6 +12,7 @@
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* 20-04-2004 KF Created file
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* 04-10-2004 BJD Removed VA address (no longer mapped)
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* tidied file for submission
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* 03-04-2005 LCVR Added S3C2400_SPPIN_nCS definition
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*/
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#ifndef __ASM_ARCH_REGS_SPI_H
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@ -46,6 +47,7 @@
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#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
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#define S3C2410_SPPIN_RESERVED (1<<1)
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#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
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#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
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@ -16,6 +16,7 @@
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* 12-Oct-2004 BJD Take account of debug uart configuration
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* 15-Nov-2004 BJD Fixed uart configuration
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* 22-Feb-2005 BJD Added watchdog to uncompress
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* 04-Apr-2005 LCVR Added support to S3C2400 (no cpuid at GSTATUS1)
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*/
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#ifndef __ASM_ARCH_UNCOMPRESS_H
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@ -69,9 +70,12 @@ uart_rd(unsigned int reg)
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static void
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putc(char ch)
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{
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int cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
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int cpuid = S3C2410_GSTATUS1_2410;
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#ifndef CONFIG_CPU_S3C2400
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cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
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cpuid &= S3C2410_GSTATUS1_IDMASK;
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#endif
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if (ch == '\n')
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putc('\r'); /* expand newline to \r\n */
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@ -29,15 +29,22 @@ extern void __memzero(void *ptr, __kernel_size_t n);
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#define memset(p,v,n) \
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({ \
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if ((n) != 0) { \
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void *__p = (p); size_t __n = n; \
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if ((__n) != 0) { \
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if (__builtin_constant_p((v)) && (v) == 0) \
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__memzero((p),(n)); \
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__memzero((__p),(__n)); \
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else \
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memset((p),(v),(n)); \
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memset((__p),(v),(__n)); \
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} \
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(p); \
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(__p); \
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})
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#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
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#define memzero(p,n) \
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({ \
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void *__p = (p); size_t __n = n; \
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if ((__n) != 0) \
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__memzero((__p),(__n)); \
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(__p); \
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})
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#endif
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