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ARM: S3C64XX: Correct reservation of GPIOs for CPU module on Cragganmore

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The gpio_base for the PMIC on the CPU module was being incorrectly set to
be the same as that for the CODEC causing the two GPIO drivers to collide.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Mark Brown 2011-11-03 16:28:15 +09:00 committed by Kukjin Kim
parent 4ff13995b5
commit aaed44e167
2 changed files with 3 additions and 2 deletions
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3
arch/arm/mach-s3c64xx/include/mach/crag6410.h
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@ -17,7 +17,8 @@
#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
#define PCA935X_GPIO_BASE GPIO_BOARD_START
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 32)
#endif

2
arch/arm/mach-s3c64xx/mach-crag6410.c
View File

@ -500,7 +500,7 @@ static struct wm831x_touch_pdata touch_pdata __initdata = {
static struct wm831x_pdata crag_pmic_pdata __initdata = {
.wm831x_num = 1,
.irq_base = BANFF_PMIC_IRQ_BASE,
.gpio_base = GPIO_BOARD_START + 8,
.gpio_base = BANFF_PMIC_GPIO_BASE,
.backup = &banff_backup_pdata,