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usb: dwc3: gadget: allow clock gating to work
The dwc3 core has internal clock gating support. Let's allow that to happen by clearing the disable bit in GCTL register. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -161,6 +161,7 @@
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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#define DWC3_GCTL_SCALEDOWN(n) (n << 4)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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@ -170,6 +171,11 @@
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
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/* Global HWPARAMS1 Register */
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#define DWC3_GHWPARAMS1_EN_PWROPT(n) ((n & (3 << 24)) >> 24)
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#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
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#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
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/* Device Configuration Register */
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#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
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#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
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@ -1164,6 +1164,14 @@ static int dwc3_gadget_start(struct usb_gadget *g,
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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reg |= DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams0)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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dev_dbg(dwc->dev, "No power optimization available\n");
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}
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug
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* when The device fails to connect at SuperSpeed
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