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- 2 fixes: 1 for perf and 1 execlist submission race.
-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJaoA9cAAoJEPpiX2QO6xPKfI8H/1M+nPvIfaqZHpnBSvLhOZ95 py3qBQ72HvAlWaChH0FBAaUkWO7g38buMoUQrXn2d5dwU+RSoRC6AsEQE/ZqntN4 QMYMMqKx8Qnd4zkYcPx2mZD414uKHKYS7TvTK1HrslCexOteDjG7myQxURnrwM3u DvJJzr0FDo5zW6kgT2sA3VXv/Fvc2heExy5QodIoF4ajU/TcU7HqC4ZiMkaigZA6 j4oWrEdf0jukWTLsgzikVwn6j0+HUapKQfHi1/OMn4cf5mTtDTTHqQVE4qjyRhuh oXnVZYWjIn4QL8mK9Ql5yJvjrsQLvxWT24FErPloz9ustl+t9A+6Zx4vPiibOUk= =Wni1 -----END PGP SIGNATURE----- Merge tag 'drm-intel-fixes-2018-03-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - 2 fixes: 1 for perf and 1 execlist submission race. * tag 'drm-intel-fixes-2018-03-07' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915: Suspend submission tasklets around wedging drm/i915/perf: fix perf stream opening lock
This commit is contained in:
commit
aa87d62f7e
@ -3205,8 +3205,10 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
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* rolling the global seqno forward (since this would complete requests
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* for which we haven't set the fence error to EIO yet).
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*/
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for_each_engine(engine, i915, id)
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for_each_engine(engine, i915, id) {
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i915_gem_reset_prepare_engine(engine);
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engine->submit_request = nop_submit_request;
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}
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/*
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* Make sure no one is running the old callback before we proceed with
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@ -3244,6 +3246,8 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
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intel_engine_init_global_seqno(engine,
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intel_engine_last_submit(engine));
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spin_unlock_irqrestore(&engine->timeline->lock, flags);
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i915_gem_reset_finish_engine(engine);
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}
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set_bit(I915_WEDGED, &i915->gpu_error.flags);
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@ -1303,9 +1303,8 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
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*/
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mutex_lock(&dev_priv->drm.struct_mutex);
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dev_priv->perf.oa.exclusive_stream = NULL;
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mutex_unlock(&dev_priv->drm.struct_mutex);
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dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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free_oa_buffer(dev_priv);
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@ -1756,22 +1755,13 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr
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* Note: it's only the RCS/Render context that has any OA state.
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*/
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static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
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const struct i915_oa_config *oa_config,
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bool interruptible)
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const struct i915_oa_config *oa_config)
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{
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struct i915_gem_context *ctx;
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int ret;
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unsigned int wait_flags = I915_WAIT_LOCKED;
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if (interruptible) {
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ret = i915_mutex_lock_interruptible(&dev_priv->drm);
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if (ret)
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return ret;
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wait_flags |= I915_WAIT_INTERRUPTIBLE;
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} else {
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mutex_lock(&dev_priv->drm.struct_mutex);
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}
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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/* Switch away from any user context. */
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ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
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@ -1819,8 +1809,6 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
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}
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out:
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return ret;
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}
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@ -1863,7 +1851,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
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* to make sure all slices/subslices are ON before writing to NOA
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* registers.
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*/
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ret = gen8_configure_all_contexts(dev_priv, oa_config, true);
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ret = gen8_configure_all_contexts(dev_priv, oa_config);
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if (ret)
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return ret;
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@ -1878,7 +1866,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
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static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)
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{
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/* Reset all contexts' slices/subslices configurations. */
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gen8_configure_all_contexts(dev_priv, NULL, false);
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gen8_configure_all_contexts(dev_priv, NULL);
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I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
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~GT_NOA_ENABLE));
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@ -1888,7 +1876,7 @@ static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)
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static void gen10_disable_metric_set(struct drm_i915_private *dev_priv)
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{
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/* Reset all contexts' slices/subslices configurations. */
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gen8_configure_all_contexts(dev_priv, NULL, false);
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gen8_configure_all_contexts(dev_priv, NULL);
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/* Make sure we disable noa to save power. */
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I915_WRITE(RPM_CONFIG1,
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@ -2138,6 +2126,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
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if (ret)
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goto err_oa_buf_alloc;
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ret = i915_mutex_lock_interruptible(&dev_priv->drm);
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if (ret)
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goto err_lock;
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ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv,
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stream->oa_config);
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if (ret)
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@ -2145,23 +2137,17 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
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stream->ops = &i915_oa_stream_ops;
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/* Lock device for exclusive_stream access late because
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* enable_metric_set() might lock as well on gen8+.
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*/
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ret = i915_mutex_lock_interruptible(&dev_priv->drm);
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if (ret)
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goto err_lock;
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dev_priv->perf.oa.exclusive_stream = stream;
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return 0;
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err_lock:
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dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
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err_enable:
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dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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err_lock:
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free_oa_buffer(dev_priv);
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err_oa_buf_alloc:
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@ -719,6 +719,8 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
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struct rb_node *rb;
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unsigned long flags;
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GEM_TRACE("%s\n", engine->name);
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spin_lock_irqsave(&engine->timeline->lock, flags);
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/* Cancel the requests on the HW and clear the ELSP tracker. */
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@ -765,6 +767,9 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
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*/
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clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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/* Mark all CS interrupts as complete */
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execlists->active = 0;
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spin_unlock_irqrestore(&engine->timeline->lock, flags);
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}
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