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clk: renesas: R-Car SYSC PM Domain Preparation
- Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
they can be called by the R-Car SYSC PM Domain driver.
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Merge tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into rcar-sysc-for-v4.7
clk: renesas: R-Car SYSC PM Domain Preparation
- Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
they can be called by the R-Car SYSC PM Domain driver.
This commit is contained in:
Simon Horman
commit
a93fed0956
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@ -201,6 +201,7 @@ source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/hisilicon/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/ti/Kconfig"
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16
drivers/clk/renesas/Kconfig
Normal file
16
drivers/clk/renesas/Kconfig
Normal file
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@ -0,0 +1,16 @@
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config CLK_RENESAS_CPG_MSSR
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bool
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default y if ARCH_R8A7795
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config CLK_RENESAS_CPG_MSTP
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bool
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default y if ARCH_R7S72100
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default y if ARCH_R8A73A4
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default y if ARCH_R8A7740
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default y if ARCH_R8A7778
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default y if ARCH_R8A7779
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default y if ARCH_R8A7790
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default y if ARCH_R8A7791
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default y if ARCH_R8A7793
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default y if ARCH_R8A7794
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default y if ARCH_SH73A0
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@ -1,13 +1,15 @@
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obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o clk-mstp.o
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obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o clk-mstp.o
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obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o clk-mstp.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
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r8a7795-cpg-mssr.o clk-div6.o
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obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
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obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o
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obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o
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obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
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obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
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@ -243,9 +243,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
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}
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CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
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#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
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int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
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int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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struct device_node *np = dev->of_node;
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struct of_phandle_args clkspec;
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@ -297,7 +295,7 @@ fail_put:
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return error;
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}
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void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
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void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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if (!list_empty(&dev->power.subsys_data->clock_list))
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pm_clk_destroy(dev);
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@ -326,4 +324,3 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
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of_genpd_add_provider_simple(np, pd);
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}
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#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
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@ -13,6 +13,7 @@
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*/
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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@ -26,6 +27,7 @@
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#include "renesas-cpg-mssr.h"
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#define CPG_RCKCR 0x240
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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@ -50,6 +52,7 @@ enum clk_ids {
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CLK_S3,
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CLK_SDSRC,
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CLK_SSPSRC,
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CLK_RINT,
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/* Module Clocks */
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MOD_CLK_BASE
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@ -63,8 +66,12 @@ enum r8a7795_clk_types {
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CLK_TYPE_GEN3_PLL3,
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CLK_TYPE_GEN3_PLL4,
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CLK_TYPE_GEN3_SD,
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CLK_TYPE_GEN3_R,
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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@ -102,10 +109,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
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DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
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DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
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DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
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DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
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DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
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DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
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DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
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DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
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DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
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@ -113,6 +120,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
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DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
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DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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};
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static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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@ -139,6 +151,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
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DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
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DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
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DEF_MOD("rwdt0", 402, R8A7795_CLK_R),
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DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
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DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
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@ -148,6 +161,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
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DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
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DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
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DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
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DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),
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@ -578,6 +592,18 @@ struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
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case CLK_TYPE_GEN3_SD:
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return cpg_sd_clk_register(core, base, __clk_get_name(parent));
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case CLK_TYPE_GEN3_R:
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/* RINT is default. Only if EXTALR is populated, we switch to it */
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value = readl(base + CPG_RCKCR) & 0x3f;
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if (clk_get_rate(clks[CLK_EXTALR])) {
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parent = clks[CLK_EXTALR];
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value |= BIT(15);
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}
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writel(value, base + CPG_RCKCR);
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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@ -15,6 +15,7 @@
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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@ -253,7 +254,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
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{
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struct clk *clk = NULL, *parent;
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struct device *dev = priv->dev;
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unsigned int id = core->id;
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unsigned int id = core->id, div = core->div;
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const char *parent_name;
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WARN_DEBUG(id >= priv->num_core_clks);
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@ -266,6 +267,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
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case CLK_TYPE_FF:
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case CLK_TYPE_DIV6P1:
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case CLK_TYPE_DIV6_RO:
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WARN_DEBUG(core->parent >= priv->num_core_clks);
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parent = priv->clks[core->parent];
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if (IS_ERR(parent)) {
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@ -274,13 +276,18 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
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}
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parent_name = __clk_get_name(parent);
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if (core->type == CLK_TYPE_FF) {
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clk = clk_register_fixed_factor(NULL, core->name,
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parent_name, 0,
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core->mult, core->div);
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} else {
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if (core->type == CLK_TYPE_DIV6_RO)
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/* Multiply with the DIV6 register value */
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div *= (readl(priv->base + core->offset) & 0x3f) + 1;
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if (core->type == CLK_TYPE_DIV6P1) {
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clk = cpg_div6_register(core->name, 1, &parent_name,
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priv->base + core->offset);
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} else {
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clk = clk_register_fixed_factor(NULL, core->name,
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parent_name, 0,
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core->mult, div);
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}
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break;
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@ -375,8 +382,6 @@ fail:
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kfree(clock);
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}
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#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
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struct cpg_mssr_clk_domain {
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struct generic_pm_domain genpd;
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struct device_node *np;
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@ -384,6 +389,8 @@ struct cpg_mssr_clk_domain {
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unsigned int core_pm_clks[0];
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};
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static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
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static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
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struct cpg_mssr_clk_domain *pd)
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{
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@ -407,17 +414,20 @@ static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
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}
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}
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static int cpg_mssr_attach_dev(struct generic_pm_domain *genpd,
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struct device *dev)
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int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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struct cpg_mssr_clk_domain *pd =
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container_of(genpd, struct cpg_mssr_clk_domain, genpd);
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struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
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struct device_node *np = dev->of_node;
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struct of_phandle_args clkspec;
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struct clk *clk;
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int i = 0;
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int error;
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if (!pd) {
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dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
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return -EPROBE_DEFER;
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}
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while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
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&clkspec)) {
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if (cpg_mssr_is_pm_clk(&clkspec, pd))
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@ -457,8 +467,7 @@ fail_put:
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return error;
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}
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static void cpg_mssr_detach_dev(struct generic_pm_domain *genpd,
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struct device *dev)
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void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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if (!list_empty(&dev->power.subsys_data->clock_list))
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pm_clk_destroy(dev);
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@ -487,19 +496,11 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
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pm_genpd_init(genpd, &simple_qos_governor, false);
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genpd->attach_dev = cpg_mssr_attach_dev;
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genpd->detach_dev = cpg_mssr_detach_dev;
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cpg_mssr_clk_domain = pd;
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of_genpd_add_provider_simple(np, genpd);
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return 0;
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}
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#else
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static inline int cpg_mssr_add_clk_domain(struct device *dev,
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const unsigned int *core_pm_clks,
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unsigned int num_core_pm_clks)
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{
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return 0;
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||||
}
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#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
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static const struct of_device_id cpg_mssr_match[] = {
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#ifdef CONFIG_ARCH_R8A7795
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|
|
|
|||
|
|
@ -37,6 +37,7 @@ enum clk_types {
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CLK_TYPE_IN, /* External Clock Input */
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
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CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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/* Custom definitions start here */
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CLK_TYPE_CUSTOM,
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|
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@ -53,9 +54,8 @@ enum clk_types {
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DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
|
||||
#define DEF_DIV6P1(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
|
||||
#define DEF_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
|
||||
|
||||
/*
|
||||
* Definitions of Module Clocks
|
||||
|
|
|
|||
|
|
@ -24,12 +24,20 @@ void r8a7778_clocks_init(u32 mode);
|
|||
void r8a7779_clocks_init(u32 mode);
|
||||
void rcar_gen2_clocks_init(u32 mode);
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
|
||||
void cpg_mstp_add_clk_domain(struct device_node *np);
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
|
||||
#ifdef CONFIG_CLK_RENESAS_CPG_MSTP
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
#else
|
||||
static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
|
||||
#define cpg_mstp_attach_dev NULL
|
||||
#define cpg_mstp_detach_dev NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CLK_RENESAS_CPG_MSSR
|
||||
int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
#else
|
||||
#define cpg_mssr_attach_dev NULL
|
||||
#define cpg_mssr_detach_dev NULL
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user