mirror of
https://github.com/torvalds/linux.git
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Merge remote-tracking branches 'regmap/topic/64bit' and 'regmap/topic/irq-type' into regmap-next
This commit is contained in:
Mark Brown
commit
a8d99344c9
@ -543,19 +543,30 @@ bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
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switch (map->cache_word_size) {
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case 1: {
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u8 *cache = base;
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cache[idx] = val;
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break;
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}
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case 2: {
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u16 *cache = base;
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cache[idx] = val;
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break;
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}
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case 4: {
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u32 *cache = base;
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cache[idx] = val;
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break;
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}
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#ifdef CONFIG_64BIT
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case 8: {
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u64 *cache = base;
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cache[idx] = val;
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break;
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}
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#endif
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default:
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BUG();
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}
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@ -576,16 +587,26 @@ unsigned int regcache_get_val(struct regmap *map, const void *base,
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switch (map->cache_word_size) {
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case 1: {
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const u8 *cache = base;
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return cache[idx];
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}
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case 2: {
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const u16 *cache = base;
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return cache[idx];
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}
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case 4: {
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const u32 *cache = base;
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return cache[idx];
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}
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#ifdef CONFIG_64BIT
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case 8: {
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const u64 *cache = base;
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return cache[idx];
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}
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#endif
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default:
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BUG();
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}
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@ -39,8 +39,11 @@ struct regmap_irq_chip_data {
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unsigned int *mask_buf;
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unsigned int *mask_buf_def;
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unsigned int *wake_buf;
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unsigned int *type_buf;
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unsigned int *type_buf_def;
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unsigned int irq_reg_stride;
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unsigned int type_reg_stride;
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};
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static inline const
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@ -144,6 +147,22 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
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}
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}
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for (i = 0; i < d->chip->num_type_reg; i++) {
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if (!d->type_buf_def[i])
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continue;
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reg = d->chip->type_base +
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(i * map->reg_stride * d->type_reg_stride);
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if (d->chip->type_invert)
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ret = regmap_update_bits(d->map, reg,
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d->type_buf_def[i], ~d->type_buf[i]);
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else
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ret = regmap_update_bits(d->map, reg,
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d->type_buf_def[i], d->type_buf[i]);
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if (ret != 0)
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dev_err(d->map->dev, "Failed to sync type in %x\n",
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reg);
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}
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if (d->chip->runtime_pm)
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pm_runtime_put(map->dev);
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@ -178,6 +197,38 @@ static void regmap_irq_disable(struct irq_data *data)
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d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
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}
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static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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int reg = irq_data->type_reg_offset / map->reg_stride;
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if (!(irq_data->type_rising_mask | irq_data->type_falling_mask))
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return 0;
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d->type_buf[reg] &= ~(irq_data->type_falling_mask |
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irq_data->type_rising_mask);
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switch (type) {
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case IRQ_TYPE_EDGE_FALLING:
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d->type_buf[reg] |= irq_data->type_falling_mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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d->type_buf[reg] |= irq_data->type_rising_mask;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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d->type_buf[reg] |= (irq_data->type_falling_mask |
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irq_data->type_rising_mask);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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@ -204,6 +255,7 @@ static const struct irq_chip regmap_irq_chip = {
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.irq_bus_sync_unlock = regmap_irq_sync_unlock,
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.irq_disable = regmap_irq_disable,
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.irq_enable = regmap_irq_enable,
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.irq_set_type = regmap_irq_set_type,
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.irq_set_wake = regmap_irq_set_wake,
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};
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@ -408,6 +460,18 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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goto err_alloc;
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}
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if (chip->num_type_reg) {
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d->type_buf_def = kcalloc(chip->num_type_reg,
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sizeof(unsigned int), GFP_KERNEL);
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if (!d->type_buf_def)
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goto err_alloc;
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d->type_buf = kcalloc(chip->num_type_reg, sizeof(unsigned int),
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GFP_KERNEL);
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if (!d->type_buf)
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goto err_alloc;
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}
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d->irq_chip = regmap_irq_chip;
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d->irq_chip.name = chip->name;
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d->irq = irq;
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@ -420,6 +484,11 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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else
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d->irq_reg_stride = 1;
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if (chip->type_reg_stride)
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d->type_reg_stride = chip->type_reg_stride;
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else
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d->type_reg_stride = 1;
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if (!map->use_single_read && map->reg_stride == 1 &&
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d->irq_reg_stride == 1) {
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d->status_reg_buf = kmalloc_array(chip->num_regs,
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@ -512,6 +581,33 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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}
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}
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if (chip->num_type_reg) {
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for (i = 0; i < chip->num_irqs; i++) {
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reg = chip->irqs[i].type_reg_offset / map->reg_stride;
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d->type_buf_def[reg] |= chip->irqs[i].type_rising_mask |
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chip->irqs[i].type_falling_mask;
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}
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for (i = 0; i < chip->num_type_reg; ++i) {
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if (!d->type_buf_def[i])
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continue;
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reg = chip->type_base +
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(i * map->reg_stride * d->type_reg_stride);
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if (chip->type_invert)
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ret = regmap_update_bits(map, reg,
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d->type_buf_def[i], 0xFF);
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else
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ret = regmap_update_bits(map, reg,
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d->type_buf_def[i], 0x0);
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if (ret != 0) {
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dev_err(map->dev,
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"Failed to set type in 0x%x: %x\n",
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reg, ret);
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goto err_alloc;
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}
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}
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}
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if (irq_base)
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d->domain = irq_domain_add_legacy(map->dev->of_node,
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chip->num_irqs, irq_base, 0,
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@ -542,6 +638,8 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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err_domain:
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/* Should really dispose of the domain but... */
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err_alloc:
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kfree(d->type_buf);
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kfree(d->type_buf_def);
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kfree(d->wake_buf);
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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@ -565,6 +663,8 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
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free_irq(irq, d);
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irq_domain_remove(d->domain);
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kfree(d->type_buf);
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kfree(d->type_buf_def);
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kfree(d->wake_buf);
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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@ -245,6 +245,28 @@ static void regmap_format_32_native(void *buf, unsigned int val,
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*(u32 *)buf = val << shift;
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}
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#ifdef CONFIG_64BIT
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static void regmap_format_64_be(void *buf, unsigned int val, unsigned int shift)
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{
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__be64 *b = buf;
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b[0] = cpu_to_be64((u64)val << shift);
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}
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static void regmap_format_64_le(void *buf, unsigned int val, unsigned int shift)
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{
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__le64 *b = buf;
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b[0] = cpu_to_le64((u64)val << shift);
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}
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static void regmap_format_64_native(void *buf, unsigned int val,
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unsigned int shift)
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{
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*(u64 *)buf = (u64)val << shift;
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}
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#endif
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static void regmap_parse_inplace_noop(void *buf)
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{
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}
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@ -332,6 +354,41 @@ static unsigned int regmap_parse_32_native(const void *buf)
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return *(u32 *)buf;
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}
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#ifdef CONFIG_64BIT
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static unsigned int regmap_parse_64_be(const void *buf)
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{
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const __be64 *b = buf;
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return be64_to_cpu(b[0]);
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}
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static unsigned int regmap_parse_64_le(const void *buf)
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{
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const __le64 *b = buf;
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return le64_to_cpu(b[0]);
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}
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static void regmap_parse_64_be_inplace(void *buf)
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{
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__be64 *b = buf;
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b[0] = be64_to_cpu(b[0]);
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}
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static void regmap_parse_64_le_inplace(void *buf)
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{
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__le64 *b = buf;
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b[0] = le64_to_cpu(b[0]);
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}
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static unsigned int regmap_parse_64_native(const void *buf)
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{
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return *(u64 *)buf;
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}
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#endif
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static void regmap_lock_mutex(void *__map)
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{
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struct regmap *map = __map;
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@ -712,6 +769,21 @@ struct regmap *__regmap_init(struct device *dev,
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}
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break;
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#ifdef CONFIG_64BIT
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case 64:
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switch (reg_endian) {
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case REGMAP_ENDIAN_BIG:
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map->format.format_reg = regmap_format_64_be;
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break;
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case REGMAP_ENDIAN_NATIVE:
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map->format.format_reg = regmap_format_64_native;
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break;
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default:
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goto err_map;
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}
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break;
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#endif
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default:
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goto err_map;
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}
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@ -771,6 +843,28 @@ struct regmap *__regmap_init(struct device *dev,
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goto err_map;
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}
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break;
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#ifdef CONFIG_64BIT
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case 64:
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switch (val_endian) {
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case REGMAP_ENDIAN_BIG:
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map->format.format_val = regmap_format_64_be;
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map->format.parse_val = regmap_parse_64_be;
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map->format.parse_inplace = regmap_parse_64_be_inplace;
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break;
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case REGMAP_ENDIAN_LITTLE:
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map->format.format_val = regmap_format_64_le;
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map->format.parse_val = regmap_parse_64_le;
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map->format.parse_inplace = regmap_parse_64_le_inplace;
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break;
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case REGMAP_ENDIAN_NATIVE:
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map->format.format_val = regmap_format_64_native;
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map->format.parse_val = regmap_parse_64_native;
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break;
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default:
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goto err_map;
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}
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break;
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#endif
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}
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if (map->format.format_write) {
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@ -2488,11 +2582,19 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
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* we assume that the values are native
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* endian.
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*/
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#ifdef CONFIG_64BIT
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u64 *u64 = val;
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#endif
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u32 *u32 = val;
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u16 *u16 = val;
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u8 *u8 = val;
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switch (map->format.val_bytes) {
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#ifdef CONFIG_64BIT
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case 8:
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u64[i] = ival;
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break;
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#endif
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case 4:
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u32[i] = ival;
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break;
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@ -788,10 +788,16 @@ int regmap_fields_update_bits(struct regmap_field *field, unsigned int id,
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*
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* @reg_offset: Offset of the status/mask register within the bank
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* @mask: Mask used to flag/control the register.
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* @type_reg_offset: Offset register for the irq type setting.
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* @type_rising_mask: Mask bit to configure RISING type irq.
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* @type_falling_mask: Mask bit to configure FALLING type irq.
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*/
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struct regmap_irq {
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unsigned int reg_offset;
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unsigned int mask;
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unsigned int type_reg_offset;
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unsigned int type_rising_mask;
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unsigned int type_falling_mask;
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};
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#define REGMAP_IRQ_REG(_irq, _off, _mask) \
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@ -811,18 +817,23 @@ struct regmap_irq {
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* @ack_base: Base ack address. If zero then the chip is clear on read.
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* Using zero value is possible with @use_ack bit.
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* @wake_base: Base address for wake enables. If zero unsupported.
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* @type_base: Base address for irq type. If zero unsupported.
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* @irq_reg_stride: Stride to use for chips where registers are not contiguous.
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* @init_ack_masked: Ack all masked interrupts once during initalization.
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* @mask_invert: Inverted mask register: cleared bits are masked out.
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* @use_ack: Use @ack register even if it is zero.
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* @ack_invert: Inverted ack register: cleared bits for ack.
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* @wake_invert: Inverted wake register: cleared bits are wake enabled.
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* @type_invert: Invert the type flags.
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* @runtime_pm: Hold a runtime PM lock on the device when accessing it.
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*
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* @num_regs: Number of registers in each control bank.
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* @irqs: Descriptors for individual IRQs. Interrupt numbers are
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* assigned based on the index in the array of the interrupt.
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* @num_irqs: Number of descriptors.
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* @num_type_reg: Number of type registers.
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* @type_reg_stride: Stride to use for chips where type registers are not
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* contiguous.
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*/
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struct regmap_irq_chip {
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const char *name;
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@ -832,6 +843,7 @@ struct regmap_irq_chip {
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unsigned int unmask_base;
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unsigned int ack_base;
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unsigned int wake_base;
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unsigned int type_base;
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unsigned int irq_reg_stride;
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bool init_ack_masked:1;
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bool mask_invert:1;
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@ -839,11 +851,15 @@ struct regmap_irq_chip {
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bool ack_invert:1;
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bool wake_invert:1;
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bool runtime_pm:1;
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bool type_invert:1;
|
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|
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int num_regs;
|
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|
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const struct regmap_irq *irqs;
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int num_irqs;
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int num_type_reg;
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unsigned int type_reg_stride;
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};
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struct regmap_irq_chip_data;
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