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dt-bindings: gpio: Add Tegra234 support

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Extend the existing Tegra186 GPIO controller device tree bindings with
support for the GPIO controller found on Tegra234. The number of pins is
slightly different, but the programming model remains the same.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
[treding@nvidia.com: update device tree bindings]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
Prathamesh Shete 2021-12-10 17:02:03 +01:00 committed by Bartosz Golaszewski
parent 7501815ffd
commit a8b10f3d12
2 changed files with 67 additions and 0 deletions
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4
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
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@ -83,6 +83,8 @@ properties:
- nvidia,tegra186-gpio-aon
- nvidia,tegra194-gpio
- nvidia,tegra194-gpio-aon
- nvidia,tegra234-gpio
- nvidia,tegra234-gpio-aon
reg-names:
items:
@ -149,6 +151,7 @@ allOf:
enum:
- nvidia,tegra186-gpio
- nvidia,tegra194-gpio
- nvidia,tegra234-gpio
then:
properties:
interrupts:
@ -162,6 +165,7 @@ allOf:
enum:
- nvidia,tegra186-gpio-aon
- nvidia,tegra194-gpio-aon
- nvidia,tegra234-gpio-aon
then:
properties:
interrupts:

63
include/dt-bindings/gpio/tegra234-gpio.h Normal file
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@ -0,0 +1,63 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */
/*
* This header provides constants for binding nvidia,tegra234-gpio*.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
#include <dt-bindings/gpio/gpio.h>
/* GPIOs implemented by main GPIO controller */
#define TEGRA234_MAIN_GPIO_PORT_A 0
#define TEGRA234_MAIN_GPIO_PORT_B 1
#define TEGRA234_MAIN_GPIO_PORT_C 2
#define TEGRA234_MAIN_GPIO_PORT_D 3
#define TEGRA234_MAIN_GPIO_PORT_E 4
#define TEGRA234_MAIN_GPIO_PORT_F 5
#define TEGRA234_MAIN_GPIO_PORT_G 6
#define TEGRA234_MAIN_GPIO_PORT_H 7
#define TEGRA234_MAIN_GPIO_PORT_I 8
#define TEGRA234_MAIN_GPIO_PORT_J 9
#define TEGRA234_MAIN_GPIO_PORT_K 10
#define TEGRA234_MAIN_GPIO_PORT_L 11
#define TEGRA234_MAIN_GPIO_PORT_M 12
#define TEGRA234_MAIN_GPIO_PORT_N 13
#define TEGRA234_MAIN_GPIO_PORT_P 14
#define TEGRA234_MAIN_GPIO_PORT_Q 15
#define TEGRA234_MAIN_GPIO_PORT_R 16
#define TEGRA234_MAIN_GPIO_PORT_S 17
#define TEGRA234_MAIN_GPIO_PORT_T 18
#define TEGRA234_MAIN_GPIO_PORT_U 19
#define TEGRA234_MAIN_GPIO_PORT_V 20
#define TEGRA234_MAIN_GPIO_PORT_X 21
#define TEGRA234_MAIN_GPIO_PORT_Y 22
#define TEGRA234_MAIN_GPIO_PORT_Z 23
#define TEGRA234_MAIN_GPIO_PORT_AC 24
#define TEGRA234_MAIN_GPIO_PORT_AD 25
#define TEGRA234_MAIN_GPIO_PORT_AE 26
#define TEGRA234_MAIN_GPIO_PORT_AF 27
#define TEGRA234_MAIN_GPIO_PORT_AG 28
#define TEGRA234_MAIN_GPIO(port, offset) \
((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)
/* GPIOs implemented by AON GPIO controller */
#define TEGRA234_AON_GPIO_PORT_AA 0
#define TEGRA234_AON_GPIO_PORT_BB 1
#define TEGRA234_AON_GPIO_PORT_CC 2
#define TEGRA234_AON_GPIO_PORT_DD 3
#define TEGRA234_AON_GPIO_PORT_EE 4
#define TEGRA234_AON_GPIO_PORT_GG 5
#define TEGRA234_AON_GPIO(port, offset) \
((TEGRA234_AON_GPIO_PORT_##port * 8) + offset)
#endif