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ARM: OMAP5 / DRA7: PM: Update CPU context register offset
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same context offset as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [rnayak@ti.com: for DRA7] Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: rebase, split/merge etc..] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
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@ -56,6 +56,7 @@
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#include "omap4-sar-layout.h"
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#include "pm.h"
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#include "prcm_mpu44xx.h"
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#include "prcm_mpu54xx.h"
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#include "prminst44xx.h"
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#include "prcm44xx.h"
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#include "prm44xx.h"
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@ -89,6 +90,7 @@ struct cpu_pm_ops {
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static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
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static struct powerdomain *mpuss_pd;
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static void __iomem *sar_base;
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static u32 cpu_context_offset;
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static int default_finish_suspend(unsigned long cpu_state)
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{
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@ -161,14 +163,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
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if (cpu_id) {
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reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
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OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
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cpu_context_offset);
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omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
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OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
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cpu_context_offset);
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} else {
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reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
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OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
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cpu_context_offset);
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omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
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OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
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cpu_context_offset);
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}
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}
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@ -392,6 +394,9 @@ int __init omap4_mpuss_init(void)
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omap_pm_ops.finish_suspend = omap4_finish_suspend;
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omap_pm_ops.resume = omap4_cpu_resume;
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omap_pm_ops.scu_prepare = scu_pwrst_prepare;
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cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
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} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
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cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
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}
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return 0;
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