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drm/i915: fix hsw uncached pte
They've changed it ... for no apparent reason. Meh. V2: remove unused 'is_hsw' field. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
b6c7488df6
commit
a843af186c
@ -64,6 +64,7 @@
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#define I830_PTE_SYSTEM_CACHED 0x00000006
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/* GT PTE cache control fields */
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#define GEN6_PTE_UNCACHED 0x00000002
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#define HSW_PTE_UNCACHED 0x00000000
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#define GEN6_PTE_LLC 0x00000004
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#define GEN6_PTE_LLC_MLC 0x00000006
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#define GEN6_PTE_GFDT 0x00000008
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@ -1156,6 +1156,30 @@ static bool gen6_check_flags(unsigned int flags)
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return true;
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}
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static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
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unsigned int flags)
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{
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unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
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unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
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u32 pte_flags;
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if (type_mask == AGP_USER_MEMORY)
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pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
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else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
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pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
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if (gfdt)
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pte_flags |= GEN6_PTE_GFDT;
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} else { /* set 'normal'/'cached' to LLC by default */
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pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
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if (gfdt)
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pte_flags |= GEN6_PTE_GFDT;
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}
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/* gen6 has bit11-4 for physical addr bit39-32 */
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addr |= (addr >> 28) & 0xff0;
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writel(addr | pte_flags, intel_private.gtt + entry);
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}
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static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
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unsigned int flags)
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{
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@ -1382,6 +1406,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
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.check_flags = gen6_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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static const struct intel_gtt_driver haswell_gtt_driver = {
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.gen = 6,
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.setup = i9xx_setup,
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.cleanup = gen6_cleanup,
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.write_entry = haswell_write_entry,
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.dma_mask_size = 40,
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.check_flags = gen6_check_flags,
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.chipset_flush = i9xx_chipset_flush,
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};
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static const struct intel_gtt_driver valleyview_gtt_driver = {
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.gen = 7,
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.setup = i9xx_setup,
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@ -1499,77 +1532,77 @@ static const struct intel_gtt_driver_description {
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{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
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"ValleyView", &valleyview_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
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"Haswell", &sandybridge_gtt_driver },
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"Haswell", &haswell_gtt_driver },
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{ 0, NULL, NULL }
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};
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@ -261,7 +261,10 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
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pte_flags |= GEN6_PTE_CACHE_LLC;
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break;
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case I915_CACHE_NONE:
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pte_flags |= GEN6_PTE_UNCACHED;
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if (IS_HASWELL(dev))
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pte_flags |= HSW_PTE_UNCACHED;
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else
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pte_flags |= GEN6_PTE_UNCACHED;
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break;
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default:
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BUG();
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@ -115,6 +115,7 @@
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#define GEN6_PTE_VALID (1 << 0)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define HSW_PTE_UNCACHED (0)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
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#define GEN6_PTE_CACHE_BITS (3 << 1)
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