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- Type-C programming fix for MTL+ (Gustavo)

Browse Source 
- Fix display clock workaround (Mitul)
  - Fix DP LTTPR detection (Imre)
  - Calculate vblank delay more accurately (Ville)
  - Make vrr_{enabling,disabling}() usable outside intel_display.c (Ville)
  - FBC clean-up (Ville)
  - DP link-training fixes and clean-up (Imre)
  - Make I2C terminology more inclusive (Easwar)
  - Make read-only array bw_gbps static const (Colin)
  - HDCP fixes and improvements (Suraj)
  - DP VSC SDP fixes and clean-ups (Suraj, Mitul)
  - Fix opregion leak in Xe code (Lucas)
  - Fix possible int overflow in skl_ddi_calculate_wrpll (Nikita)]
  - General display clean-ups and conversion towards intel_display (Jani)
  - On DP MST, Enable LT fallback for UHBR<->non-UHBR rates (Imre)
  - Add VRR condition for DPKGC Enablement (Suraj)
  - Use backlight power constants (Zimmermann)
  - Correct dual pps handling for MTL_PCH+ (Dnyaneshwar)
  - Dump DSC HW state (Imre)
  - Replace double blank with single blank after comma (Andi)
  - Read display register timeout on BMG (Mitul)
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Merge tag 'drm-intel-next-2024-08-13' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

- Type-C programming fix for MTL+ (Gustavo)
 - Fix display clock workaround (Mitul)
 - Fix DP LTTPR detection (Imre)
 - Calculate vblank delay more accurately (Ville)
 - Make vrr_{enabling,disabling}() usable outside intel_display.c (Ville)
 - FBC clean-up (Ville)
 - DP link-training fixes and clean-up (Imre)
 - Make I2C terminology more inclusive (Easwar)
 - Make read-only array bw_gbps static const (Colin)
 - HDCP fixes and improvements (Suraj)
 - DP VSC SDP fixes and clean-ups (Suraj, Mitul)
 - Fix opregion leak in Xe code (Lucas)
 - Fix possible int overflow in skl_ddi_calculate_wrpll (Nikita)]
 - General display clean-ups and conversion towards intel_display (Jani)
 - On DP MST, Enable LT fallback for UHBR<->non-UHBR rates (Imre)
 - Add VRR condition for DPKGC Enablement (Suraj)
 - Use backlight power constants (Zimmermann)
 - Correct dual pps handling for MTL_PCH+ (Dnyaneshwar)
 - Dump DSC HW state (Imre)
 - Replace double blank with single blank after comma (Andi)
 - Read display register timeout on BMG (Mitul)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZruWsyTv3nzdArDk@intel.com
This commit is contained in:
Dave Airlie 2024-08-16 12:56:37 +10:00
commit a809b92ee0
78 changed files with 1819 additions and 1408 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
drivers/gpu/drm/display/drm_dp_mst_topology.c
View File

@ -2339,7 +2339,7 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb,
{
struct drm_dp_mst_topology_mgr *mgr = mstb->mgr;
struct drm_dp_mst_port *port;
int old_ddps = 0, ret;
int ret;
u8 new_pdt = DP_PEER_DEVICE_NONE;
bool new_mcs = 0;
bool created = false, send_link_addr = false, changed = false;
@ -2372,7 +2372,6 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb,
*/
drm_modeset_lock(&mgr->base.lock, NULL);
old_ddps = port->ddps;
changed = port->ddps != port_msg->ddps ||
(port->ddps &&
(port->ldps != port_msg->legacy_device_plug_status ||
@ -2407,15 +2406,13 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb,
* Reprobe PBN caps on both hotplug, and when re-probing the link
* for our parent mstb
*/
if (old_ddps != port->ddps || !created) {
if (port->ddps && !port->input) {
ret = drm_dp_send_enum_path_resources(mgr, mstb,
port);
if (ret == 1)
changed = true;
} else {
port->full_pbn = 0;
}
if (port->ddps && !port->input) {
ret = drm_dp_send_enum_path_resources(mgr, mstb,
port);
if (ret == 1)
changed = true;
} else {
port->full_pbn = 0;
}
ret = drm_dp_port_set_pdt(port, new_pdt, new_mcs);
@ -2692,6 +2689,11 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work)
drm_kms_helper_hotplug_event(dev);
}
static void drm_dp_mst_queue_probe_work(struct drm_dp_mst_topology_mgr *mgr)
{
queue_work(system_long_wq, &mgr->work);
}
static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
u8 *guid)
{
@ -3685,7 +3687,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
/* Write reset payload */
drm_dp_dpcd_write_payload(mgr, 0, 0, 0x3f);
queue_work(system_long_wq, &mgr->work);
drm_dp_mst_queue_probe_work(mgr);
ret = 0;
} else {
@ -3723,6 +3725,33 @@ drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb)
drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb);
}
/**
* drm_dp_mst_topology_queue_probe - Queue a topology probe
* @mgr: manager to probe
*
* Queue a work to probe the MST topology. Driver's should call this only to
* sync the topology's HW->SW state after the MST link's parameters have
* changed in a way the state could've become out-of-sync. This is the case
* for instance when the link rate between the source and first downstream
* branch device has switched between UHBR and non-UHBR rates. Except of those
* cases - for instance when a sink gets plugged/unplugged to a port - the SW
* state will get updated automatically via MST UP message notifications.
*/
void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr)
{
mutex_lock(&mgr->lock);
if (drm_WARN_ON(mgr->dev, !mgr->mst_state || !mgr->mst_primary))
goto out_unlock;
drm_dp_mst_topology_mgr_invalidate_mstb(mgr->mst_primary);
drm_dp_mst_queue_probe_work(mgr);
out_unlock:
mutex_unlock(&mgr->lock);
}
EXPORT_SYMBOL(drm_dp_mst_topology_queue_probe);
/**
* drm_dp_mst_topology_mgr_suspend() - suspend the MST manager
* @mgr: manager to suspend
@ -3809,7 +3838,7 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr,
* state of our in-memory topology back into sync with reality. So,
* restart the probing process as if we're probing a new hub
*/
queue_work(system_long_wq, &mgr->work);
drm_dp_mst_queue_probe_work(mgr);
mutex_unlock(&mgr->lock);
if (sync) {

14
drivers/gpu/drm/i915/display/dvo_ch7017.c
View File

@ -170,13 +170,13 @@ static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)
{
struct i2c_msg msgs[] = {
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 1,
.buf = &addr,
},
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = I2C_M_RD,
.len = 1,
.buf = val,
@ -189,7 +189,7 @@ static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
{
u8 buf[2] = { addr, val };
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 2,
.buf = buf,
@ -197,7 +197,7 @@ static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1;
}
/** Probes for a CH7017 on the given bus and slave address. */
/** Probes for a CH7017 on the given bus and target address. */
static bool ch7017_init(struct intel_dvo_device *dvo,
struct i2c_adapter *adapter)
{
@ -227,13 +227,13 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
break;
default:
DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
"slave %d.\n",
val, adapter->name, dvo->slave_addr);
"target %d.\n",
val, adapter->name, dvo->target_addr);
goto fail;
}
DRM_DEBUG_KMS("%s detected on %s, addr %d\n",
str, adapter->name, dvo->slave_addr);
str, adapter->name, dvo->target_addr);
return true;
fail:

18
drivers/gpu/drm/i915/display/dvo_ch7xxx.c
View File

@ -153,13 +153,13 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
struct i2c_msg msgs[] = {
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 1,
.buf = out_buf,
},
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = I2C_M_RD,
.len = 1,
.buf = in_buf,
@ -176,7 +176,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
if (!ch7xxx->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
}
@ -188,7 +188,7 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
struct i2c_adapter *adapter = dvo->i2c_bus;
u8 out_buf[2];
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 2,
.buf = out_buf,
@ -202,7 +202,7 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
if (!ch7xxx->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
@ -229,8 +229,8 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
name = ch7xxx_get_id(vendor);
if (!name) {
DRM_DEBUG_KMS("ch7xxx not detected; got VID 0x%02x from %s slave %d.\n",
vendor, adapter->name, dvo->slave_addr);
DRM_DEBUG_KMS("ch7xxx not detected; got VID 0x%02x from %s target %d.\n",
vendor, adapter->name, dvo->target_addr);
goto out;
}
@ -240,8 +240,8 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
devid = ch7xxx_get_did(device);
if (!devid) {
DRM_DEBUG_KMS("ch7xxx not detected; got DID 0x%02x from %s slave %d.\n",
device, adapter->name, dvo->slave_addr);
DRM_DEBUG_KMS("ch7xxx not detected; got DID 0x%02x from %s target %d.\n",
device, adapter->name, dvo->target_addr);
goto out;
}

16
drivers/gpu/drm/i915/display/dvo_ivch.c
View File

@ -198,7 +198,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data)
struct i2c_msg msgs[] = {
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = I2C_M_RD,
.len = 0,
},
@ -209,7 +209,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data)
.buf = out_buf,
},
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = I2C_M_RD | I2C_M_NOSTART,
.len = 2,
.buf = in_buf,
@ -226,7 +226,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data)
if (!priv->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from "
"%s:%02x.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
}
@ -238,7 +238,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, u16 data)
struct i2c_adapter *adapter = dvo->i2c_bus;
u8 out_buf[3];
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 3,
.buf = out_buf,
@ -253,13 +253,13 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, u16 data)
if (!priv->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
}
/* Probes the given bus and slave address for an ivch */
/* Probes the given bus and target address for an ivch */
static bool ivch_init(struct intel_dvo_device *dvo,
struct i2c_adapter *adapter)
{
@ -283,10 +283,10 @@ static bool ivch_init(struct intel_dvo_device *dvo,
* very unique, check that the value in the base address field matches
* the address it's responding on.
*/
if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->target_addr) {
DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
"(%d vs %d)\n",
(temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
(temp & VR00_BASE_ADDRESS_MASK), dvo->target_addr);
goto out;
}

18
drivers/gpu/drm/i915/display/dvo_ns2501.c
View File

@ -398,13 +398,13 @@ static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
struct i2c_msg msgs[] = {
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 1,
.buf = out_buf,
},
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = I2C_M_RD,
.len = 1,
.buf = in_buf,
@ -422,7 +422,7 @@ static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
if (!ns->quiet) {
DRM_DEBUG_KMS
("Unable to read register 0x%02x from %s:0x%02x.\n", addr,
adapter->name, dvo->slave_addr);
adapter->name, dvo->target_addr);
}
return false;
@ -441,7 +441,7 @@ static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
u8 out_buf[2];
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 2,
.buf = out_buf,
@ -456,7 +456,7 @@ static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
if (!ns->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
@ -487,8 +487,8 @@ static bool ns2501_init(struct intel_dvo_device *dvo,
goto out;
if (ch != (NS2501_VID & 0xff)) {
DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n",
ch, adapter->name, dvo->slave_addr);
DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n",
ch, adapter->name, dvo->target_addr);
goto out;
}
@ -496,8 +496,8 @@ static bool ns2501_init(struct intel_dvo_device *dvo,
goto out;
if (ch != (NS2501_DID & 0xff)) {
DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n",
ch, adapter->name, dvo->slave_addr);
DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n",
ch, adapter->name, dvo->target_addr);
goto out;
}
ns->quiet = false;

18
drivers/gpu/drm/i915/display/dvo_sil164.c
View File

@ -79,13 +79,13 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
struct i2c_msg msgs[] = {
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 1,
.buf = out_buf,
},
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = I2C_M_RD,
.len = 1,
.buf = in_buf,
@ -102,7 +102,7 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
if (!sil->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
}
@ -113,7 +113,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
struct i2c_adapter *adapter = dvo->i2c_bus;
u8 out_buf[2];
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 2,
.buf = out_buf,
@ -127,7 +127,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
if (!sil->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
@ -153,8 +153,8 @@ static bool sil164_init(struct intel_dvo_device *dvo,
goto out;
if (ch != (SIL164_VID & 0xff)) {
DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
ch, adapter->name, dvo->slave_addr);
DRM_DEBUG_KMS("sil164 not detected got %d: from %s Target %d.\n",
ch, adapter->name, dvo->target_addr);
goto out;
}
@ -162,8 +162,8 @@ static bool sil164_init(struct intel_dvo_device *dvo,
goto out;
if (ch != (SIL164_DID & 0xff)) {
DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
ch, adapter->name, dvo->slave_addr);
DRM_DEBUG_KMS("sil164 not detected got %d: from %s Target %d.\n",
ch, adapter->name, dvo->target_addr);
goto out;
}
sil->quiet = false;

18
drivers/gpu/drm/i915/display/dvo_tfp410.c
View File

@ -100,13 +100,13 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
struct i2c_msg msgs[] = {
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 1,
.buf = out_buf,
},
{
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = I2C_M_RD,
.len = 1,
.buf = in_buf,
@ -123,7 +123,7 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
if (!tfp->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
}
@ -134,7 +134,7 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
struct i2c_adapter *adapter = dvo->i2c_bus;
u8 out_buf[2];
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.addr = dvo->target_addr,
.flags = 0,
.len = 2,
.buf = out_buf,
@ -148,7 +148,7 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
if (!tfp->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, adapter->name, dvo->slave_addr);
addr, adapter->name, dvo->target_addr);
}
return false;
@ -183,15 +183,15 @@ static bool tfp410_init(struct intel_dvo_device *dvo,
if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
"Slave %d.\n",
id, adapter->name, dvo->slave_addr);
"Target %d.\n",
id, adapter->name, dvo->target_addr);
goto out;
}
if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
"Slave %d.\n",
id, adapter->name, dvo->slave_addr);
"Target %d.\n",
id, adapter->name, dvo->target_addr);
goto out;
}
tfp->quiet = false;

3
drivers/gpu/drm/i915/display/g4x_dp.c
View File

@ -1279,6 +1279,7 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
bool g4x_dp_init(struct drm_i915_private *dev_priv,
i915_reg_t output_reg, enum port port)
{
struct intel_display *display = &dev_priv->display;
const struct intel_bios_encoder_data *devdata;
struct intel_digital_port *dig_port;
struct intel_encoder *intel_encoder;
@ -1288,7 +1289,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
if (!assert_port_valid(dev_priv, port))
return false;
devdata = intel_bios_encoder_data_lookup(dev_priv, port);
devdata = intel_bios_encoder_data_lookup(display, port);
/* FIXME bail? */
if (!devdata)

3
drivers/gpu/drm/i915/display/g4x_hdmi.c
View File

@ -686,6 +686,7 @@ static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum port port
void g4x_hdmi_init(struct drm_i915_private *dev_priv,
i915_reg_t hdmi_reg, enum port port)
{
struct intel_display *display = &dev_priv->display;
const struct intel_bios_encoder_data *devdata;
struct intel_digital_port *dig_port;
struct intel_encoder *intel_encoder;
@ -697,7 +698,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
if (!assert_hdmi_port_valid(dev_priv, port))
return;
devdata = intel_bios_encoder_data_lookup(dev_priv, port);
devdata = intel_bios_encoder_data_lookup(display, port);
/* FIXME bail? */
if (!devdata)

2
drivers/gpu/drm/i915/display/i9xx_wm.c
View File

@ -4028,7 +4028,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.wm = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
if (!pnv_get_cxsr_latency(dev_priv)) {
drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
dev_priv->display.funcs.wm = &nop_funcs;

12
drivers/gpu/drm/i915/display/icl_dsi.c
View File

@ -27,6 +27,7 @@
#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fixed.h>
#include <drm/drm_mipi_dsi.h>
#include "i915_reg.h"
@ -330,7 +331,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp;
if (crtc_state->dsc.compression_enable)
bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@ -863,7 +864,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
@ -887,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable)
bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@ -1470,7 +1471,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
&pipe_config->hw.adjusted_mode;
if (pipe_config->dsc.compressed_bpp_x16) {
int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal =
@ -1944,6 +1945,7 @@ static void icl_dsi_add_properties(struct intel_connector *connector)
void icl_dsi_init(struct drm_i915_private *dev_priv,
const struct intel_bios_encoder_data *devdata)
{
struct intel_display *display = &dev_priv->display;
struct intel_dsi *intel_dsi;
struct intel_encoder *encoder;
struct intel_connector *intel_connector;
@ -2007,7 +2009,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
intel_dsi->panel_power_off_time = ktime_get_boottime();
intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL);
intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
mutex_lock(&dev_priv->drm.mode_config.mutex);
intel_panel_add_vbt_lfp_fixed_mode(intel_connector);

17
drivers/gpu/drm/i915/display/intel_acpi.c
View File

@ -183,9 +183,9 @@ void intel_unregister_dsm_handler(void)
{
}
void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915)
void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
acpi_handle dhandle;
union acpi_object *obj;
@ -263,15 +263,14 @@ static u32 acpi_display_type(struct intel_connector *connector)
return display_type;
}
void intel_acpi_device_id_update(struct drm_i915_private *dev_priv)
void intel_acpi_device_id_update(struct intel_display *display)
{
struct drm_device *drm_dev = &dev_priv->drm;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
u8 display_index[16] = {};
/* Populate the ACPI IDs for all connectors for a given drm_device */
drm_connector_list_iter_begin(drm_dev, &conn_iter);
drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
u32 device_id, type;
@ -288,10 +287,10 @@ void intel_acpi_device_id_update(struct drm_i915_private *dev_priv)
}
/* NOTE: The connector order must be final before this is called. */
void intel_acpi_assign_connector_fwnodes(struct drm_i915_private *i915)
void intel_acpi_assign_connector_fwnodes(struct intel_display *display)
{
struct drm_device *drm_dev = display->drm;
struct drm_connector_list_iter conn_iter;
struct drm_device *drm_dev = &i915->drm;
struct fwnode_handle *fwnode = NULL;
struct drm_connector *connector;
struct acpi_device *adev;
@ -333,7 +332,7 @@ void intel_acpi_assign_connector_fwnodes(struct drm_i915_private *i915)
fwnode_handle_put(fwnode);
}
void intel_acpi_video_register(struct drm_i915_private *i915)
void intel_acpi_video_register(struct intel_display *display)
{
struct drm_connector_list_iter conn_iter;
struct drm_connector *connector;
@ -347,7 +346,7 @@ void intel_acpi_video_register(struct drm_i915_private *i915)
* a native backlight later and acpi_video_register_backlight() should
* only be called after any native backlights have been registered.
*/
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
drm_connector_list_iter_begin(display->drm, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
struct intel_panel *panel = &to_intel_connector(connector)->panel;

18
drivers/gpu/drm/i915/display/intel_acpi.h
View File

@ -6,26 +6,26 @@
#ifndef __INTEL_ACPI_H__
#define __INTEL_ACPI_H__
struct drm_i915_private;
struct intel_display;
#ifdef CONFIG_ACPI
void intel_register_dsm_handler(void);
void intel_unregister_dsm_handler(void);
void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915);
void intel_acpi_device_id_update(struct drm_i915_private *i915);
void intel_acpi_assign_connector_fwnodes(struct drm_i915_private *i915);
void intel_acpi_video_register(struct drm_i915_private *i915);
void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display);
void intel_acpi_device_id_update(struct intel_display *display);
void intel_acpi_assign_connector_fwnodes(struct intel_display *display);
void intel_acpi_video_register(struct intel_display *display);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
static inline
void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915) { return; }
void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) { return; }
static inline
void intel_acpi_device_id_update(struct drm_i915_private *i915) { return; }
void intel_acpi_device_id_update(struct intel_display *display) { return; }
static inline
void intel_acpi_assign_connector_fwnodes(struct drm_i915_private *i915) { return; }
void intel_acpi_assign_connector_fwnodes(struct intel_display *display) { return; }
static inline
void intel_acpi_video_register(struct drm_i915_private *i915) { return; }
void intel_acpi_video_register(struct intel_display *display) { return; }
#endif /* CONFIG_ACPI */
#endif /* __INTEL_ACPI_H__ */

2
drivers/gpu/drm/i915/display/intel_alpm.c
View File

@ -280,7 +280,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
if (DISPLAY_VER(i915) < 20)
return;
if (!intel_dp_as_sdp_supported(intel_dp))
if (!intel_dp->as_sdp_supported)
return;
if (crtc_state->has_psr)

5
drivers/gpu/drm/i915/display/intel_audio.c
View File

@ -26,6 +26,7 @@
#include <drm/drm_edid.h>
#include <drm/drm_eld.h>
#include <drm/drm_fixed.h>
#include <drm/intel/i915_component.h>
#include "i915_drv.h"
@ -452,8 +453,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
lanes = crtc_state->lane_count;
drm_dbg_kms(&i915->drm,
"h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n",
h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk);
"h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n",
h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk);
if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
return 0;

15
drivers/gpu/drm/i915/display/intel_backlight.c
View File

@ -455,7 +455,7 @@ void intel_backlight_disable(const struct drm_connector_state *old_conn_state)
mutex_lock(&i915->display.backlight.lock);
if (panel->backlight.device)
panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
panel->backlight.device->props.power = BACKLIGHT_POWER_OFF;
panel->backlight.enabled = false;
panel->backlight.funcs->disable(old_conn_state, 0);
@ -773,7 +773,7 @@ static void __intel_backlight_enable(const struct intel_crtc_state *crtc_state,
panel->backlight.funcs->enable(crtc_state, conn_state, panel->backlight.level);
panel->backlight.enabled = true;
if (panel->backlight.device)
panel->backlight.device->props.power = FB_BLANK_UNBLANK;
panel->backlight.device->props.power = BACKLIGHT_POWER_ON;
}
void intel_backlight_enable(const struct intel_crtc_state *crtc_state,
@ -870,12 +870,12 @@ static int intel_backlight_device_update_status(struct backlight_device *bd)
*/
if (panel->backlight.enabled) {
if (panel->backlight.power) {
bool enable = bd->props.power == FB_BLANK_UNBLANK &&
bool enable = bd->props.power == BACKLIGHT_POWER_ON &&
bd->props.brightness != 0;
panel->backlight.power(connector, enable);
}
} else {
bd->props.power = FB_BLANK_POWERDOWN;
bd->props.power = BACKLIGHT_POWER_OFF;
}
drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
@ -945,9 +945,9 @@ int intel_backlight_device_register(struct intel_connector *connector)
props.max_brightness);
if (panel->backlight.enabled)
props.power = FB_BLANK_UNBLANK;
props.power = BACKLIGHT_POWER_ON;
else
props.power = FB_BLANK_POWERDOWN;
props.power = BACKLIGHT_POWER_OFF;
name = kstrdup_const("intel_backlight", GFP_KERNEL);
if (!name)
@ -1449,6 +1449,9 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
static int cnp_num_backlight_controllers(struct drm_i915_private *i915)
{
if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
return 2;
if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
return 1;

881
drivers/gpu/drm/i915/display/intel_bios.c
View File

File diff suppressed because it is too large Load Diff

28
drivers/gpu/drm/i915/display/intel_bios.h
View File

@ -33,9 +33,9 @@
#include <linux/types.h>
struct drm_edid;
struct drm_i915_private;
struct intel_bios_encoder_data;
struct intel_crtc_state;
struct intel_display;
struct intel_encoder;
struct intel_panel;
enum aux_ch;
@ -232,28 +232,28 @@ struct mipi_pps_data {
u16 panel_power_cycle_delay;
} __packed;
void intel_bios_init(struct drm_i915_private *dev_priv);
void intel_bios_init_panel_early(struct drm_i915_private *dev_priv,
void intel_bios_init(struct intel_display *display);
void intel_bios_init_panel_early(struct intel_display *display,
struct intel_panel *panel,
const struct intel_bios_encoder_data *devdata);
void intel_bios_init_panel_late(struct drm_i915_private *dev_priv,
void intel_bios_init_panel_late(struct intel_display *display,
struct intel_panel *panel,
const struct intel_bios_encoder_data *devdata,
const struct drm_edid *drm_edid);
void intel_bios_fini_panel(struct intel_panel *panel);
void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
bool intel_bios_is_valid_vbt(struct drm_i915_private *i915,
void intel_bios_driver_remove(struct intel_display *display);
bool intel_bios_is_valid_vbt(struct intel_display *display,
const void *buf, size_t size);
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
bool intel_bios_is_tv_present(struct intel_display *display);
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin);
bool intel_bios_is_port_present(struct intel_display *display, enum port port);
bool intel_bios_is_dsi_present(struct intel_display *display, enum port *port);
bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
int dsc_max_bpc);
const struct intel_bios_encoder_data *
intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port);
intel_bios_encoder_data_lookup(struct intel_display *display, enum port port);
bool intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata);
bool intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata);
@ -277,10 +277,10 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata);
int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata);
int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata);
void intel_bios_for_each_encoder(struct drm_i915_private *i915,
void (*func)(struct drm_i915_private *i915,
void intel_bios_for_each_encoder(struct intel_display *display,
void (*func)(struct intel_display *display,
const struct intel_bios_encoder_data *devdata));
void intel_bios_debugfs_register(struct drm_i915_private *i915);
void intel_bios_debugfs_register(struct intel_display *display);
#endif /* _INTEL_BIOS_H_ */

5
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@ -23,7 +23,10 @@
#include <linux/time.h>
#include <drm/drm_fixed.h>
#include "soc/intel_dram.h"
#include "hsw_ips.h"
#include "i915_reg.h"
#include "intel_atomic.h"
@ -2750,7 +2753,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
*/
int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
int min_cdclk_bj =
(to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
pixel_clock) / (2 * bigjoiner_interface_bits);
min_cdclk = max(min_cdclk, min_cdclk_bj);

8
drivers/gpu/drm/i915/display/intel_combo_phy.c
View File

@ -159,9 +159,11 @@ static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
{
bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
struct intel_display *display = &i915->display;
bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);
bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);
bool dsi_present = intel_bios_is_dsi_present(display, NULL);
/*
* VBT's 'dvo port' field for child devices references the DDI, not

3
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
View File

@ -10,6 +10,7 @@
#include "intel_crtc_state_dump.h"
#include "intel_display_types.h"
#include "intel_hdmi.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
static void intel_dump_crtc_timings(struct drm_printer *p,
@ -369,6 +370,8 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
else if (IS_VALLEYVIEW(i915))
vlv_dump_csc(&p, "wgc csc", &pipe_config->csc);
intel_vdsc_state_dump(&p, 0, pipe_config);
dump_planes:
if (!state)
return;

8
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -4172,7 +4172,8 @@ static void intel_ddi_sync_state(struct intel_encoder *encoder,
intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
crtc_state);
if (intel_encoder_is_dp(encoder))
if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) ||
(!crtc_state && intel_encoder_is_dp(encoder)))
intel_dp_sync_state(encoder, crtc_state);
}
@ -4853,9 +4854,10 @@ static bool port_in_use(struct drm_i915_private *i915, enum port port)
return false;
}
void intel_ddi_init(struct drm_i915_private *dev_priv,
void intel_ddi_init(struct intel_display *display,
const struct intel_bios_encoder_data *devdata)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_digital_port *dig_port;
struct intel_encoder *encoder;
bool init_hdmi, init_dp;
@ -4972,7 +4974,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
} else {
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
DRM_MODE_ENCODER_TMDS,
"DDI %c/PHY %c", port_name(port), phy_name(phy));
"DDI %c/PHY %c", port_name(port), phy_name(phy));
}
intel_encoder_link_check_init(encoder, intel_ddi_link_check);

3
drivers/gpu/drm/i915/display/intel_ddi.h
View File

@ -15,6 +15,7 @@ struct intel_bios_encoder_data;
struct intel_connector;
struct intel_crtc;
struct intel_crtc_state;
struct intel_display;
struct intel_dp;
struct intel_dpll_hw_state;
struct intel_encoder;
@ -53,7 +54,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
enum port port);
void intel_ddi_init(struct drm_i915_private *dev_priv,
void intel_ddi_init(struct intel_display *display,
const struct intel_bios_encoder_data *devdata);
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,

44
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -39,6 +39,7 @@
#include <drm/drm_atomic_uapi.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fixed.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_rect.h>
@ -1014,9 +1015,14 @@ static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
}
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!new_crtc_state->hw.active)
return false;
@ -1026,9 +1032,14 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
if (!old_crtc_state->hw.active)
return false;
@ -1181,7 +1192,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
if (vrr_disabling(old_crtc_state, new_crtc_state)) {
if (intel_crtc_vrr_disabling(state, crtc)) {
intel_vrr_disable(old_crtc_state);
intel_crtc_update_active_timings(old_crtc_state, false);
}
@ -4669,11 +4680,11 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
"[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
crtc->base.base.id, crtc->base.name,
BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
crtc_state->bw_constrained = true;
}
@ -5100,7 +5111,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (current_config->name != pipe_config->name) { \
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
__stringify(name) " is not bool"); \
pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
"(expected %s, found %s)", \
str_yes_no(current_config->name), \
str_yes_no(pipe_config->name)); \
@ -6830,8 +6841,6 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@ -6844,7 +6853,7 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
!intel_crtc_needs_modeset(new_crtc_state))
skl_detach_scalers(new_crtc_state);
if (vrr_enabling(old_crtc_state, new_crtc_state))
if (intel_crtc_vrr_enabling(state, crtc))
intel_vrr_enable(new_crtc_state);
}
@ -6944,7 +6953,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
*
* FIXME Should be synchronized with the start of vblank somehow...
*/
if (vrr_enabling(old_crtc_state, new_crtc_state) ||
if (intel_crtc_vrr_enabling(state, crtc) ||
new_crtc_state->update_m_n || new_crtc_state->update_lrr)
intel_crtc_update_active_timings(new_crtc_state,
new_crtc_state->vrr.enable);
@ -7777,6 +7786,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port)
void intel_setup_outputs(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct intel_encoder *encoder;
bool dpd_is_edp = false;
@ -7789,7 +7799,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (intel_ddi_crt_present(dev_priv))
intel_crt_init(dev_priv);
intel_bios_for_each_encoder(dev_priv, intel_ddi_init);
intel_bios_for_each_encoder(display, intel_ddi_init);
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
vlv_dsi_init(dev_priv);
@ -7851,14 +7861,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
* HDMI ports that the VBT claim are DP or eDP.
*/
has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
has_port = intel_bios_is_port_present(dev_priv, PORT_B);
has_port = intel_bios_is_port_present(display, PORT_B);
if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
has_port = intel_bios_is_port_present(dev_priv, PORT_C);
has_port = intel_bios_is_port_present(display, PORT_C);
if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
@ -7869,7 +7879,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
* eDP not supported on port D,
* so no need to worry about it
*/
has_port = intel_bios_is_port_present(dev_priv, PORT_D);
has_port = intel_bios_is_port_present(display, PORT_D);
if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)

2
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@ -237,7 +237,7 @@ struct intel_vbt_data {
struct sdvo_device_mapping {
u8 initialized;
u8 dvo_port;
u8 slave_addr;
u8 target_addr;
u8 dvo_wiring;
u8 i2c_pin;
u8 ddc_pin;

15
drivers/gpu/drm/i915/display/intel_display_debugfs.c
View File

@ -36,6 +36,7 @@
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_vdsc.h"
#include "intel_wm.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
@ -492,7 +493,7 @@ static void crtc_updates_info(struct seq_file *m,
seq_printf(m, "%sMax update: %lluns\n",
hdr, crtc->debug.vbl.max);
seq_printf(m, "%sAverage update: %lluns\n",
hdr, div64_u64(crtc->debug.vbl.sum, count));
hdr, div64_u64(crtc->debug.vbl.sum, count));
seq_printf(m, "%sOverruns > %uus: %u\n",
hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over);
}
@ -551,6 +552,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_encoder *encoder;
@ -581,6 +583,8 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
crtc_state->joiner_pipes,
intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master");
intel_vdsc_state_dump(&p, 1, crtc_state);
for_each_intel_encoder_mask(&dev_priv->drm, encoder,
crtc_state->uapi.encoder_mask)
intel_encoder_info(m, crtc, encoder);
@ -1008,7 +1012,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
return ret;
}
intel_fbc_reset_underrun(dev_priv);
intel_fbc_reset_underrun(&dev_priv->display);
return cnt;
}
@ -1045,6 +1049,7 @@ static const struct {
void intel_display_debugfs_register(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
struct drm_minor *minor = i915->drm.primary;
int i;
@ -1060,12 +1065,12 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
ARRAY_SIZE(intel_display_debugfs_list),
minor->debugfs_root, minor);
intel_bios_debugfs_register(i915);
intel_bios_debugfs_register(display);
intel_cdclk_debugfs_register(i915);
intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(i915);
intel_fbc_debugfs_register(display);
intel_hpd_debugfs_register(i915);
intel_opregion_debugfs_register(i915);
intel_opregion_debugfs_register(display);
intel_psr_debugfs_register(i915);
intel_wm_debugfs_register(i915);
intel_display_debugfs_params(i915);

10
drivers/gpu/drm/i915/display/intel_display_device.c
View File

@ -1529,9 +1529,11 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf
*/
bool intel_display_device_enabled(struct drm_i915_private *i915)
{
/* Only valid when HAS_DISPLAY() is true */
drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915));
struct intel_display *display = &i915->display;
return !i915->display.params.disable_display &&
!intel_opregion_headless_sku(i915);
/* Only valid when HAS_DISPLAY() is true */
drm_WARN_ON(display->drm, !HAS_DISPLAY(display));
return !display->params.disable_display &&
!intel_opregion_headless_sku(display);
}

26
drivers/gpu/drm/i915/display/intel_display_driver.c
View File

@ -217,7 +217,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
return ret;
}
intel_bios_init(i915);
intel_bios_init(display);
ret = intel_vga_register(i915);
if (ret)
@ -265,7 +265,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
intel_init_quirks(display);
intel_fbc_init(i915);
intel_fbc_init(display);
return 0;
@ -275,7 +275,7 @@ cleanup_vga_client_pw_domain_dmc:
cleanup_vga:
intel_vga_unregister(i915);
cleanup_bios:
intel_bios_driver_remove(i915);
intel_bios_driver_remove(display);
return ret;
}
@ -416,7 +416,8 @@ bool intel_display_driver_check_access(struct drm_i915_private *i915)
/* part #2: call after irq install, but before gem init */
int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
{
struct drm_device *dev = &i915->drm;
struct intel_display *display = &i915->display;
struct drm_device *dev = display->drm;
enum pipe pipe;
int ret;
@ -466,7 +467,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
drm_modeset_lock_all(dev);
intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
intel_acpi_assign_connector_fwnodes(i915);
intel_acpi_assign_connector_fwnodes(display);
drm_modeset_unlock_all(dev);
intel_initial_plane_config(i915);
@ -526,6 +527,7 @@ int intel_display_driver_probe(struct drm_i915_private *i915)
void intel_display_driver_register(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
struct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS,
"i915 display info:");
@ -533,8 +535,8 @@ void intel_display_driver_register(struct drm_i915_private *i915)
return;
/* Must be done after probing outputs */
intel_opregion_register(i915);
intel_acpi_video_register(i915);
intel_opregion_register(display);
intel_acpi_video_register(display);
intel_audio_init(i915);
@ -607,23 +609,27 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
destroy_workqueue(i915->display.wq.flip);
destroy_workqueue(i915->display.wq.modeset);
intel_fbc_cleanup(i915);
intel_fbc_cleanup(&i915->display);
}
/* part #3: call after gem init */
void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
intel_dmc_fini(i915);
intel_power_domains_driver_remove(i915);
intel_vga_unregister(i915);
intel_bios_driver_remove(i915);
intel_bios_driver_remove(display);
}
void intel_display_driver_unregister(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
if (!HAS_DISPLAY(i915))
return;
@ -643,7 +649,7 @@ void intel_display_driver_unregister(struct drm_i915_private *i915)
drm_atomic_helper_shutdown(&i915->drm);
acpi_video_unregister();
intel_opregion_unregister(i915);
intel_opregion_unregister(display);
}
/*

36
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@ -270,10 +270,12 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
static bool i915_has_asle(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
if (!IS_PINEVIEW(i915) && !IS_MOBILE(i915))
return false;
return intel_opregion_asle_present(i915);
return intel_opregion_asle_present(display);
}
/**
@ -497,6 +499,8 @@ void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
struct intel_display *display = &dev_priv->display;
bool blc_event = false;
enum pipe pipe;
@ -515,12 +519,13 @@ void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
}
if (blc_event || (iir & I915_ASLE_INTERRUPT))
intel_opregion_asle_intr(dev_priv);
intel_opregion_asle_intr(display);
}
void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
u32 iir, u32 pipe_stats[I915_MAX_PIPES])
{
struct intel_display *display = &dev_priv->display;
bool blc_event = false;
enum pipe pipe;
@ -539,7 +544,7 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
}
if (blc_event || (iir & I915_ASLE_INTERRUPT))
intel_opregion_asle_intr(dev_priv);
intel_opregion_asle_intr(display);
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
intel_gmbus_irq_handler(dev_priv);
@ -695,6 +700,7 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
{
struct intel_display *display = &dev_priv->display;
enum pipe pipe;
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
@ -705,7 +711,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
intel_dp_aux_irq_handler(dev_priv);
if (de_iir & DE_GSE)
intel_opregion_asle_intr(dev_priv);
intel_opregion_asle_intr(display);
if (de_iir & DE_POISON)
drm_err(&dev_priv->drm, "Poison interrupt\n");
@ -743,6 +749,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
{
struct intel_display *display = &dev_priv->display;
enum pipe pipe;
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
@ -770,7 +777,7 @@ void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
intel_dp_aux_irq_handler(dev_priv);
if (de_iir & DE_GSE_IVB)
intel_opregion_asle_intr(dev_priv);
intel_opregion_asle_intr(display);
for_each_pipe(dev_priv, pipe) {
if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
@ -894,6 +901,7 @@ static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
static void
gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
struct intel_display *display = &dev_priv->display;
bool found = false;
if (DISPLAY_VER(dev_priv) >= 14) {
@ -906,8 +914,15 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
intel_pmdemand_irq_handler(dev_priv);
found = true;
}
if (iir & XELPDP_RM_TIMEOUT) {
u32 val = intel_uncore_read(&dev_priv->uncore,
RM_TIMEOUT_REG_CAPTURE);
drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val);
found = true;
}
} else if (iir & GEN8_DE_MISC_GSE) {
intel_opregion_asle_intr(dev_priv);
intel_opregion_asle_intr(display);
found = true;
}
@ -1211,8 +1226,10 @@ u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
{
struct intel_display *display = &i915->display;
if (iir & GEN11_GU_MISC_GSE)
intel_opregion_asle_intr(i915);
intel_opregion_asle_intr(display);
}
void gen11_display_irq_handler(struct drm_i915_private *i915)
@ -1680,6 +1697,7 @@ static void icp_irq_postinstall(struct drm_i915_private *i915);
void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
@ -1710,11 +1728,11 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 14) {
de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
XELPDP_PMDEMAND_RSP;
XELPDP_PMDEMAND_RSP | XELPDP_RM_TIMEOUT;
} else if (DISPLAY_VER(dev_priv) >= 11) {
enum port port;
if (intel_bios_is_dsi_present(dev_priv, &port))
if (intel_bios_is_dsi_present(display, &port))
de_port_masked |= DSI0_TE | DSI1_TE;
}

8
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -1704,6 +1704,14 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
/* Wa_14011503030:xelpd */
if (DISPLAY_VER(dev_priv) == 13)
intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
/* Wa_15013987218 */
if (DISPLAY_VER(dev_priv) == 20) {
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE);
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0);
}
}
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)

45
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1754,6 +1754,7 @@ struct intel_dp {
u8 lane_count;
u8 sink_count;
bool link_trained;
bool needs_modeset_retry;
bool use_max_params;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
@ -1777,10 +1778,30 @@ struct intel_dp {
int common_rates[DP_MAX_SUPPORTED_RATES];
struct {
/* TODO: move the rest of link specific fields to here */
/* common rate,lane_count configs in bw order */
int num_configs;
#define INTEL_DP_MAX_LANE_COUNT 4
#define INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS (ilog2(INTEL_DP_MAX_LANE_COUNT) + 1)
#define INTEL_DP_LANE_COUNT_EXP_BITS order_base_2(INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
#define INTEL_DP_LINK_RATE_IDX_BITS (BITS_PER_TYPE(u8) - INTEL_DP_LANE_COUNT_EXP_BITS)
#define INTEL_DP_MAX_LINK_CONFIGS (DP_MAX_SUPPORTED_RATES * \
INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS)
struct intel_dp_link_config {
u8 link_rate_idx:INTEL_DP_LINK_RATE_IDX_BITS;
u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS;
} configs[INTEL_DP_MAX_LINK_CONFIGS];
/* Max lane count for the current link */
int max_lane_count;
/* Max rate for the current link */
int max_rate;
/*
* Link parameters for which the MST topology was probed.
* Tracking these ensures that the MST path resources are
* re-enumerated whenever the link is retrained with new link
* parameters, as required by the DP standard.
*/
int mst_probed_lane_count;
int mst_probed_rate;
int force_lane_count;
int force_rate;
bool retrain_disabled;
@ -1806,6 +1827,7 @@ struct intel_dp {
/* connector directly attached - won't be use for modeset in mst world */
struct intel_connector *attached_connector;
bool as_sdp_supported;
struct drm_dp_tunnel *tunnel;
bool tunnel_suspended:1;
@ -2178,29 +2200,6 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
static inline int to_bpp_int(int bpp_x16)
{
return bpp_x16 >> 4;
}
static inline int to_bpp_frac(int bpp_x16)
{
return bpp_x16 & 0xf;
}
#define BPP_X16_FMT "%d.%04d"
#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
static inline int to_bpp_int_roundup(int bpp_x16)
{
return (bpp_x16 + 0xf) >> 4;
}
static inline int to_bpp_x16(int bpp)
{
return bpp << 4;
}
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.

286
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -29,6 +29,7 @@
#include <linux/i2c.h>
#include <linux/notifier.h>
#include <linux/slab.h>
#include <linux/sort.h>
#include <linux/string_helpers.h>
#include <linux/timekeeping.h>
#include <linux/types.h>
@ -42,6 +43,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_fixed.h>
#include <drm/drm_probe_helper.h>
#include "g4x_dp.h"
@ -129,14 +131,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
}
bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
return HAS_AS_SDP(i915) &&
drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
@ -642,6 +636,106 @@ int intel_dp_rate_index(const int *rates, int len, int rate)
return -1;
}
static int intel_dp_link_config_rate(struct intel_dp *intel_dp,
const struct intel_dp_link_config *lc)
{
return intel_dp_common_rate(intel_dp, lc->link_rate_idx);
}
static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)
{
return 1 << lc->lane_count_exp;
}
static int intel_dp_link_config_bw(struct intel_dp *intel_dp,
const struct intel_dp_link_config *lc)
{
return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),
intel_dp_link_config_lane_count(lc));
}
static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
{
struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */
const struct intel_dp_link_config *lc_a = a;
const struct intel_dp_link_config *lc_b = b;
int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);
int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);
if (bw_a != bw_b)
return bw_a - bw_b;
return intel_dp_link_config_rate(intel_dp, lc_a) -
intel_dp_link_config_rate(intel_dp, lc_b);
}
static void intel_dp_link_config_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_dp_link_config *lc;
int num_common_lane_configs;
int i;
int j;
if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
return;
num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs >
ARRAY_SIZE(intel_dp->link.configs)))
return;
intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;
lc = &intel_dp->link.configs[0];
for (i = 0; i < intel_dp->num_common_rates; i++) {
for (j = 0; j < num_common_lane_configs; j++) {
lc->lane_count_exp = j;
lc->link_rate_idx = i;
lc++;
}
}
sort_r(intel_dp->link.configs, intel_dp->link.num_configs,
sizeof(intel_dp->link.configs[0]),
link_config_cmp_by_bw, NULL,
intel_dp);
}
void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
const struct intel_dp_link_config *lc;
if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs))
idx = 0;
lc = &intel_dp->link.configs[idx];
*link_rate = intel_dp_link_config_rate(intel_dp, lc);
*lane_count = intel_dp_link_config_lane_count(lc);
}
int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)
{
int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,
link_rate);
int lane_count_exp = ilog2(lane_count);
int i;
for (i = 0; i < intel_dp->link.num_configs; i++) {
const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];
if (lc->lane_count_exp == lane_count_exp &&
lc->link_rate_idx == link_rate_idx)
return i;
}
return -1;
}
static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@ -660,6 +754,8 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
intel_dp->common_rates[0] = 162000;
intel_dp->num_common_rates = 1;
}
intel_dp_link_config_init(intel_dp);
}
static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
@ -1598,8 +1694,8 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
int mode_rate, link_rate, link_avail;
for (bpp = to_bpp_int(limits->link.max_bpp_x16);
bpp >= to_bpp_int(limits->link.min_bpp_x16);
for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);
bpp -= 2 * 3) {
int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
@ -1927,7 +2023,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
timeslots);
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 =
to_bpp_x16(valid_dsc_bpp[i]);
fxp_q4_from_int(valid_dsc_bpp[i]);
return 0;
}
}
@ -1970,7 +2066,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
compressed_bppx16 >= dsc_min_bpp;
compressed_bppx16 -= bppx16_step) {
if (intel_dp->force_dsc_fractional_bpp_en &&
!to_bpp_frac(compressed_bppx16))
!fxp_q4_to_frac(compressed_bppx16))
continue;
ret = dsc_compute_link_config(intel_dp,
pipe_config,
@ -1980,7 +2076,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
if (intel_dp->force_dsc_fractional_bpp_en &&
to_bpp_frac(compressed_bppx16))
fxp_q4_to_frac(compressed_bppx16))
drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
return 0;
@ -2005,7 +2101,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
@ -2017,7 +2113,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
adjusted_mode->hdisplay,
pipe_config->joiner_pipes);
dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
if (DISPLAY_VER(i915) >= 13)
return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
@ -2167,20 +2263,20 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
pipe_config,
pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
/* Compressed BPP should be less than the Input DSC bpp */
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
pipe_config->dsc.compressed_bpp_x16 =
to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
pipe_config->pipe_bpp = pipe_bpp;
@ -2270,17 +2366,17 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp = %d"
"Compressed BPP = " BPP_X16_FMT "\n",
"Compressed BPP = " FXP_Q4_FMT "\n",
pipe_config->pipe_bpp,
BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
return ret;
}
pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
"Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
"Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
pipe_config->pipe_bpp,
BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
pipe_config->dsc.slice_count);
return 0;
@ -2312,15 +2408,15 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
int max_link_bpp_x16;
max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
to_bpp_x16(limits->pipe.max_bpp));
fxp_q4_from_int(limits->pipe.max_bpp));
if (!dsc) {
max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))
return false;
limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
} else {
/*
* TODO: set the DSC link limits already here, atm these are
@ -2333,7 +2429,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
limits->link.max_bpp_x16 = max_link_bpp_x16;
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
encoder->base.base.id, encoder->base.name,
crtc->base.base.id, crtc->base.name,
adjusted_mode->crtc_clock,
@ -2341,7 +2437,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
limits->max_lane_count,
limits->max_rate,
limits->pipe.max_bpp,
BPP_X16_ARGS(limits->link.max_bpp_x16));
FXP_Q4_ARGS(limits->link.max_bpp_x16));
return true;
}
@ -2393,7 +2489,7 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int bpp = crtc_state->dsc.compression_enable ?
to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
crtc_state->pipe_bpp;
return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
@ -2472,10 +2568,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
}
drm_dbg_kms(&i915->drm,
"DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n",
"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp,
BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
intel_dp_config_required_rate(pipe_config),
intel_dp_max_link_data_rate(intel_dp,
pipe_config->port_clock,
@ -2625,8 +2721,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
if (!crtc_state->vrr.enable ||
!intel_dp_as_sdp_supported(intel_dp))
if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
return;
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
@ -2875,7 +2970,6 @@ static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
drm_connector_put(&connector->base);
}
/* NOTE: @state is only valid for MST links and can be %NULL for SST. */
void
intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
struct intel_encoder *encoder,
@ -2884,18 +2978,19 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
struct intel_connector *connector;
struct intel_digital_connector_state *conn_state;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i;
if (intel_dp->needs_modeset_retry)
return;
intel_dp->needs_modeset_retry = true;
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
return;
}
if (drm_WARN_ON(&i915->drm, !state))
return;
for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
if (!conn_state->base.crtc)
continue;
@ -2967,8 +3062,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable)
link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
else
link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp));
link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp));
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
@ -3023,6 +3118,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
{
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp->link_trained = false;
intel_dp->needs_modeset_retry = false;
intel_dp->link_rate = link_rate;
intel_dp->lane_count = lane_count;
}
@ -3031,6 +3127,8 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
{
intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->link.mst_probed_lane_count = 0;
intel_dp->link.mst_probed_rate = 0;
intel_dp->link.retrain_disabled = false;
intel_dp->link.seq_train_failures = 0;
}
@ -3366,8 +3464,11 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
if (crtc_state)
if (crtc_state) {
intel_dp_reset_link_params(intel_dp);
intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
intel_dp->link_trained = true;
}
}
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
@ -3434,7 +3535,7 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
{
int bw_gbps[] = {9, 18, 24, 32, 40, 48};
static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};
int i;
for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
@ -4154,6 +4255,9 @@ intel_dp_mst_configure(struct intel_dp *intel_dp)
intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
if (intel_dp->is_mst)
intel_dp_mst_prepare_probe(intel_dp);
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
/* Avoid stale info on the next detect cycle. */
@ -4383,8 +4487,11 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
if (!enable && HAS_DSC(dev_priv))
val &= ~VDIP_ENABLE_PPS;
/* When PSR is enabled, this routine doesn't disable VSC DIP */
if (!crtc_state->has_psr)
/*
* This routine disables VSC DIP if the function is called
* to disable SDP or if it does not have PSR
*/
if (!enable || !crtc_state->has_psr)
val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
intel_de_write(dev_priv, reg, val);
@ -5251,8 +5358,6 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_crtc *crtc;
bool mst_output = false;
u8 pipe_mask;
int ret;
@ -5281,78 +5386,28 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder,
encoder->base.base.id, encoder->base.name,
str_yes_no(intel_dp->link.force_retrain));
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
if (ret == -EDEADLK)
return ret;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
mst_output = true;
break;
}
intel_dp->link.force_retrain = false;
/* Suppress underruns caused by re-training */
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
if (crtc_state->has_pch_encoder)
intel_set_pch_fifo_underrun_reporting(dev_priv,
intel_crtc_pch_transcoder(crtc), false);
}
/* TODO: use a modeset for SST as well. */
if (mst_output) {
ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
if (ret && ret != -EDEADLK)
drm_dbg_kms(&dev_priv->drm,
"[ENCODER:%d:%s] link retraining failed: %pe\n",
encoder->base.base.id, encoder->base.name,
ERR_PTR(ret));
goto out;
}
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
intel_dp->link_trained = false;
intel_dp_check_frl_training(intel_dp);
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
intel_dp_start_link_train(NULL, intel_dp, crtc_state);
intel_dp_stop_link_train(intel_dp, crtc_state);
break;
}
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
/* Keep underrun reporting disabled until things are stable */
intel_crtc_wait_for_next_vblank(crtc);
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
if (crtc_state->has_pch_encoder)
intel_set_pch_fifo_underrun_reporting(dev_priv,
intel_crtc_pch_transcoder(crtc), true);
}
out:
if (ret != -EDEADLK)
intel_dp->link.force_retrain = false;
if (ret)
drm_dbg_kms(&dev_priv->drm,
"[ENCODER:%d:%s] link retraining failed: %pe\n",
encoder->base.base.id, encoder->base.name,
ERR_PTR(ret));
return ret;
}
void intel_dp_link_check(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_modeset_acquire_ctx ctx;
int ret;
intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
ret = intel_dp_retrain_link(encoder, &ctx);
drm_WARN_ON(&i915->drm, ret);
}
void intel_dp_check_link_state(struct intel_dp *intel_dp)
@ -5902,6 +5957,15 @@ intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *conn
connector);
}
static void
intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&
drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
}
static int
intel_dp_detect(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx,
@ -5960,13 +6024,15 @@ intel_dp_detect(struct drm_connector *connector,
intel_dp_detect_dsc_caps(intel_dp, intel_connector);
intel_dp_mst_configure(intel_dp);
intel_dp_detect_sdp_caps(intel_dp);
if (intel_dp->reset_link_params) {
intel_dp_reset_link_params(intel_dp);
intel_dp->reset_link_params = false;
}
intel_dp_mst_configure(intel_dp);
intel_dp_print_rates(intel_dp);
if (intel_dp->is_mst) {
@ -6437,8 +6503,9 @@ static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
{
struct intel_display *display = &i915->display;
const struct intel_bios_encoder_data *devdata =
intel_bios_encoder_data_lookup(i915, port);
intel_bios_encoder_data_lookup(display, port);
return _intel_dp_is_port_edp(i915, devdata, port);
}
@ -6541,6 +6608,7 @@ static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector)
{
struct intel_display *display = to_intel_display(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct drm_connector *connector = &intel_connector->base;
struct drm_display_mode *fixed_mode;
@ -6566,7 +6634,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
return false;
}
intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
intel_bios_init_panel_early(display, &intel_connector->panel,
encoder->devdata);
if (!intel_pps_init(intel_dp)) {
@ -6663,7 +6731,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
drm_edid = ERR_PTR(-ENOENT);
}
intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata,
IS_ERR(drm_edid) ? NULL : drm_edid);
intel_panel_add_edid_fixed_modes(intel_connector, true);

3
drivers/gpu/drm/i915/display/intel_dp.h
View File

@ -85,7 +85,6 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state);
bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
bool intel_dp_is_edp(struct intel_dp *intel_dp);
bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp);
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
bool intel_dp_has_dsc(const struct intel_connector *connector);
int intel_dp_link_symbol_size(int rate);
@ -108,6 +107,8 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp);
int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
int intel_dp_common_rate(struct intel_dp *intel_dp, int index);
int intel_dp_rate_index(const int *rates, int len, int rate);
int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
void intel_dp_reset_link_params(struct intel_dp *intel_dp);

13
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
View File

@ -150,7 +150,7 @@ int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
ssize_t ret;
u8 bcaps;
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
if (ret)
return ret;
@ -675,8 +675,15 @@ static
int intel_dp_hdcp2_get_capability(struct intel_connector *connector,
bool *capable)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_dp_aux *aux = &dig_port->dp.aux;
struct intel_digital_port *dig_port;
struct drm_dp_aux *aux;
*capable = false;
if (!intel_attached_encoder(connector))
return -EINVAL;
dig_port = intel_attached_dig_port(connector);
aux = &dig_port->dp.aux;
return _intel_dp_hdcp2_get_capability(aux, capable);
}

132
drivers/gpu/drm/i915/display/intel_dp_link_training.c
View File

@ -21,6 +21,8 @@
* IN THE SOFTWARE.
*/
#include <drm/display/drm_dp_helper.h>
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_dp.h"
@ -114,7 +116,13 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1)
return false;
intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val;
return true;
}
static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)
@ -174,7 +182,7 @@ static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_
* still taking into account any LTTPR common lane- rate/count limits.
*/
if (lttpr_count < 0)
return 0;
goto out_reset_lttpr_count;
if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
lt_dbg(intel_dp, DP_PHY_DPRX,
@ -697,26 +705,28 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
return true;
}
static void
intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
{
u8 link_config[2];
link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
link_config[1] = intel_dp_is_uhbr(crtc_state) ?
link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
}
static void
intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
u8 link_bw, u8 rate_select)
static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
u8 lane_count = crtc_state->lane_count;
intel_dp_link_training_set_mode(intel_dp,
crtc_state->port_clock, crtc_state->vrr.flipline);
}
if (crtc_state->enhanced_framing)
void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
int link_bw, int rate_select, int lane_count,
bool enhanced_framing)
{
if (enhanced_framing)
lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
if (link_bw) {
@ -740,6 +750,14 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
}
}
static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
u8 link_bw, u8 rate_select)
{
intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,
crtc_state->enhanced_framing);
}
/*
* Prepare link training by configuring the link parameters. On DDI platforms
* also enable the port here.
@ -1152,6 +1170,36 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
return true;
}
static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
int *new_link_rate, int *new_lane_count)
{
int link_rate;
int lane_count;
int i;
i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
for (i--; i >= 0; i--) {
intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count);
if ((intel_dp->link.force_rate &&
intel_dp->link.force_rate != link_rate) ||
(intel_dp->link.force_lane_count &&
intel_dp->link.force_lane_count != lane_count))
continue;
break;
}
if (i < 0)
return false;
*new_link_rate = link_rate;
*new_lane_count = lane_count;
return true;
}
static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)
{
int rate_index;
@ -1187,6 +1235,41 @@ static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)
return current_lane_count >> 1;
}
static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
int *new_link_rate, int *new_lane_count)
{
int link_rate;
int lane_count;
lane_count = crtc_state->lane_count;
link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
if (link_rate < 0) {
lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);
link_rate = intel_dp_max_common_rate(intel_dp);
}
if (lane_count < 0)
return false;
*new_link_rate = link_rate;
*new_lane_count = lane_count;
return true;
}
static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
int *new_link_rate, int *new_lane_count)
{
/* TODO: Use the same fallback logic on SST as on MST. */
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
return reduce_link_params_in_bw_order(intel_dp, crtc_state,
new_link_rate, new_lane_count);
else
return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,
new_link_rate, new_lane_count);
}
static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
@ -1200,14 +1283,7 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
return 0;
}
new_lane_count = crtc_state->lane_count;
new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
if (new_link_rate < 0) {
new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);
new_link_rate = intel_dp_max_common_rate(intel_dp);
}
if (new_lane_count < 0)
if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))
return -1;
if (intel_dp_is_edp(intel_dp) &&
@ -1228,12 +1304,10 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
return 0;
}
/* NOTE: @state is only valid for MST links and can be %NULL for SST. */
static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state,
struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
@ -1249,11 +1323,6 @@ static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *
return false;
}
if (drm_WARN_ON(&i915->drm,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
!state))
return false;
/* Schedule a Hotplug Uevent to userspace to start modeset */
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
@ -1512,8 +1581,6 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
* retraining with reduced link rate/lane parameters if the link training
* fails.
* After calling this function intel_dp_stop_link_train() must be called.
*
* NOTE: @state is only valid for MST links and can be %NULL for SST.
*/
void intel_dp_start_link_train(struct intel_atomic_state *state,
struct intel_dp *intel_dp,
@ -1530,11 +1597,6 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
*/
int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
if (drm_WARN_ON(&i915->drm,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
!state))
return;
if (lttpr_count < 0)
/* Still continue with enabling the port and link training. */
lttpr_count = 0;

6
drivers/gpu/drm/i915/display/intel_dp_link_training.h
View File

@ -16,6 +16,12 @@ struct intel_dp;
int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
int link_rate, bool is_vrr);
void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
int link_bw, int rate_select, int lane_count,
bool enhanced_framing);
void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy,

100
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -43,6 +43,7 @@
#include "intel_dp_hdcp.h"
#include "intel_dp_mst.h"
#include "intel_dp_tunnel.h"
#include "intel_dp_link_training.h"
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
@ -211,8 +212,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
link_bpp_x16 = to_bpp_x16(dsc ? bpp :
intel_dp_output_bpp(crtc_state->output_format, bpp));
link_bpp_x16 = fxp_q4_from_int(dsc ? bpp :
intel_dp_output_bpp(crtc_state->output_format, bpp));
local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
false, dsc, link_bpp_x16);
@ -289,7 +290,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (!dsc)
crtc_state->pipe_bpp = bpp;
else
crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
}
@ -308,8 +309,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
* YUV420 is only half of the pipe bpp value.
*/
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
to_bpp_int(limits->link.max_bpp_x16),
to_bpp_int(limits->link.min_bpp_x16),
fxp_q4_to_int(limits->link.max_bpp_x16),
fxp_q4_to_int(limits->link.min_bpp_x16),
limits,
conn_state, 2 * 3, false);
@ -374,11 +375,11 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
crtc_state,
max_bpp / 3);
max_compressed_bpp = min(max_compressed_bpp,
to_bpp_int(limits->link.max_bpp_x16));
fxp_q4_to_int(limits->link.max_bpp_x16));
min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
min_compressed_bpp = max(min_compressed_bpp,
to_bpp_int_roundup(limits->link.min_bpp_x16));
fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
min_compressed_bpp, max_compressed_bpp);
@ -478,10 +479,10 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne
crtc->base.base.id, crtc->base.name,
connector->base.base.id, connector->base.name);
if (limits->link.max_bpp_x16 < to_bpp_x16(24))
if (limits->link.max_bpp_x16 < fxp_q4_from_int(24))
return false;
limits->link.min_bpp_x16 = to_bpp_x16(24);
limits->link.min_bpp_x16 = fxp_q4_from_int(24);
return true;
}
@ -489,18 +490,18 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne
drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
if (limits->max_rate < 540000)
min_bpp_x16 = to_bpp_x16(13);
min_bpp_x16 = fxp_q4_from_int(13);
else if (limits->max_rate < 810000)
min_bpp_x16 = to_bpp_x16(10);
min_bpp_x16 = fxp_q4_from_int(10);
if (limits->link.min_bpp_x16 >= min_bpp_x16)
return true;
drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n",
"[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n",
crtc->base.base.id, crtc->base.name,
connector->base.base.id, connector->base.name,
BPP_X16_ARGS(min_bpp_x16));
FXP_Q4_ARGS(min_bpp_x16));
if (limits->link.max_bpp_x16 < min_bpp_x16)
return false;
@ -1113,6 +1114,33 @@ static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
to_intel_crtc(pipe_config->uapi.crtc));
}
static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp,
int link_rate, int lane_count)
{
return intel_dp->link.mst_probed_rate == link_rate &&
intel_dp->link.mst_probed_lane_count == lane_count;
}
static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp,
int link_rate, int lane_count)
{
intel_dp->link.mst_probed_rate = link_rate;
intel_dp->link.mst_probed_lane_count = lane_count;
}
static void intel_mst_reprobe_topology(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
if (intel_mst_probed_link_params_valid(intel_dp,
crtc_state->port_clock, crtc_state->lane_count))
return;
drm_dp_mst_topology_queue_probe(&intel_dp->mst_mgr);
intel_mst_set_probed_link_params(intel_dp,
crtc_state->port_clock, crtc_state->lane_count);
}
static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@ -1149,17 +1177,19 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_sink_enable_decompression(state, connector, pipe_config);
if (first_mst_stream)
if (first_mst_stream) {
dig_port->base.pre_enable(state, &dig_port->base,
pipe_config, NULL);
intel_mst_reprobe_topology(intel_dp, pipe_config);
}
intel_dp->active_mst_links++;
ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
drm_atomic_get_mst_payload_state(mst_state, connector->port));
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
connector->base.name, ret);
intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);
/*
* Before Gen 12 this is not done as part of
@ -1223,6 +1253,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
enum transcoder trans = pipe_config->cpu_transcoder;
bool first_mst_stream = intel_dp->active_mst_links == 1;
struct intel_crtc *pipe_crtc;
int ret;
drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
@ -1254,8 +1285,11 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
if (first_mst_stream)
intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
drm_dp_add_payload_part2(&intel_dp->mst_mgr,
drm_atomic_get_mst_payload_state(mst_state, connector->port));
ret = drm_dp_add_payload_part2(&intel_dp->mst_mgr,
drm_atomic_get_mst_payload_state(mst_state,
connector->port));
if (ret < 0)
intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);
if (DISPLAY_VER(dev_priv) >= 12)
intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),
@ -1998,3 +2032,33 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
return false;
}
/**
* intel_dp_mst_prepare_probe - Prepare an MST link for topology probing
* @intel_dp: DP port object
*
* Prepare an MST link for topology probing, programming the target
* link parameters to DPCD. This step is a requirement of the enumaration
* of path resources during probing.
*/
void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
{
int link_rate = intel_dp_max_link_rate(intel_dp);
int lane_count = intel_dp_max_lane_count(intel_dp);
u8 rate_select;
u8 link_bw;
if (intel_dp->link_trained)
return;
if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))
return;
intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
intel_dp_link_training_set_mode(intel_dp, link_rate, false);
intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
drm_dp_enhanced_frame_cap(intel_dp->dpcd));
intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);
}

1
drivers/gpu/drm/i915/display/intel_dp_mst.h
View File

@ -27,5 +27,6 @@ int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
struct intel_link_bw_limits *limits);
bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);
#endif /* __INTEL_DP_MST_H__ */

2
drivers/gpu/drm/i915/display/intel_dsi.h
View File

@ -66,7 +66,7 @@ struct intel_dsi {
/* number of DSI lanes */
unsigned int lane_count;
/* i2c bus associated with the slave device */
/* i2c bus associated with the target device */
int i2c_bus_num;
/*

20
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
View File

@ -56,7 +56,7 @@
#define MIPI_PORT_SHIFT 3
struct i2c_adapter_lookup {
u16 slave_addr;
u16 target_addr;
struct intel_dsi *intel_dsi;
acpi_handle dev_handle;
};
@ -443,7 +443,7 @@ static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
if (!i2c_acpi_get_i2c_resource(ares, &sb))
return 1;
if (lookup->slave_addr != sb->slave_address)
if (lookup->target_addr != sb->slave_address)
return 1;
status = acpi_get_handle(lookup->dev_handle,
@ -460,12 +460,12 @@ static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
}
static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
const u16 slave_addr)
const u16 target_addr)
{
struct drm_device *drm_dev = intel_dsi->base.base.dev;
struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
struct i2c_adapter_lookup lookup = {
.slave_addr = slave_addr,
.target_addr = target_addr,
.intel_dsi = intel_dsi,
.dev_handle = acpi_device_handle(adev),
};
@ -476,7 +476,7 @@ static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
}
#else
static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
const u16 slave_addr)
const u16 target_addr)
{
}
#endif
@ -488,17 +488,17 @@ static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
struct i2c_msg msg;
int ret;
u8 vbt_i2c_bus_num = *(data + 2);
u16 slave_addr = *(u16 *)(data + 3);
u16 target_addr = *(u16 *)(data + 3);
u8 reg_offset = *(data + 5);
u8 payload_size = *(data + 6);
u8 *payload_data;
drm_dbg_kms(&i915->drm, "bus %d client-addr 0x%02x reg 0x%02x data %*ph\n",
vbt_i2c_bus_num, slave_addr, reg_offset, payload_size, data + 7);
drm_dbg_kms(&i915->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n",
vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7);
if (intel_dsi->i2c_bus_num < 0) {
intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
i2c_acpi_find_adapter(intel_dsi, slave_addr);
i2c_acpi_find_adapter(intel_dsi, target_addr);
}
adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
@ -514,7 +514,7 @@ static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
payload_data[0] = reg_offset;
memcpy(&payload_data[1], (data + 7), payload_size);
msg.addr = slave_addr;
msg.addr = target_addr;
msg.flags = 0;
msg.len = payload_size + 1;
msg.buf = payload_data;

14
drivers/gpu/drm/i915/display/intel_dvo.c
View File

@ -60,42 +60,42 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
.type = INTEL_DVO_CHIP_TMDS,
.name = "sil164",
.port = PORT_C,
.slave_addr = SIL164_ADDR,
.target_addr = SIL164_ADDR,
.dev_ops = &sil164_ops,
},
{
.type = INTEL_DVO_CHIP_TMDS,
.name = "ch7xxx",
.port = PORT_C,
.slave_addr = CH7xxx_ADDR,
.target_addr = CH7xxx_ADDR,
.dev_ops = &ch7xxx_ops,
},
{
.type = INTEL_DVO_CHIP_TMDS,
.name = "ch7xxx",
.port = PORT_C,
.slave_addr = 0x75, /* For some ch7010 */
.target_addr = 0x75, /* For some ch7010 */
.dev_ops = &ch7xxx_ops,
},
{
.type = INTEL_DVO_CHIP_LVDS,
.name = "ivch",
.port = PORT_A,
.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
.target_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
.dev_ops = &ivch_ops,
},
{
.type = INTEL_DVO_CHIP_TMDS,
.name = "tfp410",
.port = PORT_C,
.slave_addr = TFP410_ADDR,
.target_addr = TFP410_ADDR,
.dev_ops = &tfp410_ops,
},
{
.type = INTEL_DVO_CHIP_LVDS,
.name = "ch7017",
.port = PORT_C,
.slave_addr = 0x75,
.target_addr = 0x75,
.gpio = GMBUS_PIN_DPB,
.dev_ops = &ch7017_ops,
},
@ -103,7 +103,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
.type = INTEL_DVO_CHIP_LVDS_NO_FIXED,
.name = "ns2501",
.port = PORT_B,
.slave_addr = NS2501_ADDR,
.target_addr = NS2501_ADDR,
.dev_ops = &ns2501_ops,
},
};

2
drivers/gpu/drm/i915/display/intel_dvo_dev.h
View File

@ -38,7 +38,7 @@ struct intel_dvo_device {
enum port port;
/* GPIO register used for i2c bus to control this device */
u32 gpio;
int slave_addr;
int target_addr;
const struct intel_dvo_dev_ops *dev_ops;
void *dev_priv;

547
drivers/gpu/drm/i915/display/intel_fbc.c
View File

File diff suppressed because it is too large Load Diff

13
drivers/gpu/drm/i915/display/intel_fbc.h
View File

@ -13,6 +13,7 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_display;
struct intel_fbc;
struct intel_plane;
struct intel_plane_state;
@ -31,9 +32,9 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_post_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_init(struct drm_i915_private *dev_priv);
void intel_fbc_cleanup(struct drm_i915_private *dev_priv);
void intel_fbc_sanitize(struct drm_i915_private *dev_priv);
void intel_fbc_init(struct intel_display *display);
void intel_fbc_cleanup(struct intel_display *display);
void intel_fbc_sanitize(struct intel_display *display);
void intel_fbc_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_disable(struct intel_crtc *crtc);
@ -43,9 +44,9 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
void intel_fbc_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin);
void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
void intel_fbc_reset_underrun(struct drm_i915_private *i915);
void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
void intel_fbc_reset_underrun(struct intel_display *display);
void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
void intel_fbc_debugfs_register(struct drm_i915_private *i915);
void intel_fbc_debugfs_register(struct intel_display *display);
#endif /* __INTEL_FBC_H__ */

6
drivers/gpu/drm/i915/display/intel_fdi.c
View File

@ -5,6 +5,8 @@
#include <linux/string_helpers.h>
#include <drm/drm_fixed.h>
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
@ -304,7 +306,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
{
int pipe_bpp = min(crtc_state->pipe_bpp,
to_bpp_int(crtc_state->max_link_bpp_x16));
fxp_q4_to_int(crtc_state->max_link_bpp_x16));
pipe_bpp = rounddown(pipe_bpp, 2 * 3);
@ -340,7 +342,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(to_bpp_x16(pipe_config->pipe_bpp),
intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp),
lane, fdi_dotclock,
link_bw,
intel_dp_bw_fec_overhead(false),

2
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
View File

@ -440,7 +440,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
}
intel_fbc_handle_fifo_underrun_irq(dev_priv);
intel_fbc_handle_fifo_underrun_irq(&dev_priv->display);
}
/**

4
drivers/gpu/drm/i915/display/intel_gmbus.c
View File

@ -478,7 +478,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
/*
* HW spec says that 512Bytes in Burst read need special treatment.
* But it doesn't talk about other multiple of 256Bytes. And couldn't locate
* an I2C slave, which supports such a lengthy burst read too for experiments.
* an I2C target, which supports such a lengthy burst read too for experiments.
*
* So until things get clarified on HW support, to avoid the burst read length
* in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
@ -701,7 +701,7 @@ clear_err:
/* Toggle the Software Clear Interrupt bit. This has the effect
* of resetting the GMBUS controller and so clearing the
* BUS_ERROR raised by the slave's NAK.
* BUS_ERROR raised by the target's NAK.
*/
intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
intel_de_write_fw(i915, GMBUS1(i915), 0);

7
drivers/gpu/drm/i915/display/intel_hdcp.c
View File

@ -203,11 +203,16 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port,
/* Is HDCP1.4 capable on Platform and Sink */
bool intel_hdcp_get_capability(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct intel_digital_port *dig_port;
const struct intel_hdcp_shim *shim = connector->hdcp.shim;
bool capable = false;
u8 bksv[5];
if (!intel_attached_encoder(connector))
return capable;
dig_port = intel_attached_dig_port(connector);
if (!shim)
return capable;

4
drivers/gpu/drm/i915/display/intel_link_bw.c
View File

@ -3,6 +3,8 @@
* Copyright © 2023 Intel Corporation
*/
#include <drm/drm_fixed.h>
#include "i915_drv.h"
#include "intel_atomic.h"
@ -93,7 +95,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
* is based on the pipe bpp value, set the actual link bpp
* limit here once the MST BW allocation is fixed.
*/
link_bpp_x16 = to_bpp_x16(crtc_state->pipe_bpp);
link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp);
if (link_bpp_x16 > max_bpp_x16) {
max_bpp_x16 = link_bpp_x16;

5
drivers/gpu/drm/i915/display/intel_lvds.c
View File

@ -838,6 +838,7 @@ static void intel_lvds_add_properties(struct drm_connector *connector)
*/
void intel_lvds_init(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
struct intel_lvds_encoder *lvds_encoder;
struct intel_connector *connector;
const struct drm_edid *drm_edid;
@ -872,7 +873,7 @@ void intel_lvds_init(struct drm_i915_private *i915)
}
ddc_pin = GMBUS_PIN_PANEL;
if (!intel_bios_is_lvds_present(i915, &ddc_pin)) {
if (!intel_bios_is_lvds_present(display, &ddc_pin)) {
if ((lvds & LVDS_PORT_EN) == 0) {
drm_dbg_kms(&i915->drm,
"LVDS is not present in VBT\n");
@ -966,7 +967,7 @@ void intel_lvds_init(struct drm_i915_private *i915)
} else {
drm_edid = ERR_PTR(-ENOENT);
}
intel_bios_init_panel_late(i915, &connector->panel, NULL,
intel_bios_init_panel_late(display, &connector->panel, NULL,
IS_ERR(drm_edid) ? NULL : drm_edid);
/* Try EDID first */

2
drivers/gpu/drm/i915/display/intel_modeset_setup.c
View File

@ -966,7 +966,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
}
}
intel_fbc_sanitize(i915);
intel_fbc_sanitize(&i915->display);
intel_sanitize_plane_mapping(i915);

320
drivers/gpu/drm/i915/display/intel_opregion.c
View File

@ -252,7 +252,7 @@ struct opregion_asle_ext {
#define OPREGION_SIZE (8 * 1024)
struct intel_opregion {
struct drm_i915_private *i915;
struct intel_display *display;
struct opregion_header *header;
struct opregion_acpi *acpi;
@ -268,9 +268,9 @@ struct intel_opregion {
struct notifier_block acpi_notifier;
};
static int check_swsci_function(struct drm_i915_private *i915, u32 function)
static int check_swsci_function(struct intel_display *display, u32 function)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
struct opregion_swsci *swsci;
u32 main_function, sub_function;
@ -300,20 +300,20 @@ static int check_swsci_function(struct drm_i915_private *i915, u32 function)
return 0;
}
static int swsci(struct drm_i915_private *dev_priv,
static int swsci(struct intel_display *display,
u32 function, u32 parm, u32 *parm_out)
{
struct opregion_swsci *swsci;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
u32 scic, dslp;
u16 swsci_val;
int ret;
ret = check_swsci_function(dev_priv, function);
ret = check_swsci_function(display, function);
if (ret)
return ret;
swsci = dev_priv->display.opregion->swsci;
swsci = display->opregion->swsci;
/* Driver sleep timeout in ms. */
dslp = swsci->dslp;
@ -331,7 +331,7 @@ static int swsci(struct drm_i915_private *dev_priv,
/* The spec tells us to do this, but we are the only user... */
scic = swsci->scic;
if (scic & SWSCI_SCIC_INDICATOR) {
drm_dbg(&dev_priv->drm, "SWSCI request already in progress\n");
drm_dbg(display->drm, "SWSCI request already in progress\n");
return -EBUSY;
}
@ -355,7 +355,7 @@ static int swsci(struct drm_i915_private *dev_priv,
/* Poll for the result. */
#define C (((scic = swsci->scic) & SWSCI_SCIC_INDICATOR) == 0)
if (wait_for(C, dslp)) {
drm_dbg(&dev_priv->drm, "SWSCI request timed out\n");
drm_dbg(display->drm, "SWSCI request timed out\n");
return -ETIMEDOUT;
}
@ -364,7 +364,7 @@ static int swsci(struct drm_i915_private *dev_priv,
/* Note: scic == 0 is an error! */
if (scic != SWSCI_SCIC_EXIT_STATUS_SUCCESS) {
drm_dbg(&dev_priv->drm, "SWSCI request error %u\n", scic);
drm_dbg(display->drm, "SWSCI request error %u\n", scic);
return -EIO;
}
@ -381,28 +381,28 @@ static int swsci(struct drm_i915_private *dev_priv,
#define DISPLAY_TYPE_EXTERNAL_FLAT_PANEL 2
#define DISPLAY_TYPE_INTERNAL_FLAT_PANEL 3
int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
int intel_opregion_notify_encoder(struct intel_encoder *encoder,
bool enable)
{
struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
struct intel_display *display = to_intel_display(encoder);
u32 parm = 0;
u32 type = 0;
u32 port;
int ret;
/* don't care about old stuff for now */
if (!HAS_DDI(dev_priv))
if (!HAS_DDI(display))
return 0;
/* Avoid port out of bounds checks if SWSCI isn't there. */
ret = check_swsci_function(dev_priv, SWSCI_SBCB_DISPLAY_POWER_STATE);
ret = check_swsci_function(display, SWSCI_SBCB_DISPLAY_POWER_STATE);
if (ret)
return ret;
if (intel_encoder->type == INTEL_OUTPUT_DSI)
if (encoder->type == INTEL_OUTPUT_DSI)
port = 0;
else
port = intel_encoder->port;
port = encoder->port;
if (port == PORT_E) {
port = 0;
@ -419,17 +419,17 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
* number is out of bounds after mapping.
*/
if (port > 4) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"[ENCODER:%d:%s] port %c (index %u) out of bounds for display power state notification\n",
intel_encoder->base.base.id, intel_encoder->base.name,
port_name(intel_encoder->port), port);
encoder->base.base.id, encoder->base.name,
port_name(encoder->port), port);
return -EINVAL;
}
if (!enable)
parm |= 4 << 8;
switch (intel_encoder->type) {
switch (encoder->type) {
case INTEL_OUTPUT_ANALOG:
type = DISPLAY_TYPE_CRT;
break;
@ -444,15 +444,15 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
break;
default:
drm_WARN_ONCE(&dev_priv->drm, 1,
drm_WARN_ONCE(display->drm, 1,
"unsupported intel_encoder type %d\n",
intel_encoder->type);
encoder->type);
return -EINVAL;
}
parm |= type << (16 + port * 3);
return swsci(dev_priv, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL);
return swsci(display, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL);
}
static const struct {
@ -466,33 +466,33 @@ static const struct {
{ PCI_D3cold, 0x04 },
};
int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
int intel_opregion_notify_adapter(struct intel_display *display,
pci_power_t state)
{
int i;
if (!HAS_DDI(dev_priv))
if (!HAS_DDI(display))
return 0;
for (i = 0; i < ARRAY_SIZE(power_state_map); i++) {
if (state == power_state_map[i].pci_power_state)
return swsci(dev_priv, SWSCI_SBCB_ADAPTER_POWER_STATE,
return swsci(display, SWSCI_SBCB_ADAPTER_POWER_STATE,
power_state_map[i].parm, NULL);
}
return -EINVAL;
}
static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp)
static u32 asle_set_backlight(struct intel_display *display, u32 bclp)
{
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
struct opregion_asle *asle = dev_priv->display.opregion->asle;
struct opregion_asle *asle = display->opregion->asle;
drm_dbg(&dev_priv->drm, "bclp = 0x%08x\n", bclp);
drm_dbg(display->drm, "bclp = 0x%08x\n", bclp);
if (acpi_video_get_backlight_type() == acpi_backlight_native) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"opregion backlight request ignored\n");
return 0;
}
@ -504,104 +504,104 @@ static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp)
if (bclp > 255)
return ASLC_BACKLIGHT_FAILED;
drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, NULL);
drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL);
/*
* Update backlight on all connectors that support backlight (usually
* only one).
*/
drm_dbg_kms(&dev_priv->drm, "updating opregion backlight %d/255\n",
drm_dbg_kms(display->drm, "updating opregion backlight %d/255\n",
bclp);
drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter)
intel_backlight_set_acpi(connector->base.state, bclp, 255);
drm_connector_list_iter_end(&conn_iter);
asle->cblv = DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID;
drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex);
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
return 0;
}
static u32 asle_set_als_illum(struct drm_i915_private *dev_priv, u32 alsi)
static u32 asle_set_als_illum(struct intel_display *display, u32 alsi)
{
/* alsi is the current ALS reading in lux. 0 indicates below sensor
range, 0xffff indicates above sensor range. 1-0xfffe are valid */
drm_dbg(&dev_priv->drm, "Illum is not supported\n");
drm_dbg(display->drm, "Illum is not supported\n");
return ASLC_ALS_ILLUM_FAILED;
}
static u32 asle_set_pwm_freq(struct drm_i915_private *dev_priv, u32 pfmb)
static u32 asle_set_pwm_freq(struct intel_display *display, u32 pfmb)
{
drm_dbg(&dev_priv->drm, "PWM freq is not supported\n");
drm_dbg(display->drm, "PWM freq is not supported\n");
return ASLC_PWM_FREQ_FAILED;
}
static u32 asle_set_pfit(struct drm_i915_private *dev_priv, u32 pfit)
static u32 asle_set_pfit(struct intel_display *display, u32 pfit)
{
/* Panel fitting is currently controlled by the X code, so this is a
noop until modesetting support works fully */
drm_dbg(&dev_priv->drm, "Pfit is not supported\n");
drm_dbg(display->drm, "Pfit is not supported\n");
return ASLC_PFIT_FAILED;
}
static u32 asle_set_supported_rotation_angles(struct drm_i915_private *dev_priv, u32 srot)
static u32 asle_set_supported_rotation_angles(struct intel_display *display, u32 srot)
{
drm_dbg(&dev_priv->drm, "SROT is not supported\n");
drm_dbg(display->drm, "SROT is not supported\n");
return ASLC_ROTATION_ANGLES_FAILED;
}
static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer)
static u32 asle_set_button_array(struct intel_display *display, u32 iuer)
{
if (!iuer)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Button array event is not supported (nothing)\n");
if (iuer & ASLE_IUER_ROTATION_LOCK_BTN)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Button array event is not supported (rotation lock)\n");
if (iuer & ASLE_IUER_VOLUME_DOWN_BTN)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Button array event is not supported (volume down)\n");
if (iuer & ASLE_IUER_VOLUME_UP_BTN)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Button array event is not supported (volume up)\n");
if (iuer & ASLE_IUER_WINDOWS_BTN)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Button array event is not supported (windows)\n");
if (iuer & ASLE_IUER_POWER_BTN)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Button array event is not supported (power)\n");
return ASLC_BUTTON_ARRAY_FAILED;
}
static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer)
static u32 asle_set_convertible(struct intel_display *display, u32 iuer)
{
if (iuer & ASLE_IUER_CONVERTIBLE)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Convertible is not supported (clamshell)\n");
else
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Convertible is not supported (slate)\n");
return ASLC_CONVERTIBLE_FAILED;
}
static u32 asle_set_docking(struct drm_i915_private *dev_priv, u32 iuer)
static u32 asle_set_docking(struct intel_display *display, u32 iuer)
{
if (iuer & ASLE_IUER_DOCKING)
drm_dbg(&dev_priv->drm, "Docking is not supported (docked)\n");
drm_dbg(display->drm, "Docking is not supported (docked)\n");
else
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"Docking is not supported (undocked)\n");
return ASLC_DOCKING_FAILED;
}
static u32 asle_isct_state(struct drm_i915_private *dev_priv)
static u32 asle_isct_state(struct intel_display *display)
{
drm_dbg(&dev_priv->drm, "ISCT is not supported\n");
drm_dbg(display->drm, "ISCT is not supported\n");
return ASLC_ISCT_STATE_FAILED;
}
@ -609,7 +609,7 @@ static void asle_work(struct work_struct *work)
{
struct intel_opregion *opregion =
container_of(work, struct intel_opregion, asle_work);
struct drm_i915_private *dev_priv = opregion->i915;
struct intel_display *display = opregion->display;
struct opregion_asle *asle = opregion->asle;
u32 aslc_stat = 0;
u32 aslc_req;
@ -620,50 +620,51 @@ static void asle_work(struct work_struct *work)
aslc_req = asle->aslc;
if (!(aslc_req & ASLC_REQ_MSK)) {
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"No request on ASLC interrupt 0x%08x\n", aslc_req);
return;
}
if (aslc_req & ASLC_SET_ALS_ILLUM)
aslc_stat |= asle_set_als_illum(dev_priv, asle->alsi);
aslc_stat |= asle_set_als_illum(display, asle->alsi);
if (aslc_req & ASLC_SET_BACKLIGHT)
aslc_stat |= asle_set_backlight(dev_priv, asle->bclp);
aslc_stat |= asle_set_backlight(display, asle->bclp);
if (aslc_req & ASLC_SET_PFIT)
aslc_stat |= asle_set_pfit(dev_priv, asle->pfit);
aslc_stat |= asle_set_pfit(display, asle->pfit);
if (aslc_req & ASLC_SET_PWM_FREQ)
aslc_stat |= asle_set_pwm_freq(dev_priv, asle->pfmb);
aslc_stat |= asle_set_pwm_freq(display, asle->pfmb);
if (aslc_req & ASLC_SUPPORTED_ROTATION_ANGLES)
aslc_stat |= asle_set_supported_rotation_angles(dev_priv,
aslc_stat |= asle_set_supported_rotation_angles(display,
asle->srot);
if (aslc_req & ASLC_BUTTON_ARRAY)
aslc_stat |= asle_set_button_array(dev_priv, asle->iuer);
aslc_stat |= asle_set_button_array(display, asle->iuer);
if (aslc_req & ASLC_CONVERTIBLE_INDICATOR)
aslc_stat |= asle_set_convertible(dev_priv, asle->iuer);
aslc_stat |= asle_set_convertible(display, asle->iuer);
if (aslc_req & ASLC_DOCKING_INDICATOR)
aslc_stat |= asle_set_docking(dev_priv, asle->iuer);
aslc_stat |= asle_set_docking(display, asle->iuer);
if (aslc_req & ASLC_ISCT_STATE_CHANGE)
aslc_stat |= asle_isct_state(dev_priv);
aslc_stat |= asle_isct_state(display);
asle->aslc = aslc_stat;
}
bool intel_opregion_asle_present(struct drm_i915_private *i915)
bool intel_opregion_asle_present(struct intel_display *display)
{
return i915->display.opregion && i915->display.opregion->asle;
return display->opregion && display->opregion->asle;
}
void intel_opregion_asle_intr(struct drm_i915_private *i915)
void intel_opregion_asle_intr(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_opregion *opregion = display->opregion;
if (opregion && opregion->asle)
queue_work(i915->unordered_wq, &opregion->asle_work);
@ -720,9 +721,9 @@ static void set_did(struct intel_opregion *opregion, int i, u32 val)
}
}
static void intel_didl_outputs(struct drm_i915_private *dev_priv)
static void intel_didl_outputs(struct intel_display *display)
{
struct intel_opregion *opregion = dev_priv->display.opregion;
struct intel_opregion *opregion = display->opregion;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
int i = 0, max_outputs;
@ -737,9 +738,9 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv)
max_outputs = ARRAY_SIZE(opregion->acpi->didl) +
ARRAY_SIZE(opregion->acpi->did2);
intel_acpi_device_id_update(dev_priv);
intel_acpi_device_id_update(display);
drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
if (i < max_outputs)
set_did(opregion, i, connector->acpi_device_id);
@ -747,10 +748,10 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv)
}
drm_connector_list_iter_end(&conn_iter);
drm_dbg_kms(&dev_priv->drm, "%d outputs detected\n", i);
drm_dbg_kms(display->drm, "%d outputs detected\n", i);
if (i > max_outputs)
drm_err(&dev_priv->drm,
drm_err(display->drm,
"More than %d outputs in connector list\n",
max_outputs);
@ -759,9 +760,9 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv)
set_did(opregion, i, 0);
}
static void intel_setup_cadls(struct drm_i915_private *dev_priv)
static void intel_setup_cadls(struct intel_display *display)
{
struct intel_opregion *opregion = dev_priv->display.opregion;
struct intel_opregion *opregion = display->opregion;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
int i = 0;
@ -776,7 +777,7 @@ static void intel_setup_cadls(struct drm_i915_private *dev_priv)
* Note that internal panels should be at the front of the connector
* list already, ensuring they're not left out.
*/
drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
drm_connector_list_iter_begin(display->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
if (i >= ARRAY_SIZE(opregion->acpi->cadl))
break;
@ -789,9 +790,9 @@ static void intel_setup_cadls(struct drm_i915_private *dev_priv)
opregion->acpi->cadl[i] = 0;
}
static void swsci_setup(struct drm_i915_private *dev_priv)
static void swsci_setup(struct intel_display *display)
{
struct intel_opregion *opregion = dev_priv->display.opregion;
struct intel_opregion *opregion = display->opregion;
bool requested_callbacks = false;
u32 tmp;
@ -800,7 +801,7 @@ static void swsci_setup(struct drm_i915_private *dev_priv)
opregion->swsci_sbcb_sub_functions = 1;
/* We use GBDA to ask for supported GBDA calls. */
if (swsci(dev_priv, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {
if (swsci(display, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {
/* make the bits match the sub-function codes */
tmp <<= 1;
opregion->swsci_gbda_sub_functions |= tmp;
@ -811,7 +812,7 @@ static void swsci_setup(struct drm_i915_private *dev_priv)
* must not call interfaces that are not specifically requested by the
* bios.
*/
if (swsci(dev_priv, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {
if (swsci(display, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {
/* here, the bits already match sub-function codes */
opregion->swsci_sbcb_sub_functions |= tmp;
requested_callbacks = true;
@ -822,7 +823,7 @@ static void swsci_setup(struct drm_i915_private *dev_priv)
* the callback is _requested_. But we still can't call interfaces that
* are not requested.
*/
if (swsci(dev_priv, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {
if (swsci(display, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {
/* make the bits match the sub-function codes */
u32 low = tmp & 0x7ff;
u32 high = tmp & ~0xfff; /* bit 11 is reserved */
@ -832,7 +833,7 @@ static void swsci_setup(struct drm_i915_private *dev_priv)
if (requested_callbacks) {
u32 req = opregion->swsci_sbcb_sub_functions;
if ((req & tmp) != req)
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n",
req, tmp);
/* XXX: for now, trust the requested callbacks */
@ -842,7 +843,7 @@ static void swsci_setup(struct drm_i915_private *dev_priv)
}
}
drm_dbg(&dev_priv->drm,
drm_dbg(display->drm,
"SWSCI GBDA callbacks %08x, SBCB callbacks %08x\n",
opregion->swsci_gbda_sub_functions,
opregion->swsci_sbcb_sub_functions);
@ -867,10 +868,10 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = {
{ }
};
int intel_opregion_setup(struct drm_i915_private *dev_priv)
int intel_opregion_setup(struct intel_display *display)
{
struct intel_opregion *opregion;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
u32 asls, mboxes;
char buf[sizeof(OPREGION_SIGNATURE)];
int err = 0;
@ -885,10 +886,10 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400);
pci_read_config_dword(pdev, ASLS, &asls);
drm_dbg(&dev_priv->drm, "graphic opregion physical addr: 0x%x\n",
drm_dbg(display->drm, "graphic opregion physical addr: 0x%x\n",
asls);
if (asls == 0) {
drm_dbg(&dev_priv->drm, "ACPI OpRegion not supported!\n");
drm_dbg(display->drm, "ACPI OpRegion not supported!\n");
return -ENOTSUPP;
}
@ -896,8 +897,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
if (!opregion)
return -ENOMEM;
opregion->i915 = dev_priv;
dev_priv->display.opregion = opregion;
opregion->display = display;
display->opregion = opregion;
INIT_WORK(&opregion->asle_work, asle_work);
@ -910,20 +911,20 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
memcpy(buf, base, sizeof(buf));
if (memcmp(buf, OPREGION_SIGNATURE, 16)) {
drm_dbg(&dev_priv->drm, "opregion signature mismatch\n");
drm_dbg(display->drm, "opregion signature mismatch\n");
err = -EINVAL;
goto err_out;
}
opregion->header = base;
drm_dbg(&dev_priv->drm, "ACPI OpRegion version %u.%u.%u\n",
drm_dbg(display->drm, "ACPI OpRegion version %u.%u.%u\n",
opregion->header->over.major,
opregion->header->over.minor,
opregion->header->over.revision);
mboxes = opregion->header->mboxes;
if (mboxes & MBOX_ACPI) {
drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
drm_dbg(display->drm, "Public ACPI methods supported\n");
opregion->acpi = base + OPREGION_ACPI_OFFSET;
/*
* Indicate we handle monitor hotplug events ourselves so we do
@ -938,30 +939,30 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
u8 major = opregion->header->over.major;
if (major >= 3) {
drm_err(&dev_priv->drm, "SWSCI Mailbox #2 present for opregion v3.x, ignoring\n");
drm_err(display->drm, "SWSCI Mailbox #2 present for opregion v3.x, ignoring\n");
} else {
if (major >= 2)
drm_dbg(&dev_priv->drm, "SWSCI Mailbox #2 present for opregion v2.x\n");
drm_dbg(&dev_priv->drm, "SWSCI supported\n");
drm_dbg(display->drm, "SWSCI Mailbox #2 present for opregion v2.x\n");
drm_dbg(display->drm, "SWSCI supported\n");
opregion->swsci = base + OPREGION_SWSCI_OFFSET;
swsci_setup(dev_priv);
swsci_setup(display);
}
}
if (mboxes & MBOX_ASLE) {
drm_dbg(&dev_priv->drm, "ASLE supported\n");
drm_dbg(display->drm, "ASLE supported\n");
opregion->asle = base + OPREGION_ASLE_OFFSET;
opregion->asle->ardy = ASLE_ARDY_NOT_READY;
}
if (mboxes & MBOX_ASLE_EXT) {
drm_dbg(&dev_priv->drm, "ASLE extension supported\n");
drm_dbg(display->drm, "ASLE extension supported\n");
opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
}
if (mboxes & MBOX_BACKLIGHT) {
drm_dbg(&dev_priv->drm, "Mailbox #2 for backlight present\n");
drm_dbg(display->drm, "Mailbox #2 for backlight present\n");
}
if (dmi_check_system(intel_no_opregion_vbt))
@ -979,7 +980,7 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
*/
if (opregion->header->over.major > 2 ||
opregion->header->over.minor >= 1) {
drm_WARN_ON(&dev_priv->drm, rvda < OPREGION_SIZE);
drm_WARN_ON(display->drm, rvda < OPREGION_SIZE);
rvda += asls;
}
@ -989,14 +990,14 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
vbt = opregion->rvda;
vbt_size = opregion->asle->rvds;
if (intel_bios_is_valid_vbt(dev_priv, vbt, vbt_size)) {
drm_dbg_kms(&dev_priv->drm,
if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {
drm_dbg_kms(display->drm,
"Found valid VBT in ACPI OpRegion (RVDA)\n");
opregion->vbt = vbt;
opregion->vbt_size = vbt_size;
goto out;
} else {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Invalid VBT in ACPI OpRegion (RVDA)\n");
memunmap(opregion->rvda);
opregion->rvda = NULL;
@ -1014,13 +1015,13 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
vbt_size = (mboxes & MBOX_ASLE_EXT) ?
OPREGION_ASLE_EXT_OFFSET : OPREGION_SIZE;
vbt_size -= OPREGION_VBT_OFFSET;
if (intel_bios_is_valid_vbt(dev_priv, vbt, vbt_size)) {
drm_dbg_kms(&dev_priv->drm,
if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) {
drm_dbg_kms(display->drm,
"Found valid VBT in ACPI OpRegion (Mailbox #4)\n");
opregion->vbt = vbt;
opregion->vbt_size = vbt_size;
} else {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Invalid VBT in ACPI OpRegion (Mailbox #4)\n");
}
@ -1031,7 +1032,7 @@ err_out:
memunmap(base);
err_memremap:
kfree(opregion);
dev_priv->display.opregion = NULL;
display->opregion = NULL;
return err;
}
@ -1054,25 +1055,25 @@ static const struct dmi_system_id intel_use_opregion_panel_type[] = {
};
int
intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
intel_opregion_get_panel_type(struct intel_display *display)
{
u32 panel_details;
int ret;
ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);
ret = swsci(display, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);
if (ret)
return ret;
ret = (panel_details >> 8) & 0xff;
if (ret > 0x10) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Invalid OpRegion panel type 0x%x\n", ret);
return -EINVAL;
}
/* fall back to VBT panel type? */
if (ret == 0x0) {
drm_dbg_kms(&dev_priv->drm, "No panel type in OpRegion\n");
drm_dbg_kms(display->drm, "No panel type in OpRegion\n");
return -ENODEV;
}
@ -1082,7 +1083,7 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
* via a quirk list :(
*/
if (!dmi_check_system(intel_use_opregion_panel_type)) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Ignoring OpRegion panel type (%d)\n", ret - 1);
return -ENODEV;
}
@ -1092,7 +1093,7 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
/**
* intel_opregion_get_edid - Fetch EDID from ACPI OpRegion mailbox #5
* @intel_connector: eDP connector
* @connector: eDP connector
*
* This reads the ACPI Opregion mailbox #5 to extract the EDID that is passed
* to it.
@ -1101,11 +1102,10 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
* The EDID in the OpRegion, or NULL if there is none or it's invalid.
*
*/
const struct drm_edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
const struct drm_edid *intel_opregion_get_edid(struct intel_connector *connector)
{
struct drm_connector *connector = &intel_connector->base;
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_opregion *opregion = i915->display.opregion;
struct intel_display *display = to_intel_display(connector);
struct intel_opregion *opregion = display->opregion;
const struct drm_edid *drm_edid;
const void *edid;
int len;
@ -1123,7 +1123,7 @@ const struct drm_edid *intel_opregion_get_edid(struct intel_connector *intel_con
drm_edid = drm_edid_alloc(edid, len);
if (!drm_edid_valid(drm_edid)) {
drm_dbg_kms(&i915->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n");
drm_dbg_kms(display->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n");
drm_edid_free(drm_edid);
drm_edid = NULL;
}
@ -1131,9 +1131,9 @@ const struct drm_edid *intel_opregion_get_edid(struct intel_connector *intel_con
return drm_edid;
}
bool intel_opregion_vbt_present(struct drm_i915_private *i915)
bool intel_opregion_vbt_present(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (!opregion || !opregion->vbt)
return false;
@ -1141,9 +1141,9 @@ bool intel_opregion_vbt_present(struct drm_i915_private *i915)
return true;
}
const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size)
const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (!opregion || !opregion->vbt)
return NULL;
@ -1154,9 +1154,9 @@ const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size)
return kmemdup(opregion->vbt, opregion->vbt_size, GFP_KERNEL);
}
bool intel_opregion_headless_sku(struct drm_i915_private *i915)
bool intel_opregion_headless_sku(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
struct opregion_header *header;
if (!opregion)
@ -1171,9 +1171,9 @@ bool intel_opregion_headless_sku(struct drm_i915_private *i915)
return opregion->header->pcon & PCON_HEADLESS_SKU;
}
void intel_opregion_register(struct drm_i915_private *i915)
void intel_opregion_register(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (!opregion)
return;
@ -1184,16 +1184,16 @@ void intel_opregion_register(struct drm_i915_private *i915)
register_acpi_notifier(&opregion->acpi_notifier);
}
intel_opregion_resume(i915);
intel_opregion_resume(display);
}
static void intel_opregion_resume_display(struct drm_i915_private *i915)
static void intel_opregion_resume_display(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (opregion->acpi) {
intel_didl_outputs(i915);
intel_setup_cadls(i915);
intel_didl_outputs(display);
intel_setup_cadls(display);
/*
* Notify BIOS we are ready to handle ACPI video ext notifs.
@ -1210,25 +1210,25 @@ static void intel_opregion_resume_display(struct drm_i915_private *i915)
}
/* Some platforms abuse the _DSM to enable MUX */
intel_dsm_get_bios_data_funcs_supported(i915);
intel_dsm_get_bios_data_funcs_supported(display);
}
void intel_opregion_resume(struct drm_i915_private *i915)
void intel_opregion_resume(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (!opregion)
return;
if (HAS_DISPLAY(i915))
intel_opregion_resume_display(i915);
if (HAS_DISPLAY(display))
intel_opregion_resume_display(display);
intel_opregion_notify_adapter(i915, PCI_D0);
intel_opregion_notify_adapter(display, PCI_D0);
}
static void intel_opregion_suspend_display(struct drm_i915_private *i915)
static void intel_opregion_suspend_display(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (opregion->asle)
opregion->asle->ardy = ASLE_ARDY_NOT_READY;
@ -1239,24 +1239,24 @@ static void intel_opregion_suspend_display(struct drm_i915_private *i915)
opregion->acpi->drdy = 0;
}
void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state)
void intel_opregion_suspend(struct intel_display *display, pci_power_t state)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (!opregion)
return;
intel_opregion_notify_adapter(i915, state);
intel_opregion_notify_adapter(display, state);
if (HAS_DISPLAY(i915))
intel_opregion_suspend_display(i915);
if (HAS_DISPLAY(display))
intel_opregion_suspend_display(display);
}
void intel_opregion_unregister(struct drm_i915_private *i915)
void intel_opregion_unregister(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
intel_opregion_suspend(i915, PCI_D1);
intel_opregion_suspend(display, PCI_D1);
if (!opregion)
return;
@ -1267,9 +1267,9 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
}
}
void intel_opregion_cleanup(struct drm_i915_private *i915)
void intel_opregion_cleanup(struct intel_display *display)
{
struct intel_opregion *opregion = i915->display.opregion;
struct intel_opregion *opregion = display->opregion;
if (!opregion)
return;
@ -1278,13 +1278,13 @@ void intel_opregion_cleanup(struct drm_i915_private *i915)
if (opregion->rvda)
memunmap(opregion->rvda);
kfree(opregion);
i915->display.opregion = NULL;
display->opregion = NULL;
}
static int intel_opregion_show(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = m->private;
struct intel_opregion *opregion = i915->display.opregion;
struct intel_display *display = m->private;
struct intel_opregion *opregion = display->opregion;
if (opregion)
seq_write(m, opregion->header, OPREGION_SIZE);
@ -1294,10 +1294,10 @@ static int intel_opregion_show(struct seq_file *m, void *unused)
DEFINE_SHOW_ATTRIBUTE(intel_opregion);
void intel_opregion_debugfs_register(struct drm_i915_private *i915)
void intel_opregion_debugfs_register(struct intel_display *display)
{
struct drm_minor *minor = i915->drm.primary;
struct drm_minor *minor = display->drm->primary;
debugfs_create_file("i915_opregion", 0444, minor->debugfs_root,
i915, &intel_opregion_fops);
display, &intel_opregion_fops);
}

62
drivers/gpu/drm/i915/display/intel_opregion.h
View File

@ -28,88 +28,88 @@
#include <linux/pci.h>
#include <linux/types.h>
struct drm_i915_private;
struct intel_connector;
struct intel_display;
struct intel_encoder;
#ifdef CONFIG_ACPI
int intel_opregion_setup(struct drm_i915_private *dev_priv);
void intel_opregion_cleanup(struct drm_i915_private *i915);
int intel_opregion_setup(struct intel_display *display);
void intel_opregion_cleanup(struct intel_display *display);
void intel_opregion_register(struct drm_i915_private *dev_priv);
void intel_opregion_unregister(struct drm_i915_private *dev_priv);
void intel_opregion_register(struct intel_display *display);
void intel_opregion_unregister(struct intel_display *display);
void intel_opregion_resume(struct drm_i915_private *dev_priv);
void intel_opregion_suspend(struct drm_i915_private *dev_priv,
void intel_opregion_resume(struct intel_display *display);
void intel_opregion_suspend(struct intel_display *display,
pci_power_t state);
bool intel_opregion_asle_present(struct drm_i915_private *i915);
void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
bool intel_opregion_asle_present(struct intel_display *display);
void intel_opregion_asle_intr(struct intel_display *display);
int intel_opregion_notify_encoder(struct intel_encoder *encoder,
bool enable);
int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
int intel_opregion_notify_adapter(struct intel_display *display,
pci_power_t state);
int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
int intel_opregion_get_panel_type(struct intel_display *display);
const struct drm_edid *intel_opregion_get_edid(struct intel_connector *connector);
bool intel_opregion_vbt_present(struct drm_i915_private *i915);
const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size);
bool intel_opregion_vbt_present(struct intel_display *display);
const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size);
bool intel_opregion_headless_sku(struct drm_i915_private *i915);
bool intel_opregion_headless_sku(struct intel_display *display);
void intel_opregion_debugfs_register(struct drm_i915_private *i915);
void intel_opregion_debugfs_register(struct intel_display *display);
#else /* CONFIG_ACPI*/
static inline int intel_opregion_setup(struct drm_i915_private *dev_priv)
static inline int intel_opregion_setup(struct intel_display *display)
{
return 0;
}
static inline void intel_opregion_cleanup(struct drm_i915_private *i915)
static inline void intel_opregion_cleanup(struct intel_display *display)
{
}
static inline void intel_opregion_register(struct drm_i915_private *dev_priv)
static inline void intel_opregion_register(struct intel_display *display)
{
}
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv)
static inline void intel_opregion_unregister(struct intel_display *display)
{
}
static inline void intel_opregion_resume(struct drm_i915_private *dev_priv)
static inline void intel_opregion_resume(struct intel_display *display)
{
}
static inline void intel_opregion_suspend(struct drm_i915_private *dev_priv,
static inline void intel_opregion_suspend(struct intel_display *display,
pci_power_t state)
{
}
static inline bool intel_opregion_asle_present(struct drm_i915_private *i915)
static inline bool intel_opregion_asle_present(struct intel_display *display)
{
return false;
}
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
static inline void intel_opregion_asle_intr(struct intel_display *display)
{
}
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
intel_opregion_notify_encoder(struct intel_encoder *encoder, bool enable)
{
return 0;
}
static inline int
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
intel_opregion_notify_adapter(struct intel_display *display, pci_power_t state)
{
return 0;
}
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
static inline int intel_opregion_get_panel_type(struct intel_display *display)
{
return -ENODEV;
}
@ -120,23 +120,23 @@ intel_opregion_get_edid(struct intel_connector *connector)
return NULL;
}
static inline bool intel_opregion_vbt_present(struct drm_i915_private *i915)
static inline bool intel_opregion_vbt_present(struct intel_display *display)
{
return false;
}
static inline const void *
intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size)
intel_opregion_get_vbt(struct intel_display *display, size_t *size)
{
return NULL;
}
static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915)
static inline bool intel_opregion_headless_sku(struct intel_display *display)
{
return false;
}
static inline void intel_opregion_debugfs_register(struct drm_i915_private *i915)
static inline void intel_opregion_debugfs_register(struct intel_display *display)
{
}

3
drivers/gpu/drm/i915/display/intel_pps.c
View File

@ -351,6 +351,9 @@ static int intel_num_pps(struct drm_i915_private *i915)
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
return 2;
if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
return 2;
if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
return 1;

33
drivers/gpu/drm/i915/display/intel_sdvo.c
View File

@ -95,7 +95,7 @@ struct intel_sdvo {
struct intel_encoder base;
struct i2c_adapter *i2c;
u8 slave_addr;
u8 target_addr;
struct intel_sdvo_ddc ddc[3];
@ -255,13 +255,13 @@ static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
struct i2c_msg msgs[] = {
{
.addr = intel_sdvo->slave_addr,
.addr = intel_sdvo->target_addr,
.flags = 0,
.len = 1,
.buf = &addr,
},
{
.addr = intel_sdvo->slave_addr,
.addr = intel_sdvo->target_addr,
.flags = I2C_M_RD,
.len = 1,
.buf = ch,
@ -483,14 +483,14 @@ static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
for (i = 0; i < args_len; i++) {
msgs[i].addr = intel_sdvo->slave_addr;
msgs[i].addr = intel_sdvo->target_addr;
msgs[i].flags = 0;
msgs[i].len = 2;
msgs[i].buf = buf + 2 *i;
buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
buf[2*i + 1] = ((u8*)args)[i];
}
msgs[i].addr = intel_sdvo->slave_addr;
msgs[i].addr = intel_sdvo->target_addr;
msgs[i].flags = 0;
msgs[i].len = 2;
msgs[i].buf = buf + 2*i;
@ -499,12 +499,12 @@ static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
/* the following two are to read the response */
status = SDVO_I2C_CMD_STATUS;
msgs[i+1].addr = intel_sdvo->slave_addr;
msgs[i+1].addr = intel_sdvo->target_addr;
msgs[i+1].flags = 0;
msgs[i+1].len = 1;
msgs[i+1].buf = &status;
msgs[i+2].addr = intel_sdvo->slave_addr;
msgs[i+2].addr = intel_sdvo->target_addr;
msgs[i+2].flags = I2C_M_RD;
msgs[i+2].len = 1;
msgs[i+2].buf = &status;
@ -2652,9 +2652,9 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
else
pin = GMBUS_PIN_DPB;
drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n",
drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n",
sdvo->base.base.base.id, sdvo->base.base.name,
pin, sdvo->slave_addr);
pin, sdvo->target_addr);
sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
@ -2680,7 +2680,7 @@ intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo)
}
static u8
intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo)
intel_sdvo_get_target_addr(struct intel_sdvo *sdvo)
{
struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
const struct sdvo_device_mapping *my_mapping, *other_mapping;
@ -2694,15 +2694,15 @@ intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo)
}
/* If the BIOS described our SDVO device, take advantage of it. */
if (my_mapping->slave_addr)
return my_mapping->slave_addr;
if (my_mapping->target_addr)
return my_mapping->target_addr;
/*
* If the BIOS only described a different SDVO device, use the
* address that it isn't using.
*/
if (other_mapping->slave_addr) {
if (other_mapping->slave_addr == 0x70)
if (other_mapping->target_addr) {
if (other_mapping->target_addr == 0x70)
return 0x72;
else
return 0x70;
@ -2919,6 +2919,7 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
static bool
intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
{
struct intel_display *display = to_intel_display(&intel_sdvo->base);
struct drm_encoder *encoder = &intel_sdvo->base.base;
struct drm_i915_private *i915 = to_i915(encoder->dev);
struct drm_connector *connector;
@ -2946,7 +2947,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
goto err;
intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL);
intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL);
/*
* Fetch modes from VBT. For SDVO prefer the VBT mode since some
@ -3405,7 +3406,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
"SDVO %c", port_name(port));
intel_sdvo->sdvo_reg = sdvo_reg;
intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(intel_sdvo) >> 1;
intel_sdvo->target_addr = intel_sdvo_get_target_addr(intel_sdvo) >> 1;
intel_sdvo_select_i2c_bus(intel_sdvo);

3
drivers/gpu/drm/i915/display/intel_tc.c
View File

@ -393,6 +393,9 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
u32 val;
if (DISPLAY_VER(i915) >= 14)
return;
drm_WARN_ON(&i915->drm,
lane_reversal && tc->mode != TC_PORT_LEGACY);

3
drivers/gpu/drm/i915/display/intel_tv.c
View File

@ -1930,6 +1930,7 @@ static void intel_tv_add_properties(struct drm_connector *connector)
void
intel_tv_init(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct drm_connector *connector;
struct intel_tv *intel_tv;
struct intel_encoder *intel_encoder;
@ -1939,7 +1940,7 @@ intel_tv_init(struct drm_i915_private *dev_priv)
if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
return;
if (!intel_bios_is_tv_present(dev_priv)) {
if (!intel_bios_is_tv_present(display)) {
drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
return;
}

3
drivers/gpu/drm/i915/display/intel_vblank.c
View File

@ -652,7 +652,8 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
*/
if (intel_color_uses_dsb(new_crtc_state) ||
new_crtc_state->update_m_n || new_crtc_state->update_lrr)
evade->min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
evade->min -= intel_mode_vblank_start(adjusted_mode) -
intel_mode_vdisplay(adjusted_mode);
}
/* must be called with vblank interrupt already enabled! */

4
drivers/gpu/drm/i915/display/intel_vbt_defs.h
View File

@ -493,7 +493,7 @@ struct child_device_config {
u16 addin_offset;
u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
u8 i2c_pin;
u8 slave_addr;
u8 target_addr;
u8 ddc_pin;
u16 edid_ptr;
u8 dvo_cfg; /* See DEVICE_CFG_* above */
@ -502,7 +502,7 @@ struct child_device_config {
struct {
u8 dvo2_port;
u8 i2c2_pin;
u8 slave2_addr;
u8 target2_addr;
u8 ddc2_pin;
} __packed;
struct {

51
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -8,6 +8,7 @@
#include <linux/limits.h>
#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_fixed.h>
#include "i915_drv.h"
#include "intel_crtc.h"
@ -76,7 +77,7 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
static void
calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpp = to_bpp_int(vdsc_cfg->bits_per_pixel);
int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel);
int bpc = vdsc_cfg->bits_per_component;
int qp_bpc_modifier = (bpc - 8) * 2;
int uncompressed_bpg_rate;
@ -184,7 +185,7 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
}
} else {
/* fractional bpp part * 10000 (for precision up to 4 decimal places) */
int fractional_bits = to_bpp_frac(vdsc_cfg->bits_per_pixel);
int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel);
static const s8 ofs_und6[] = {
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
@ -263,7 +264,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
int err;
int ret;
@ -456,36 +457,30 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val |= DSC_PPS0_422_ENABLE;
if (vdsc_cfg->vbr_enable)
pps_val |= DSC_PPS0_VBR_ENABLE;
drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 0, pps_val);
/* PPS 1 */
pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 1, pps_val);
/* PPS 2 */
pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 2, pps_val);
/* PPS 3 */
pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 3, pps_val);
/* PPS 4 */
pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 4, pps_val);
/* PPS 5 */
pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 5, pps_val);
/* PPS 6 */
@ -493,25 +488,21 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 6, pps_val);
/* PPS 7 */
pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 7, pps_val);
/* PPS 8 */
pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 8, pps_val);
/* PPS 9 */
pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 9, pps_val);
/* PPS 10 */
@ -519,7 +510,6 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 10, pps_val);
/* PPS 16 */
@ -528,31 +518,25 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
vdsc_cfg->slice_width) |
DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
vdsc_cfg->slice_height);
drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 16, pps_val);
if (DISPLAY_VER(dev_priv) >= 14) {
/* PPS 17 */
pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 17, pps_val);
/* PPS 18 */
pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 18, pps_val);
}
/* Populate the RC_BUF_THRESH registers */
memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
rc_buf_thresh_dword[i / 4] |=
(u32)(vdsc_cfg->rc_buf_thresh[i] <<
BITS_PER_BYTE * (i % 4));
drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
rc_buf_thresh_dword[i / 4]);
}
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
rc_buf_thresh_dword[0]);
@ -599,7 +583,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
/* Populate the RC_RANGE_PARAMETERS registers */
memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
for (i = 0; i < DSC_NUM_BUF_RANGES; i++)
rc_range_params_dword[i / 2] |=
(u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
RC_BPG_OFFSET_SHIFT) |
@ -607,9 +591,6 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
RC_MAX_QP_SHIFT) |
(vdsc_cfg->rc_range_params[i].range_min_qp <<
RC_MIN_QP_SHIFT)) << 16 * (i % 2));
drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
rc_range_params_dword[i / 2]);
}
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
rc_range_params_dword[0]);
@ -989,3 +970,23 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
const struct intel_crtc_state *crtc_state)
{
drm_printf_indent(p, indent,
"dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",
FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
crtc_state->dsc.slice_count,
str_yes_no(crtc_state->dsc.dsc_split));
}
void intel_vdsc_state_dump(struct drm_printer *p, int indent,
const struct intel_crtc_state *crtc_state)
{
if (!crtc_state->dsc.compression_enable)
return;
intel_vdsc_dump_state(p, indent, crtc_state);
drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
}

4
drivers/gpu/drm/i915/display/intel_vdsc.h
View File

@ -8,6 +8,8 @@
#include <linux/types.h>
struct drm_printer;
enum transcoder;
struct intel_crtc;
struct intel_crtc_state;
@ -27,5 +29,7 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_vdsc_state_dump(struct drm_printer *p, int indent,
const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VDSC_H__ */

3
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -233,8 +233,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
if (intel_dp_as_sdp_supported(intel_dp) &&
crtc_state->vrr.enable) {
if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) {
crtc_state->vrr.vsync_start =
(crtc_state->hw.adjusted_mode.crtc_vtotal -
crtc_state->hw.adjusted_mode.vsync_start);

24
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -2830,17 +2830,17 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
}
/*
* If Fixed Refresh Rate:
* If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline:
* Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
* watermark level1 and up and above. If watermark level 1 is
* invalid program it with all 1's.
* Program PKG_C_LATENCY Added Wake Time = DSB execution time
* If Variable Refresh Rate:
* If Variable Refresh Rate where Vmin != Vmax != Flipline:
* Program DEEP PKG_C_LATENCY Pkg C with all 1's.
* Program PKG_C_LATENCY Added Wake Time = 0
*/
static void
skl_program_dpkgc_latency(struct drm_i915_private *i915, bool vrr_enabled)
skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
{
u32 max_latency = 0;
u32 clear = 0, val = 0;
@ -2849,15 +2849,15 @@ skl_program_dpkgc_latency(struct drm_i915_private *i915, bool vrr_enabled)
if (DISPLAY_VER(i915) < 20)
return;
if (vrr_enabled) {
max_latency = LNL_PKG_C_LATENCY_MASK;
added_wake_time = 0;
} else {
if (enable_dpkgc) {
max_latency = skl_watermark_max_latency(i915, 1);
if (max_latency == 0)
max_latency = LNL_PKG_C_LATENCY_MASK;
added_wake_time = DSB_EXE_TIME +
i915->display.sagv.block_time_us;
} else {
max_latency = LNL_PKG_C_LATENCY_MASK;
added_wake_time = 0;
}
clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
@ -2873,7 +2873,7 @@ skl_compute_wm(struct intel_atomic_state *state)
struct intel_crtc *crtc;
struct intel_crtc_state __maybe_unused *new_crtc_state;
int ret, i;
bool vrr_enabled = false;
bool enable_dpkgc = false;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
ret = skl_build_pipe_wm(state, crtc);
@ -2899,11 +2899,13 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
if (new_crtc_state->vrr.enable)
vrr_enabled = true;
if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) ||
!new_crtc_state->vrr.enable)
enable_dpkgc = true;
}
skl_program_dpkgc_latency(to_i915(state->base.dev), vrr_enabled);
skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc);
skl_print_wm_changes(state);

5
drivers/gpu/drm/i915/display/vlv_dsi.c
View File

@ -1880,6 +1880,7 @@ static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = {
void vlv_dsi_init(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct intel_dsi *intel_dsi;
struct intel_encoder *encoder;
struct intel_connector *connector;
@ -1891,7 +1892,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "\n");
/* There is no detection method for MIPI so rely on VBT */
if (!intel_bios_is_dsi_present(dev_priv, &port))
if (!intel_bios_is_dsi_present(display, &port))
return;
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
@ -1946,7 +1947,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
intel_dsi->panel_power_off_time = ktime_get_boottime();
intel_bios_init_panel_late(dev_priv, &connector->panel, NULL, NULL);
intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);
if (connector->panel.vbt.dsi.config->dual_link)
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);

28
drivers/gpu/drm/i915/gvt/edid.c
View File

@ -42,8 +42,8 @@
#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
#define gmbus1_total_byte_count(v) (((v) >> \
GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
#define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
#define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
#define gmbus1_target_addr(v) (((v) & 0xff) >> 1)
#define gmbus1_target_index(v) (((v) >> 8) & 0xff)
#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
/* GMBUS0 bits definitions */
@ -54,7 +54,7 @@ static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
unsigned char chr = 0;
if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
if (edid->state == I2C_NOT_SPECIFIED || !edid->target_selected) {
gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
return 0;
}
@ -179,7 +179,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
u32 slave_addr;
u32 target_addr;
u32 wvalue = *(u32 *)p_data;
if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
@ -210,21 +210,21 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
i2c_edid->gmbus.total_byte_count =
gmbus1_total_byte_count(wvalue);
slave_addr = gmbus1_slave_addr(wvalue);
target_addr = gmbus1_target_addr(wvalue);
/* vgpu gmbus only support EDID */
if (slave_addr == EDID_ADDR) {
i2c_edid->slave_selected = true;
} else if (slave_addr != 0) {
if (target_addr == EDID_ADDR) {
i2c_edid->target_selected = true;
} else if (target_addr != 0) {
gvt_dbg_dpy(
"vgpu%d: unsupported gmbus slave addr(0x%x)\n"
"vgpu%d: unsupported gmbus target addr(0x%x)\n"
" gmbus operations will be ignored.\n",
vgpu->id, slave_addr);
vgpu->id, target_addr);
}
if (wvalue & GMBUS_CYCLE_INDEX)
i2c_edid->current_edid_read =
gmbus1_slave_index(wvalue);
gmbus1_target_index(wvalue);
i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
switch (gmbus1_bus_cycle(wvalue)) {
@ -523,7 +523,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
} else if (addr == EDID_ADDR) {
i2c_edid->state = I2C_AUX_CH;
i2c_edid->port = port_idx;
i2c_edid->slave_selected = true;
i2c_edid->target_selected = true;
if (intel_vgpu_has_monitor_on_port(vgpu,
port_idx) &&
intel_vgpu_port_is_dp(vgpu, port_idx))
@ -542,7 +542,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
return;
if (drm_WARN_ON(&i915->drm, msg_length != 4))
return;
if (i2c_edid->edid_available && i2c_edid->slave_selected) {
if (i2c_edid->edid_available && i2c_edid->target_selected) {
unsigned char val = edid_get_byte(vgpu);
aux_data_for_write = (val << 16);
@ -571,7 +571,7 @@ void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
edid->state = I2C_NOT_SPECIFIED;
edid->port = -1;
edid->slave_selected = false;
edid->target_selected = false;
edid->edid_available = false;
edid->current_edid_read = 0;

4
drivers/gpu/drm/i915/gvt/edid.h
View File

@ -80,7 +80,7 @@ enum gmbus_cycle_type {
* R/W Protect
* Command and Status.
* bit0 is the direction bit: 1 is read; 0 is write.
* bit1 - bit7 is slave 7-bit address.
* bit1 - bit7 is target 7-bit address.
* bit16 - bit24 total byte count (ignore?)
*
* GMBUS2:
@ -130,7 +130,7 @@ struct intel_vgpu_i2c_edid {
enum i2c_state state;
unsigned int port;
bool slave_selected;
bool target_selected;
bool edid_available;
unsigned int current_edid_read;

2
drivers/gpu/drm/i915/gvt/opregion.c
View File

@ -86,7 +86,7 @@ struct efp_child_device_config {
u8 skip2;
u8 dvo_port;
u8 i2c_pin; /* for add-in card */
u8 slave_addr; /* for add-in card */
u8 target_addr; /* for add-in card */
u8 ddc_pin;
u16 edid_ptr;
u8 dvo_config;

2
drivers/gpu/drm/i915/gvt/trace.h
View File

@ -227,7 +227,7 @@ TRACE_EVENT(oos_sync,
#define GVT_CMD_STR_LEN 40
TRACE_EVENT(gvt_command,
TP_PROTO(u8 vgpu_id, u8 ring_id, u32 ip_gma, u32 *cmd_va,
u32 cmd_len, u32 buf_type, u32 buf_addr_type,
u32 cmd_len, u32 buf_type, u32 buf_addr_type,
void *workload, const char *cmd_name),
TP_ARGS(vgpu_id, ring_id, ip_gma, cmd_va, cmd_len, buf_type,

36
drivers/gpu/drm/i915/i915_driver.c
View File

@ -442,6 +442,7 @@ static int i915_pcode_init(struct drm_i915_private *i915)
*/
static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
int ret;
@ -451,8 +452,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (HAS_PPGTT(dev_priv)) {
if (intel_vgpu_active(dev_priv) &&
!intel_vgpu_has_full_ppgtt(dev_priv)) {
i915_report_error(dev_priv,
"incompatible vGPU found, support for isolated ppGTT required\n");
drm_err(&dev_priv->drm,
"incompatible vGPU found, support for isolated ppGTT required\n");
return -ENXIO;
}
}
@ -465,8 +466,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
*/
if (intel_vgpu_active(dev_priv) &&
!intel_vgpu_has_hwsp_emulation(dev_priv)) {
i915_report_error(dev_priv,
"old vGPU host found, support for HWSP emulation required\n");
drm_err(&dev_priv->drm,
"old vGPU host found, support for HWSP emulation required\n");
return -ENXIO;
}
}
@ -542,7 +543,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_msi;
intel_opregion_setup(dev_priv);
intel_opregion_setup(display);
ret = i915_pcode_init(dev_priv);
if (ret)
@ -559,7 +560,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
return 0;
err_opregion:
intel_opregion_cleanup(dev_priv);
intel_opregion_cleanup(display);
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
@ -580,11 +581,12 @@ err_perf:
*/
static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
i915_perf_fini(dev_priv);
intel_opregion_cleanup(dev_priv);
intel_opregion_cleanup(display);
if (pdev->msi_enabled)
pci_disable_msi(pdev);
@ -1014,6 +1016,7 @@ static int i915_drm_prepare(struct drm_device *dev)
static int i915_drm_suspend(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_display *display = &dev_priv->display;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
pci_power_t opregion_target_state;
@ -1049,7 +1052,7 @@ static int i915_drm_suspend(struct drm_device *dev)
i915_save_display(dev_priv);
opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
intel_opregion_suspend(dev_priv, opregion_target_state);
intel_opregion_suspend(display, opregion_target_state);
dev_priv->suspend_count++;
@ -1138,6 +1141,7 @@ int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
static int i915_drm_resume(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_display *display = &dev_priv->display;
struct intel_gt *gt;
int ret, i;
@ -1205,7 +1209,7 @@ static int i915_drm_resume(struct drm_device *dev)
}
intel_hpd_poll_disable(dev_priv);
intel_opregion_resume(dev_priv);
intel_opregion_resume(display);
intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
@ -1454,6 +1458,7 @@ static int i915_pm_restore(struct device *kdev)
static int intel_runtime_suspend(struct device *kdev)
{
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
struct intel_display *display = &dev_priv->display;
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct pci_dev *root_pdev;
@ -1528,7 +1533,7 @@ static int intel_runtime_suspend(struct device *kdev)
* won't be able to restore them. Since PCI_D3hot matches the
* actual specification and appears to be working, use it.
*/
intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
intel_opregion_notify_adapter(display, PCI_D3hot);
} else {
/*
* current versions of firmware which depend on this opregion
@ -1537,7 +1542,7 @@ static int intel_runtime_suspend(struct device *kdev)
* to distinguish it from notifications that might be sent via
* the suspend path.
*/
intel_opregion_notify_adapter(dev_priv, PCI_D1);
intel_opregion_notify_adapter(display, PCI_D1);
}
assert_forcewakes_inactive(&dev_priv->uncore);
@ -1552,6 +1557,7 @@ static int intel_runtime_suspend(struct device *kdev)
static int intel_runtime_resume(struct device *kdev)
{
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
struct intel_display *display = &dev_priv->display;
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct pci_dev *root_pdev;
@ -1566,7 +1572,7 @@ static int intel_runtime_resume(struct device *kdev)
drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
disable_rpm_wakeref_asserts(rpm);
intel_opregion_notify_adapter(dev_priv, PCI_D0);
intel_opregion_notify_adapter(display, PCI_D0);
root_pdev = pcie_find_root_port(pdev);
if (root_pdev)
@ -1693,9 +1699,9 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

3
drivers/gpu/drm/i915/i915_drv.h
View File

@ -678,9 +678,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
})
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
(IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)

6
drivers/gpu/drm/i915/i915_pci.c
View File

@ -880,7 +880,7 @@ static void i915_pci_remove(struct pci_dev *pdev)
{
struct drm_i915_private *i915;
i915 = pci_get_drvdata(pdev);
i915 = pdev_to_i915(pdev);
if (!i915) /* driver load aborted, nothing to cleanup */
return;
@ -1003,7 +1003,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (err)
return err;
if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
if (i915_inject_probe_failure(pdev_to_i915(pdev))) {
i915_pci_remove(pdev);
return -ENODEV;
}
@ -1025,7 +1025,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
static void i915_pci_shutdown(struct pci_dev *pdev)
{
struct drm_i915_private *i915 = pci_get_drvdata(pdev);
struct drm_i915_private *i915 = pdev_to_i915(pdev);
i915_driver_shutdown(i915);
}

2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2396,6 +2396,7 @@
/* Display Internal Timeout Register */
#define RM_TIMEOUT _MMIO(0x42060)
#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
/* interrupts */
@ -2574,6 +2575,7 @@
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
#define XELPDP_RM_TIMEOUT REG_BIT(29)
#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
#define GEN8_DE_MISC_GSE REG_BIT(27)
#define GEN8_DE_EDP_PSR REG_BIT(19)

4
drivers/gpu/drm/i915/i915_sysfs.c
View File

@ -191,8 +191,8 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
i915_gpu_error_sysfs_teardown(dev_priv);
device_remove_bin_file(kdev, &dpf_attrs_1);
device_remove_bin_file(kdev, &dpf_attrs);
device_remove_bin_file(kdev, &dpf_attrs_1);
device_remove_bin_file(kdev, &dpf_attrs);
kobject_put(dev_priv->sysfs_gt);
}

51
drivers/gpu/drm/i915/i915_utils.c
View File

@ -11,51 +11,10 @@
#include "i915_reg.h"
#include "i915_utils.h"
#define FDO_BUG_MSG "Please file a bug on drm/i915; see " FDO_BUG_URL " for details."
void
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
const char *fmt, ...)
{
static bool shown_bug_once;
struct device *kdev = dev_priv->drm.dev;
bool is_error = level[1] <= KERN_ERR[1];
bool is_debug = level[1] == KERN_DEBUG[1];
struct va_format vaf;
va_list args;
if (is_debug && !drm_debug_enabled(DRM_UT_DRIVER))
return;
va_start(args, fmt);
vaf.fmt = fmt;
vaf.va = &args;
if (is_error)
dev_printk(level, kdev, "%pV", &vaf);
else
dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
__builtin_return_address(0), &vaf);
va_end(args);
if (is_error && !shown_bug_once) {
/*
* Ask the user to file a bug report for the error, except
* if they may have caused the bug by fiddling with unsafe
* module parameters.
*/
if (!test_taint(TAINT_USER))
dev_notice(kdev, "%s", FDO_BUG_MSG);
shown_bug_once = true;
}
}
void add_taint_for_CI(struct drm_i915_private *i915, unsigned int taint)
{
__i915_printk(i915, KERN_NOTICE, "CI tainted:%#x by %pS\n",
taint, (void *)_RET_IP_);
drm_notice(&i915->drm, "CI tainted: %#x by %pS\n",
taint, __builtin_return_address(0));
/* Failures that occur during fault injection testing are expected */
if (!i915_error_injected())
@ -74,9 +33,9 @@ int __i915_inject_probe_error(struct drm_i915_private *i915, int err,
if (++i915_probe_fail_count < i915_modparams.inject_probe_failure)
return 0;
__i915_printk(i915, KERN_INFO,
"Injecting failure %d at checkpoint %u [%s:%d]\n",
err, i915_modparams.inject_probe_failure, func, line);
drm_info(&i915->drm, "Injecting failure %d at checkpoint %u [%s:%d]\n",
err, i915_modparams.inject_probe_failure, func, line);
i915_modparams.inject_probe_failure = 0;
return err;
}

16
drivers/gpu/drm/i915/i915_utils.h
View File

@ -45,13 +45,6 @@ struct timer_list;
#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
__stringify(x), (long)(x))
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
const char *fmt, ...);
#define i915_report_error(dev_priv, fmt, ...) \
__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
int __i915_inject_probe_error(struct drm_i915_private *i915, int err,
@ -69,9 +62,12 @@ bool i915_error_injected(void);
#define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV)
#define i915_probe_error(i915, fmt, ...) \
__i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
fmt, ##__VA_ARGS__)
#define i915_probe_error(i915, fmt, ...) ({ \
if (i915_error_injected()) \
drm_dbg(&(i915)->drm, fmt, ##__VA_ARGS__); \
else \
drm_err(&(i915)->drm, fmt, ##__VA_ARGS__); \
})
#define range_overflows(start, size, max) ({ \
typeof(start) start__ = (start); \

20
drivers/gpu/drm/xe/display/xe_display.c
View File

@ -127,15 +127,18 @@ int xe_display_init_nommio(struct xe_device *xe)
static void xe_display_fini_noirq(void *arg)
{
struct xe_device *xe = arg;
struct intel_display *display = &xe->display;
if (!xe->info.enable_display)
return;
intel_display_driver_remove_noirq(xe);
intel_opregion_cleanup(display);
}
int xe_display_init_noirq(struct xe_device *xe)
{
struct intel_display *display = &xe->display;
int err;
if (!xe->info.enable_display)
@ -144,7 +147,7 @@ int xe_display_init_noirq(struct xe_device *xe)
intel_display_driver_early_probe(xe);
/* Early display init.. */
intel_opregion_setup(xe);
intel_opregion_setup(display);
/*
* Fill the dram structure to get the system dram info. This will be
@ -157,8 +160,10 @@ int xe_display_init_noirq(struct xe_device *xe)
intel_display_device_info_runtime_init(xe);
err = intel_display_driver_probe_noirq(xe);
if (err)
if (err) {
intel_opregion_cleanup(display);
return err;
}
return devm_add_action_or_reset(xe->drm.dev, xe_display_fini_noirq, xe);
}
@ -247,11 +252,13 @@ void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)
void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)
{
struct intel_display *display = &xe->display;
if (!xe->info.enable_display)
return;
if (gu_misc_iir & GU_MISC_GSE)
intel_opregion_asle_intr(xe);
intel_opregion_asle_intr(display);
}
void xe_display_irq_reset(struct xe_device *xe)
@ -282,6 +289,7 @@ static bool suspend_to_idle(void)
void xe_display_pm_suspend(struct xe_device *xe, bool runtime)
{
struct intel_display *display = &xe->display;
bool s2idle = suspend_to_idle();
if (!xe->info.enable_display)
return;
@ -303,7 +311,7 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime)
intel_encoder_suspend_all(&xe->display);
intel_opregion_suspend(xe, s2idle ? PCI_D1 : PCI_D3cold);
intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold);
intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);
@ -333,6 +341,8 @@ void xe_display_pm_resume_early(struct xe_device *xe)
void xe_display_pm_resume(struct xe_device *xe, bool runtime)
{
struct intel_display *display = &xe->display;
if (!xe->info.enable_display)
return;
@ -353,7 +363,7 @@ void xe_display_pm_resume(struct xe_device *xe, bool runtime)
if (has_display(xe))
drm_kms_helper_poll_enable(&xe->drm);
intel_opregion_resume(xe);
intel_opregion_resume(display);
intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_RUNNING, false);

8
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
View File

@ -40,10 +40,14 @@ bool intel_hdcp_gsc_check_status(struct xe_device *xe)
{
struct xe_tile *tile = xe_device_get_root_tile(xe);
struct xe_gt *gt = tile->media_gt;
struct xe_gsc *gsc = &gt->uc.gsc;
bool ret = true;
if (!xe_uc_fw_is_enabled(&gt->uc.gsc.fw))
if (!gsc && !xe_uc_fw_is_enabled(&gsc->fw)) {
drm_dbg_kms(&xe->drm,
"GSC Components not ready for HDCP2.x\n");
return false;
}
xe_pm_runtime_get(xe);
if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC)) {
@ -53,7 +57,7 @@ bool intel_hdcp_gsc_check_status(struct xe_device *xe)
goto out;
}
if (!xe_gsc_proxy_init_done(&gt->uc.gsc))
if (!xe_gsc_proxy_init_done(gsc))
ret = false;
xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);

2
include/drm/display/drm_dp_mst_helper.h
View File

@ -885,6 +885,8 @@ int drm_dp_check_act_status(struct drm_dp_mst_topology_mgr *mgr);
void drm_dp_mst_dump_topology(struct seq_file *m,
struct drm_dp_mst_topology_mgr *mgr);
void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr);
void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr);
int __must_check
drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr,