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RISC-V Fixes for 6.0-rc7
* A handful of build fixes for the T-Head errata, including some functional issues the compilers found. * A fix for a nasty sigreturn bug. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmMtlZYTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYifj4EAC/POyM8gOYkiaaAgMvjeNTiJYdvBq/ ZuWBpnmDfayXyg+OHRpe2EQDJL51oDLA0LejN3V0C3fMOA1/zvrb/2LGbwd8v3Ly i/Lm9/18P6MJo3vSZ0A5DEOZKj41QsoGd5PIn8uuYT8nYQhCtm2g2ug8lX5Eb3QH pI9xjYZWI3nJ8/ah7NOrtB7LWan8BZdH6VuPBKN6zbG466Td7jT3QFQuyw4Ri0Lk rbMifm985EUEs/o9X+ObXmi+5M1PoAw+DVMeFq7VkgkHHBwCuVBlEd80wT6wT//1 qSPQh5i/zs7GT5o8fgRQ+VJCLBh2s3meIFPa3TZ+fkh17w8Ww7tx+NtcOFgp6jWP NcPsaF8tokOwNVJNbFdCjXRAHxc6TuZ8hfjj+IsDxxbit9BMVSXdEpeOjURbLCNX HI3qooTCIBYh+9CzK3dF+ep0dnGC/awBnoLoH8UgNVxmitSVyc5PgR4w3NBpjoO8 Htxl1ESll8nIXam6Rzi0UHgDgmMCRNdrW6vil/QD9UNcBYbkrUWhD/PmTfH+2uYC UtfzVCnXpeDRkLbNxBMwBGSsb/kMl1hkHcMbXRRgIQRxzqRPs69K8umcc6Xy+3AB timl5kzIeGid0nFG1+H67uGjc8Ea0RW3awel2Y8PmCGJDUNMBmKlizqrwMDfZrB0 HxxG8vcuPF7zWg== =9l0i -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - A handful of build fixes for the T-Head errata, including some functional issues the compilers found - A fix for a nasty sigreturn bug * tag 'riscv-for-linus-6.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: RISC-V: Avoid coupling the T-Head CMOs and Zicbom riscv: fix a nasty sigreturn bug... riscv: make t-head erratas depend on MMU riscv: fix RISCV_ISA_SVPBMT kconfig dependency warning RISC-V: Clean up the Zicbom block size probing
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commit
a7b7751aeb
@ -386,6 +386,7 @@ config RISCV_ISA_C
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config RISCV_ISA_SVPBMT
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bool "SVPBMT extension support"
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depends on 64BIT && MMU
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depends on !XIP_KERNEL
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select RISCV_ALTERNATIVE
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default y
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help
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@ -46,7 +46,7 @@ config ERRATA_THEAD
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config ERRATA_THEAD_PBMT
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bool "Apply T-Head memory type errata"
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depends on ERRATA_THEAD && 64BIT
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depends on ERRATA_THEAD && 64BIT && MMU
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select RISCV_ALTERNATIVE_EARLY
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default y
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help
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@ -57,7 +57,7 @@ config ERRATA_THEAD_PBMT
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config ERRATA_THEAD_CMO
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bool "Apply T-Head cache management errata"
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depends on ERRATA_THEAD
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depends on ERRATA_THEAD && MMU
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select RISCV_DMA_NONCOHERENT
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default y
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help
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@ -37,6 +37,7 @@ static bool errata_probe_cmo(unsigned int stage,
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if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
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return false;
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riscv_cbom_block_size = L1_CACHE_BYTES;
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riscv_noncoherent_supported();
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return true;
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#else
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@ -42,6 +42,11 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
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#endif /* CONFIG_SMP */
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/*
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* The T-Head CMO errata internally probe the CBOM block size, but otherwise
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* don't depend on Zicbom.
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*/
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extern unsigned int riscv_cbom_block_size;
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#ifdef CONFIG_RISCV_ISA_ZICBOM
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void riscv_init_cbom_blocksize(void);
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#else
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@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p)
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setup_smp();
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#endif
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riscv_fill_hwcap();
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riscv_init_cbom_blocksize();
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riscv_fill_hwcap();
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apply_boot_alternatives();
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}
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@ -124,6 +124,8 @@ SYSCALL_DEFINE0(rt_sigreturn)
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if (restore_altstack(&frame->uc.uc_stack))
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goto badframe;
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regs->cause = -1UL;
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return regs->a0;
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badframe:
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@ -12,7 +12,7 @@
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#include <linux/of_device.h>
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#include <asm/cacheflush.h>
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static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
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unsigned int riscv_cbom_block_size;
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static bool noncoherent_supported;
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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@ -79,38 +79,41 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
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void riscv_init_cbom_blocksize(void)
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{
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struct device_node *node;
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unsigned long cbom_hartid;
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u32 val, probed_block_size;
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int ret;
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u32 val;
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probed_block_size = 0;
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for_each_of_cpu_node(node) {
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unsigned long hartid;
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int cbom_hartid;
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ret = riscv_of_processor_hartid(node, &hartid);
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if (ret)
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continue;
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if (hartid < 0)
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continue;
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/* set block-size for cbom extension if available */
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ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
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if (ret)
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continue;
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if (!riscv_cbom_block_size) {
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riscv_cbom_block_size = val;
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if (!probed_block_size) {
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probed_block_size = val;
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cbom_hartid = hartid;
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} else {
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if (riscv_cbom_block_size != val)
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pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
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if (probed_block_size != val)
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pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
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cbom_hartid, hartid);
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}
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}
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if (probed_block_size)
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riscv_cbom_block_size = probed_block_size;
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}
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#endif
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void riscv_noncoherent_supported(void)
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{
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WARN(!riscv_cbom_block_size,
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"Non-coherent DMA support enabled without a block size\n");
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noncoherent_supported = true;
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}
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