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dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280

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The camera clock controller clock provider have a bunch of generic
properties that are needed in a device tree. Add the CAMCC clock IDs for
camera client to request for the clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1633567425-11953-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Taniya Das 2021-10-07 06:13:44 +05:30 committed by Stephen Boyd
parent 4ab43d1711
commit a764e1ed50
2 changed files with 198 additions and 0 deletions
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71
Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SC7280.
See also dt-bindings/clock/qcom,camcc-sc7280.h
properties:
compatible:
const: qcom,sc7280-camcc
clocks:
items:
- description: Board XO source
- description: Board XO active source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0x0ad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

127
include/dt-bindings/clock/qcom,camcc-sc7280.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC7280_H
/* CAM_CC clocks */
#define CAM_CC_PLL0 0
#define CAM_CC_PLL0_OUT_EVEN 1
#define CAM_CC_PLL0_OUT_ODD 2
#define CAM_CC_PLL1 3
#define CAM_CC_PLL1_OUT_EVEN 4
#define CAM_CC_PLL2 5
#define CAM_CC_PLL2_OUT_AUX 6
#define CAM_CC_PLL2_OUT_AUX2 7
#define CAM_CC_PLL3 8
#define CAM_CC_PLL3_OUT_EVEN 9
#define CAM_CC_PLL4 10
#define CAM_CC_PLL4_OUT_EVEN 11
#define CAM_CC_PLL5 12
#define CAM_CC_PLL5_OUT_EVEN 13
#define CAM_CC_PLL6 14
#define CAM_CC_PLL6_OUT_EVEN 15
#define CAM_CC_PLL6_OUT_ODD 16
#define CAM_CC_BPS_AHB_CLK 17
#define CAM_CC_BPS_AREG_CLK 18
#define CAM_CC_BPS_AXI_CLK 19
#define CAM_CC_BPS_CLK 20
#define CAM_CC_BPS_CLK_SRC 21
#define CAM_CC_CAMNOC_AXI_CLK 22
#define CAM_CC_CAMNOC_AXI_CLK_SRC 23
#define CAM_CC_CAMNOC_DCD_XO_CLK 24
#define CAM_CC_CCI_0_CLK 25
#define CAM_CC_CCI_0_CLK_SRC 26
#define CAM_CC_CCI_1_CLK 27
#define CAM_CC_CCI_1_CLK_SRC 28
#define CAM_CC_CORE_AHB_CLK 29
#define CAM_CC_CPAS_AHB_CLK 30
#define CAM_CC_CPHY_RX_CLK_SRC 31
#define CAM_CC_CSI0PHYTIMER_CLK 32
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 33
#define CAM_CC_CSI1PHYTIMER_CLK 34
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 35
#define CAM_CC_CSI2PHYTIMER_CLK 36
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 37
#define CAM_CC_CSI3PHYTIMER_CLK 38
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 39
#define CAM_CC_CSI4PHYTIMER_CLK 40
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 41
#define CAM_CC_CSIPHY0_CLK 42
#define CAM_CC_CSIPHY1_CLK 43
#define CAM_CC_CSIPHY2_CLK 44
#define CAM_CC_CSIPHY3_CLK 45
#define CAM_CC_CSIPHY4_CLK 46
#define CAM_CC_FAST_AHB_CLK_SRC 47
#define CAM_CC_GDSC_CLK 48
#define CAM_CC_ICP_AHB_CLK 49
#define CAM_CC_ICP_CLK 50
#define CAM_CC_ICP_CLK_SRC 51
#define CAM_CC_IFE_0_AXI_CLK 52
#define CAM_CC_IFE_0_CLK 53
#define CAM_CC_IFE_0_CLK_SRC 54
#define CAM_CC_IFE_0_CPHY_RX_CLK 55
#define CAM_CC_IFE_0_CSID_CLK 56
#define CAM_CC_IFE_0_CSID_CLK_SRC 57
#define CAM_CC_IFE_0_DSP_CLK 58
#define CAM_CC_IFE_1_AXI_CLK 59
#define CAM_CC_IFE_1_CLK 60
#define CAM_CC_IFE_1_CLK_SRC 61
#define CAM_CC_IFE_1_CPHY_RX_CLK 62
#define CAM_CC_IFE_1_CSID_CLK 63
#define CAM_CC_IFE_1_CSID_CLK_SRC 64
#define CAM_CC_IFE_1_DSP_CLK 65
#define CAM_CC_IFE_2_AXI_CLK 66
#define CAM_CC_IFE_2_CLK 67
#define CAM_CC_IFE_2_CLK_SRC 68
#define CAM_CC_IFE_2_CPHY_RX_CLK 69
#define CAM_CC_IFE_2_CSID_CLK 70
#define CAM_CC_IFE_2_CSID_CLK_SRC 71
#define CAM_CC_IFE_2_DSP_CLK 72
#define CAM_CC_IFE_LITE_0_CLK 73
#define CAM_CC_IFE_LITE_0_CLK_SRC 74
#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 75
#define CAM_CC_IFE_LITE_0_CSID_CLK 76
#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 77
#define CAM_CC_IFE_LITE_1_CLK 78
#define CAM_CC_IFE_LITE_1_CLK_SRC 79
#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 80
#define CAM_CC_IFE_LITE_1_CSID_CLK 81
#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 82
#define CAM_CC_IPE_0_AHB_CLK 83
#define CAM_CC_IPE_0_AREG_CLK 84
#define CAM_CC_IPE_0_AXI_CLK 85
#define CAM_CC_IPE_0_CLK 86
#define CAM_CC_IPE_0_CLK_SRC 87
#define CAM_CC_JPEG_CLK 88
#define CAM_CC_JPEG_CLK_SRC 89
#define CAM_CC_LRME_CLK 90
#define CAM_CC_LRME_CLK_SRC 91
#define CAM_CC_MCLK0_CLK 92
#define CAM_CC_MCLK0_CLK_SRC 93
#define CAM_CC_MCLK1_CLK 94
#define CAM_CC_MCLK1_CLK_SRC 95
#define CAM_CC_MCLK2_CLK 96
#define CAM_CC_MCLK2_CLK_SRC 97
#define CAM_CC_MCLK3_CLK 98
#define CAM_CC_MCLK3_CLK_SRC 99
#define CAM_CC_MCLK4_CLK 100
#define CAM_CC_MCLK4_CLK_SRC 101
#define CAM_CC_MCLK5_CLK 102
#define CAM_CC_MCLK5_CLK_SRC 103
#define CAM_CC_SLEEP_CLK 104
#define CAM_CC_SLEEP_CLK_SRC 105
#define CAM_CC_SLOW_AHB_CLK_SRC 106
#define CAM_CC_XO_CLK_SRC 107
/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC 0
#define CAM_CC_IFE_0_GDSC 1
#define CAM_CC_IFE_1_GDSC 2
#define CAM_CC_IFE_2_GDSC 3
#define CAM_CC_IPE_0_GDSC 4
#define CAM_CC_TITAN_TOP_GDSC 5
#endif