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clock mvebu changes for v3.18 (round 2)
- armada 370/375 - Fix SSCG node lookup -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJULVYpAAoJEP45WPkGe8ZnSOAP/2V3KoDeaINR0cGG/u/YI/hp M5E4nZtRF9rZS3WMhULVjevcoddClDpvSJIvW34ZEI5uWc+kqkq+Q5Jj23t1oczq f5TqRDR2GenvxF1RbNGazZhLUJE6ubV1ADRKZNdRYfwR33RgrjRmWe2xrQ4vpemf 58BSYbYwsrySd6s7KRJaSnSLrhxywPZCaisod4oquZF75cZ3W63V9RugHGADu/SZ gSxU+0bN4nbU8MFQxyaKq94FeyaAoDPkrMiSXAtjPQzl9a4zZd+BD/KArnf5LCs/ kmRUfOQ38p4KIH9W49YRESZdh2/jUO+3hFTSsAKcXid7ZTadSH/WKHC4LCXH5Td6 ST1fq0gGTPwDqULSCguw0n/UgIsn3D3fI3ruXuAAoV1S36Hzsh6n3dhZunfE9V/Y yKjf36GHT6g9a3CV3CEuSY18mLdDvkN9F/4A2mGhVHt11gl0JbaAKPb0D1GWzucP 1N24NqCZ8/tOO4J3wseqvEW0imsZY4GB5CauJr9bgARaZhv2rjks79KExgpoTyk3 ttDMl2JAspcZntHQQxVBGa3buux11SAH4jUdhtJC8BNGFXPo9XThNS2m+shseSJP UDlo6SWSMNohwAcWVSyEGkTHSe7Z2h3+PHDBKB8LwW8he9EIbCsxKJgk+Uz/gq8x 8uMlUwJz1LajKur3+MSP =q4nx -----END PGP SIGNATURE----- Merge tag 'clk-mvebu-3.18-2' of git://git.infradead.org/linux-mvebu into clk-next clock mvebu changes for v3.18 (round 2) - armada 370/375 - Fix SSCG node lookup
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commit
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@ -41,7 +41,7 @@ static struct clk_onecell_data clk_data;
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* chosen following the dt convention: using the first known SoC
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* compatible with it.
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*/
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u32 kirkwood_fix_sscg_deviation(struct device_node *np, u32 system_clk)
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u32 kirkwood_fix_sscg_deviation(u32 system_clk)
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{
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struct device_node *sscg_np = NULL;
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void __iomem *sscg_map;
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@ -49,7 +49,7 @@ u32 kirkwood_fix_sscg_deviation(struct device_node *np, u32 system_clk)
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s32 low_bound, high_bound;
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u64 freq_swing_half;
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sscg_np = of_find_node_by_name(np, "sscg");
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sscg_np = of_find_node_by_name(NULL, "sscg");
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if (sscg_np == NULL) {
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pr_err("cannot get SSCG register node\n");
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return system_clk;
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@ -142,7 +142,7 @@ void __init mvebu_coreclk_setup(struct device_node *np,
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if (desc->is_sscg_enabled && desc->fix_sscg_deviation
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&& desc->is_sscg_enabled(base))
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rate = desc->fix_sscg_deviation(np, rate);
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rate = desc->fix_sscg_deviation(rate);
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clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
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CLK_IS_ROOT, rate);
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@ -31,7 +31,7 @@ struct coreclk_soc_desc {
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u32 (*get_cpu_freq)(void __iomem *sar);
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void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
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bool (*is_sscg_enabled)(void __iomem *sar);
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u32 (*fix_sscg_deviation)(struct device_node *np, u32 system_clk);
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u32 (*fix_sscg_deviation)(u32 system_clk);
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const struct coreclk_ratio *ratios;
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int num_ratios;
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};
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@ -53,5 +53,5 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
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* This function is shared among the Kirkwood, Armada 370, Armada XP
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* and Armada 375 SoC
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*/
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u32 kirkwood_fix_sscg_deviation(struct device_node *np, u32 system_clk);
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u32 kirkwood_fix_sscg_deviation(u32 system_clk);
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#endif
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