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Merge branch 'icc-sm8350' into icc-next
A set of fixes that target stability of the SM8350 platform. * icc-sm8350 interconnect: qcom: sm8350: drop DISP nodes dt-bindings: interconnect: qcom,sm8350: drop DISP nodes interconnect: qcom: sm8250: Enable sync_state Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-0-1149dd8399fe@linaro.org/ Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
commit
a5733950fe
@ -628,60 +628,6 @@ static struct qcom_icc_node xm_gic = {
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.links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
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};
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static struct qcom_icc_node qnm_mnoc_hf_disp = {
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.name = "qnm_mnoc_hf_disp",
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.id = SM8350_MASTER_MNOC_HF_MEM_NOC_DISP,
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.channels = 2,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8350_SLAVE_LLCC_DISP },
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};
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static struct qcom_icc_node qnm_mnoc_sf_disp = {
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.name = "qnm_mnoc_sf_disp",
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.id = SM8350_MASTER_MNOC_SF_MEM_NOC_DISP,
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.channels = 2,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8350_SLAVE_LLCC_DISP },
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};
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static struct qcom_icc_node llcc_mc_disp = {
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.name = "llcc_mc_disp",
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.id = SM8350_MASTER_LLCC_DISP,
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.channels = 4,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8350_SLAVE_EBI1_DISP },
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};
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static struct qcom_icc_node qxm_mdp0_disp = {
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.name = "qxm_mdp0_disp",
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.id = SM8350_MASTER_MDP0_DISP,
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.channels = 1,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
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};
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static struct qcom_icc_node qxm_mdp1_disp = {
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.name = "qxm_mdp1_disp",
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.id = SM8350_MASTER_MDP1_DISP,
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.channels = 1,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
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};
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static struct qcom_icc_node qxm_rot_disp = {
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.name = "qxm_rot_disp",
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.id = SM8350_MASTER_ROTATOR_DISP,
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.channels = 1,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP },
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};
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static struct qcom_icc_node qns_a1noc_snoc = {
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.name = "qns_a1noc_snoc",
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.id = SM8350_SLAVE_A1NOC_SNOC,
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@ -1320,40 +1266,6 @@ static struct qcom_icc_node srvc_snoc = {
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.buswidth = 4,
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};
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static struct qcom_icc_node qns_llcc_disp = {
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.name = "qns_llcc_disp",
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.id = SM8350_SLAVE_LLCC_DISP,
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.channels = 4,
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.buswidth = 16,
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.num_links = 1,
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.links = { SM8350_MASTER_LLCC_DISP },
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};
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static struct qcom_icc_node ebi_disp = {
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.name = "ebi_disp",
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.id = SM8350_SLAVE_EBI1_DISP,
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.channels = 4,
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.buswidth = 4,
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};
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static struct qcom_icc_node qns_mem_noc_hf_disp = {
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.name = "qns_mem_noc_hf_disp",
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.id = SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP,
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.channels = 2,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP },
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};
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static struct qcom_icc_node qns_mem_noc_sf_disp = {
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.name = "qns_mem_noc_sf_disp",
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.id = SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP,
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.channels = 2,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP },
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};
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static struct qcom_icc_bcm bcm_acv = {
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.name = "ACV",
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.enable_mask = BIT(3),
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@ -1583,55 +1495,6 @@ static struct qcom_icc_bcm bcm_sn14 = {
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.nodes = { &qns_pcie_mem_noc },
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};
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static struct qcom_icc_bcm bcm_acv_disp = {
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.name = "ACV",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &ebi_disp },
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};
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static struct qcom_icc_bcm bcm_mc0_disp = {
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.name = "MC0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &ebi_disp },
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};
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static struct qcom_icc_bcm bcm_mm0_disp = {
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.name = "MM0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_hf_disp },
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};
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static struct qcom_icc_bcm bcm_mm1_disp = {
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.name = "MM1",
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.keepalive = false,
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.num_nodes = 2,
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.nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp },
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};
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static struct qcom_icc_bcm bcm_mm4_disp = {
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.name = "MM4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_sf_disp },
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};
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static struct qcom_icc_bcm bcm_mm5_disp = {
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.name = "MM5",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxm_rot_disp },
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};
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static struct qcom_icc_bcm bcm_sh0_disp = {
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.name = "SH0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_llcc_disp },
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};
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static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
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};
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@ -1785,7 +1648,6 @@ static struct qcom_icc_bcm * const gem_noc_bcms[] = {
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&bcm_sh2,
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&bcm_sh3,
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&bcm_sh4,
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&bcm_sh0_disp,
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};
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static struct qcom_icc_node * const gem_noc_nodes[] = {
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@ -1808,9 +1670,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
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[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
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[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
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[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
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[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
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[MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
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[SLAVE_LLCC_DISP] = &qns_llcc_disp,
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};
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static const struct qcom_icc_desc sm8350_gem_noc = {
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@ -1843,15 +1702,11 @@ static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
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static struct qcom_icc_bcm * const mc_virt_bcms[] = {
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&bcm_acv,
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&bcm_mc0,
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&bcm_acv_disp,
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&bcm_mc0_disp,
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};
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static struct qcom_icc_node * const mc_virt_nodes[] = {
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[MASTER_LLCC] = &llcc_mc,
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[SLAVE_EBI1] = &ebi,
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[MASTER_LLCC_DISP] = &llcc_mc_disp,
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[SLAVE_EBI1_DISP] = &ebi_disp,
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};
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static const struct qcom_icc_desc sm8350_mc_virt = {
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@ -1866,10 +1721,6 @@ static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
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&bcm_mm1,
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&bcm_mm4,
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&bcm_mm5,
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&bcm_mm0_disp,
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&bcm_mm1_disp,
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&bcm_mm4_disp,
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&bcm_mm5_disp,
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};
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static struct qcom_icc_node * const mmss_noc_nodes[] = {
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@ -1886,11 +1737,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
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[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
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[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
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[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
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[MASTER_MDP0_DISP] = &qxm_mdp0_disp,
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[MASTER_MDP1_DISP] = &qxm_mdp1_disp,
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[MASTER_ROTATOR_DISP] = &qxm_rot_disp,
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[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
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[SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
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};
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static const struct qcom_icc_desc sm8350_mmss_noc = {
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@ -1965,6 +1811,7 @@ static struct platform_driver qnoc_driver = {
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.driver = {
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.name = "qnoc-sm8350",
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.of_match_table = qnoc_of_match,
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.sync_state = icc_sync_state,
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},
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};
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module_platform_driver(qnoc_driver);
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@ -154,15 +154,5 @@
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#define SM8350_SLAVE_PCIE_1 143
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#define SM8350_SLAVE_QDSS_STM 144
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#define SM8350_SLAVE_TCU 145
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#define SM8350_MASTER_LLCC_DISP 146
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#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP 147
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#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP 148
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#define SM8350_MASTER_MDP0_DISP 149
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#define SM8350_MASTER_MDP1_DISP 150
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#define SM8350_MASTER_ROTATOR_DISP 151
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#define SM8350_SLAVE_EBI1_DISP 152
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#define SM8350_SLAVE_LLCC_DISP 153
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#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP 154
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#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP 155
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#endif
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@ -119,9 +119,6 @@
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#define SLAVE_SERVICE_GEM_NOC_1 16
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#define SLAVE_SERVICE_GEM_NOC_2 17
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#define SLAVE_SERVICE_GEM_NOC 18
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#define MASTER_MNOC_HF_MEM_NOC_DISP 19
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#define MASTER_MNOC_SF_MEM_NOC_DISP 20
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#define SLAVE_LLCC_DISP 21
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#define MASTER_CNOC_LPASS_AG_NOC 0
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#define SLAVE_LPASS_CORE_CFG 1
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@ -133,8 +130,6 @@
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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#define MASTER_LLCC_DISP 2
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#define SLAVE_EBI1_DISP 3
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#define MASTER_CAMNOC_HF 0
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#define MASTER_CAMNOC_ICP 1
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@ -149,11 +144,6 @@
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#define SLAVE_MNOC_HF_MEM_NOC 10
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#define SLAVE_MNOC_SF_MEM_NOC 11
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#define SLAVE_SERVICE_MNOC 12
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#define MASTER_MDP0_DISP 13
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#define MASTER_MDP1_DISP 14
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#define MASTER_ROTATOR_DISP 15
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#define SLAVE_MNOC_HF_MEM_NOC_DISP 16
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#define SLAVE_MNOC_SF_MEM_NOC_DISP 17
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#define MASTER_CDSP_NOC_CFG 0
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#define MASTER_CDSP_PROC 1
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