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skge: WOL support
Add WOL support for Yukon chipsets in skge device. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
1479d13cb5
commit
a504e64ab4
@ -132,18 +132,93 @@ static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
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}
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/* Wake on Lan only supported on Yukon chips with rev 1 or above */
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static int wol_supported(const struct skge_hw *hw)
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static u32 wol_supported(const struct skge_hw *hw)
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{
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return !((hw->chip_id == CHIP_ID_GENESIS ||
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(hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
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if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev != 0)
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return WAKE_MAGIC | WAKE_PHY;
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else
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return 0;
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}
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static u32 pci_wake_enabled(struct pci_dev *dev)
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{
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int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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u16 value;
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/* If device doesn't support PM Capabilities, but request is to disable
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* wake events, it's a nop; otherwise fail */
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if (!pm)
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return 0;
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pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
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value &= PCI_PM_CAP_PME_MASK;
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value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
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return value != 0;
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}
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static void skge_wol_init(struct skge_port *skge)
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{
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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enum pause_control save_mode;
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u32 ctrl;
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/* Bring hardware out of reset */
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skge_write16(hw, B0_CTST, CS_RST_CLR);
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skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
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skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
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skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
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/* Force to 10/100 skge_reset will re-enable on resume */
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save_mode = skge->flow_control;
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skge->flow_control = FLOW_MODE_SYMMETRIC;
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ctrl = skge->advertising;
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skge->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
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skge_phy_reset(skge);
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skge->flow_control = save_mode;
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skge->advertising = ctrl;
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/* Set GMAC to no flow control and auto update for speed/duplex */
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gma_write16(hw, port, GM_GP_CTRL,
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GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
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GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
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/* Set WOL address */
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memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
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skge->netdev->dev_addr, ETH_ALEN);
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/* Turn on appropriate WOL control bits */
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skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
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ctrl = 0;
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if (skge->wol & WAKE_PHY)
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ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
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else
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ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
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if (skge->wol & WAKE_MAGIC)
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ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
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else
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ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
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ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
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skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
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/* block receiver */
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skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
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}
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static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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{
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struct skge_port *skge = netdev_priv(dev);
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wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
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wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
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wol->supported = wol_supported(skge->hw);
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wol->wolopts = skge->wol;
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}
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static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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@ -151,23 +226,12 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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struct skge_port *skge = netdev_priv(dev);
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struct skge_hw *hw = skge->hw;
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if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
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if (wol->wolopts & wol_supported(hw))
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return -EOPNOTSUPP;
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if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
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return -EOPNOTSUPP;
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skge->wol = wol->wolopts == WAKE_MAGIC;
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if (skge->wol) {
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memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
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skge_write16(hw, WOL_CTRL_STAT,
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WOL_CTL_ENA_PME_ON_MAGIC_PKT |
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WOL_CTL_ENA_MAGIC_PKT_UNIT);
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} else
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skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
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skge->wol = wol->wolopts;
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if (!netif_running(dev))
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skge_wol_init(skge);
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return 0;
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}
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@ -3456,6 +3520,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
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skge->duplex = -1;
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skge->speed = -1;
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skge->advertising = skge_supported_modes(hw);
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skge->wol = pci_wake_enabled(hw->pdev) ? wol_supported(hw) : 0;
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hw->dev[port] = dev;
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@ -3654,28 +3719,46 @@ static void __devexit skge_remove(struct pci_dev *pdev)
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}
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#ifdef CONFIG_PM
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static int vaux_avail(struct pci_dev *pdev)
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{
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int pm_cap;
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pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
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if (pm_cap) {
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u16 ctl;
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pci_read_config_word(pdev, pm_cap + PCI_PM_PMC, &ctl);
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if (ctl & PCI_PM_CAP_AUX_POWER)
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return 1;
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}
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return 0;
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}
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static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct skge_hw *hw = pci_get_drvdata(pdev);
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int i, wol = 0;
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int i, err, wol = 0;
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err = pci_save_state(pdev);
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if (err)
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return err;
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pci_save_state(pdev);
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for (i = 0; i < hw->ports; i++) {
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struct net_device *dev = hw->dev[i];
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struct skge_port *skge = netdev_priv(dev);
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if (netif_running(dev)) {
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struct skge_port *skge = netdev_priv(dev);
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if (netif_running(dev))
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skge_down(dev);
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if (skge->wol)
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skge_wol_init(skge);
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netif_carrier_off(dev);
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if (skge->wol)
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netif_stop_queue(dev);
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else
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skge_down(dev);
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wol |= skge->wol;
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}
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netif_device_detach(dev);
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wol |= skge->wol;
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}
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if (wol && vaux_avail(pdev))
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skge_write8(hw, B0_POWER_CTRL,
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PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
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skge_write32(hw, B0_IMSK, 0);
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pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
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pci_set_power_state(pdev, pci_choose_state(pdev, state));
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@ -3688,8 +3771,14 @@ static int skge_resume(struct pci_dev *pdev)
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struct skge_hw *hw = pci_get_drvdata(pdev);
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int i, err;
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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err = pci_set_power_state(pdev, PCI_D0);
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if (err)
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goto out;
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err = pci_restore_state(pdev);
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if (err)
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goto out;
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pci_enable_wake(pdev, PCI_D0, 0);
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err = skge_reset(hw);
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@ -3699,7 +3788,6 @@ static int skge_resume(struct pci_dev *pdev)
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for (i = 0; i < hw->ports; i++) {
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struct net_device *dev = hw->dev[i];
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netif_device_attach(dev);
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if (netif_running(dev)) {
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err = skge_up(dev);
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@ -876,11 +876,13 @@ enum {
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WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
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WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
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};
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#define WOL_REGS(port, x) (x + (port)*0x80)
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enum {
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WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
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WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
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};
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#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
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enum {
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BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
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